`

`Worldwide Semicondudor Produdion - Vol 37. No. I - A Ponanll Publication
`
`MAREH 1994
`
`FOCUS ON GERMANY
`
`FEATURE“
`
`DEPOSITION
`
`65 “MIM'W'SM
`f0! semiconductorW
`
`Wummm,umuumcm
`Il.ll". FIJ‘JJ’. WW. 5, Per [3.4. [300612, CC. i’il
`Void-tree oxide films are deposited using APCVD with TEOS/ozone diemistries
`7 3 NW K81 Sim mym forsub-half-micron poly-metal isolation (interlayerdielectric), intermetal spaces,
`Gonna! homology to the US
`and isolation trenches
`This section explores some of the unique technology being
`developed in Germany and explains how research results move
`from R&D into commercial production.
`
`43m —What next?
`Ruben I, Saw
`Measurements are mon'ng from the lab to the factory while spedfication of finer target
`properties taxes the limits of metrology. This is forcing new mechan'sms for supplier/
`user collaboration in the semimnducmr industry.
`
`Micromachined rapid AIDS tester.
`
`“no.1” ______________________________________ _ _1o
`iWoI-ld Now.................................. ..12
`
`4 W10»:mmmummmlm
`.Ilum'n Hill. Dielmm' Hellman. iilicbael Roler
`Quartzglass is widely used in semiconductor fabrication for waterboats, process
`tubes, battles for heat and gas distribution, etc. Even though flame-fused (F-type) and
`electric-{med (E-type) materials may have similar metal impurities, lab tests showed
`that E-type material caused more silicon contamination.
`
`Tochnology News .............................22
`‘Iflkot wnch ---------------------------------“26 5
`'
`~- mm m...77
`,E
`P
`I
`I P
`CompaniesthatobtainBOMMfificafionotquahtysystenisexpecttogain
`marketing advantages, espedally in Europe. But the rigorous certification process
`can itself bring insights and improvements, as five companies in semiconductor
`processing demonstrate by describing their enlightening experiences.
`
`MANAGEMENT
`
`PeterxDmm
`
`
`
`Void-freedielectricscanbedepositedbythisZtXmeatmospheric—prmre am1
`vapor deposition reactor using TEOS/ozone chemistries at temperatures from
`350to§50°CSuchproccss<sarevital tormaldngdeepsubrniaonle.TheWatkins
`Johnson wnooo reactor shown eases water transport by enabling atmospheric operating
`pressure in a Class 1 environment.
`Ciu'r {how by ChuckW, minim} of Wetkins—Mmlm
`Industry II‘ICI‘I'I . . . .
`Panama Ilifi.t"'l\, uv =wv'Woti Wig Conwvy 1121 S smxm Rd. Tuna 0K 74! 12 Schism. Tombgy ofloas. Yaw Two 3M1”
`' hm sen {war I
`r in Monte! Assocznm 4
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`-
`r Jilommnmwm 5192mm W7 mmmmm15235‘mm:m76.sn¢m
`(1‘ 4w~wsuasea1N'$ll5mvam “flew-WEST SWIM-Q82) was:
`Jag-(funk)
`mbrKLlnllytlLIl’: mum.-
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`mm H:
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`mfh mmommarvmsdnmtamaovnwmemmurmmmmwwn "swag,de
`m WV:
`‘ Hmirrn; LXWCL'VY', m-
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`mmmr -u
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`tnm wnmiii mum w-mi
`i "nm‘nn' s gin-ism to: those vegetarian Mththe Commit!m Cans Inc WI 21 Congas: &., Sm. MAOer to
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`.
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`Mcmflm 300M MW‘A’IYIW.MlAEH:Q Guru»
`twin-i WMrim/ill,(liuaLsMJRi‘WooMBLO-tusgi ScfidSmI YndwflogymttmwewhminEngm-Mglmmm
`'
`*
`Canon: Cuojerou' Scrum cuss posture in: an Tum OK i'-‘-‘ 12 l. Jodi-moi llhlllll .sr‘iu; MSuumclm-jos to. SclldStm Tm ‘421 5 SWIM” Tum 0K 741 '2.
`
`“ow ' ' ' ' '85
`- W. & Conferences -------------------- -91
`, w maul". _________________________________ 35
`
`Subocflptlon Card ..................... .. 96c
`
`"u'" "m." """"""""""""" "97
`
`‘
`
`.-
`
`Page 2 of 12
`
`larch 1990 Sand State Technology 3
`
`

`

`ULSI IC fabrication
`
`Wallace Fry, Wafkins-lolmson Co., Scotts Valley, California
`y P. West, Stephen Poon, Bruce A. Boock, Chrls c. Yu, Motorola Inc, Austin, Texas
`
`DEPOSITION
`
`Si-(OC2H5)i]. Silane is easily oxidized with oxygen at tempera—
`tures below 450°C and constitutes an explosion hazard in high
`concentration. The TEOS molecule, on the other hand, undergoes
`pyrolysis with oxygen to produce SlOz only at temperatures above
`600°C. Without a strong oxidizer, TEOS is unable to produce SiOz
`films compatible with low-temperature metallization processes.
`The addition of plasma excitation energy (PECVD) can reduce
`the deposition temperature below 450°C for TEOS—based oxides,
`a requirement for interrnetal dielectric (lMD) applications. Al-
`ternatively, ozone (03) can be used as the oxidizer in APCVD
`TEOS processes to enable deposition temperatures compatible
`with lMD processing. Both doped and undoped APCVD
`TEOS/O; films exhibit better conformality and gap-fill capabil-
`ity than PECVD films.
`Low-temperature (<420°C) PECVD TEOS (PEI'EOS) based so;
`films are currently being used as IMDs in multilevel processing
`for devices with CDs as small as 0.65 pm. PETEOS-based films
`exhibit better step coverage than their silane counterparts, but still
`result in void formation between metal lines. Void formation
`
`becomes more severe at reduced geometries and can reduce die
`yield. Silicon dioxide thin films using APCVD TEOS/O; are de-
`posited void-free for sub-half-micrometer dimensions. This article
`will discuss the application and integration of APCVD TEOS/Q;
`for trench fill, poly-metal isolation (i.e., interlayer dielectric),
`and intermetal gap fill (i.e., lMD).
`
`Flow flat.
`The first oxides using TEOS/Oi chemistry in IC manufacturing
`were doped with boron and phosphorus (OcBI‘TEOS) and
`were used to replace silane borophosphosilicatae glass (BPSG) in
`devices with severe topography. Heating after deposition
`causes the doped oxide to flow, improving planarizatjon and film
`quality. The superior step coverage of the TEOS/03 oxide im-
`proves local planarization and produces a void-free dielectric with
`no increase in flow temperature. These doped films have been
`successfully integrated into 4- and 16-Mbit DRAM production
`processes [1].
`Silicide compatibility is driving the allowable furnace
`
`March 199‘ Solid State Technotogy 31
`
`
`
`dielectricsaerequiredforadvanoedlCdevelop-
`v
`‘hmbecat-mecharicalpotistingandtench
`i
`,bothotMtichareessemialfordeepstbmici-om-
`prooossi‘tg.Atnospheric-pressmCVD(APCVD)
`Mylorthostttcatelozono (TEOS/Og) chemistryts
`-
`.
`technologyfordepositingvoid-free oxides. This
`prosontsbasicfitmandprooesscharactertsttmas
`ushehicaltestmdtsforTEOS/anxidesmedfor
`,premetal,andshallowtrenchisolationinsrnatt
`.AnAPCVDoozoneprooessforboron-and
`- TEOStinsproduoesfitmsthatpla-
`atlowtemperaturesandmeettherequirementsof
`
`‘
`
`,t prodioesaoontonnal,mttmn,andstablemdde
`.
`downcomemfionsastighasflmomand
`' mgtoslessthanwmtumeemneelhgaslaw
`‘1'.'l'hetntermetaldielectricgap-fillprooesspro-
`,
`hrlyflinctionato.5—umCMOSIogtcandBtCMos
`r marcutttheadvantagesofattilplasma-
`. CVDTEOSbarfierbetweenTEOS/Qiandthe
`metatareexptoredUndopedAPCVDTEOS/Oa
`'fu’isolafiontenchfillarecharacterizedandtherele-
`Mvmiables evaluated. Wei-behaved transistors
`
`i
`
`isota‘tionatgeometriesdownto05um.
`
`half-micrometer 1C development challenges established
`' -film deposition processes and equipment. Some exist-
`; processes, however, can be extended to future-genera-
`, 103 by altering the chemistry and/ or modifying existing
`» 'tion hardware.
`
`- most common methods for depositing dielectric films
`manufacturing are atmospheric-pressure CVD (APCVD),
`‘ D, and plasma-enhanced CVD (PECVD). Deposition
`. ' tries use a variety of organic and inorganic silicon (Si)
`' materials to produce silicon dioxide (SiOz) based dielectrics.
`'
`majority of CVD SiOz films used in IC fabrication today
`I.
`I u need from silane (Sit-l4) or tetraethylorthosilicate [TEOS,
`
`Page 3 of 12
`
`

`

`Flinn 3. inadequate PEN step coverage aggravated by light meta
`geometries and PECVD PSG “bread loaiing." Poor step coverage aru-
`void formation allow moisture penetration into the active deuce
`
`
`
`
`
`
`shows spectra of an as—deposited film 1 hour after deposition and'
`125 hours after deposition. No change in the asymmetric SiOH
`peak (3650 cm“) or the broad “:0 band (3300—3600 cm" l is ob-
`served. Also, a calibrated production particle detector showed
`neither degradation to the film surface nor an increase in haze
`or scattered light over a 48-hour period.
`Submicrometer development also poses challenges to the
`passivation film deposition processes. The limited step cover
`age of APCVD and PECVD phosphosilicate glass (PSG) oxides
`results in overhanging ("bread loaf”) sidewall profiles that produce
`voids. This inhibits deposition of moisture-impervious l’ECVD
`silicon nitride (PEN) between metal lines (Fig. 3). Inadequate PEN
`step c0verage can lead to early device failure due to moisture pen-
`etration into the active area. Some IC manufacturers are finding
`the APCVD OxBPTEOS film works well for the standard
`oxide/nitride passivation layer [6]. Phosphorus is incorporated
`into the passivation oxide to provide ionic gettering, while
`boron is included to reduce the tensile stress and improve the step
`coverage of the phosphorus—doped TEOS/Og, The extremely con-‘
`formal nature of the APCVD O3zBPTEOS process facilitate!
`sidewall coating with the hermetic PEN.
`
`
`
`Undopod TEOS/O,
`Undoped TEOS/Oa silicon oxides (USG) have the potential {W
`providing flo r-lil<e step coverage and good local planari zali
`Film quality approaches thermal oxide only after a densificati '
`at temperatures incompatible with multilevel metalliyation. Com‘
`pared to spin-on glasses ($065). the TEOS/Oa oxide exhibits lowe'
`shrinkage when exposed to metallization temperatures of 450°C
`Measured shrinkage is less than 3% by volume. A thorough '
`derstanding of TEOS/Os gas phase polymerization could red“
`the required densification temperature and extend USG pm
`technology to 0.25pm manufacturing.
`Oxides deposited from the high-temperature pyrolysis of 113m
`have been thoroughly explored, and the results have been "1‘"
`satisfactory from a gap-fill and cost basis. bow—temperature i»
`.
`TEOS/Oa processes, however, show excellent void—free till ‘0‘
`both trench- and [MD gap-fill applications.
`'
`Dielectric voids are of primary concern for sub-halt-microme ' "
`trench-fill and [MD processing. The mechanical and prowf-5 ’
`tributes of APCVD TEOS/O; thin films have been reported 5‘
`tensively for ozone-to—reactant ratios (Oxzk) below 6:1 l7l-
`"
`properties have also been reported for oxides deposited at 600 " "
`
`
`
`
`
`
`Flynn 1. The surtace angle of a 22 mol% OyBPTEOS oxide after a
`15—min. 850°C anneal in N2 is acceptable for 0.65-um contacts using
`i-Iine lithography.
`
`,_._._k :..1
`2444.4.
`16W “M9
`(“4)
`
`figure 2. FUR spectra of a 22 mol% asideposited 03:BPTEOS
`(a) 1 hour after deposition and (b) 125 hours after deposition. The
`absence of moisture-induced bands between 3300 cm“ and 3650
`cm“ indicates the lack of chemacal degradation.
`
`flow/anneal temperature below 850°C. To meet these require
`ments, oxides have been developed using higher dopant con—
`centrations, allowing lower {low temperatures and improved local
`planari7ation. Figure l is a SEM cross section of a topography test
`structure showing the planarity of an Oa:B[’TEOS oxide. The film
`is heavily doped (total dopant concentration is 22 mol%) and
`achieves very good local planarization (surface angle of 22C for
`a 600mm film deposited over 600—nm steps) after an 850°C,
`15-min anneal. This is satisfactory topography smoothing for pat-
`terning 0.65-pm contacts using i—line lithography [2].
`Increasing dopant concentration and film thickness further
`reduces surface angle and processing temperature. With 27 mol‘7r
`doping, a surface angle of 24° can be achieved with a 15—min 800°C
`flow cycle. Reduction of flow cycle temperatures to 800°C and
`lower is essential to make flow glass planarization compatible
`with salicide processing at CD5 of 0.5 pm and below.
`Highly doped silane BPSG films can be unstable. Moisture is
`absorbed into the film after exposure to air and can cause the
`formation of boric or phosphoric acid crystals on the surface of
`the wafer, which can lead to formation of insoluble BPO; crys-
`tals during the flow process [3—5]. ngBl’I'EOS films have unique
`properties that enable highly doped films to be very stable as
`deposited. Fourier transfomr IR (FTlR) spectra of a 22 mol%
`QuBl’TEOS film indicate no change in moisture content. Figure 2
`
`32 Solid State Technology March 1004
`
`Page 4 of 12
`
`

`

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`Page 5 of 12
`
`allenge was engi-
`j: a seven-axis sys-
`move semiconduc-
`ers to accuracies
`d in microns and
`dians. The solution
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`*- Newport's Klinger
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`

`

`Fly" 4. The substrate sensitivity of TEOS/Od films depends on the
`gas dispersion technology.
`
`
`
`
`Mn 5. IMD structures (a) with and (b) without a PECVD underiayer.
`
`(subatmospheric CVD) for OacR ratios as high as 12.611 [8].
`Both of these studies used a showerhead gas distribution system
`that covers the entire substrate surface simultaneously with a
`TEOS, ozone, and oxygen mixture. Oxides deposited at 032R
`ratios above 13, using showerhead gas dispersion technology,
`result in films that are more sensitive to the underlying surface.
`Figure 4 compares the reduction of the TEOS/Oi deposition rate
`to thermal oxide on silicon using showerhead and linear injec-
`tor gas dispersion systems. The linear gas distribution system,
`which covers only a narrow band across the substrate at any one
`time, reduces the deposition rate differential by 40% com-
`pared to conventional showerhead dispersion and by 10% com-
`pared to a multiple parallel-plate configuration [9]. The fol—
`lowing section examines the undoped APCVD TEOS/O;
`chemistry in a higher O3:R ratio regime, 13:1 to 70:], which is
`possible with the linear gas injector.
`Integrated TEOS/O3 lMD. Figure 5 shows two proposed IMD
`film stacks, one with and one without a PECVD underlayer. In
`both structures, TEOS/Or gap-fill material is capped with a
`thick (>1 .O-pm) dielectric (either SOC or PECVD), which is etched
`away during the planarization step. IMD processing is completed
`with a final PECVD [MD deposition.
`in this study, the
`film is a compressive PETEOS oxide
`that contributes to making the total IMD film stack mildly com-
`pressive, thus raising the cracking threshold of the stack. The
`PECVD underlayer provides a uniform nucleation layer for the
`TEOS/Oa, acts to suppress hillocks and potential via poisoning
`[10,11], and helps control film stress to increase the cracking
`threshold. The PECVD underlayer also protects underlying devias
`from moisture evolving from the [MD at elevated temperatures
`used in subsequent CVD dielectric depositions, metal annealing,
`
`84 Solid State Technology March 19“
`
`
`
`Flam 6. Crack resistance histogram for different IMD stacks ob-
`served at the comers of 200 x 1000-um metal pads. No cracks ap-
`peared in typical device structures
`
`-
`
`and in the packaging processes. Excessive moisture from the i ii
`has been reported to cause hot carrier degradation, indicated
`a reduction in transconductance [12,13].
`=0
`Some of the film characteristics of TEOS/Q; lMDs — p
`larly the low (<400°C) maximum deposition temperature — n
`crease the challenge for successful integration. Film quality :
`i
`stress are Mr) limiting factors related to deposition tempera i’
`_
`Wet etch rates and refractive index are effective indicators of o -
`film quality; films with relatively high etch ratesare porous, a u: I v
`higher concentrations of moisture, and are more loosely b0 - '-
`.vn‘ n-
`As-deposited TEOS/Qz oxides etch 3.4 to 3.bx faster than th-
`in
`oxide in 10:1 buffered-oxide etch (BOE) and 1.5x fastc
`PEFEDS. The refractive index of as—deposited films is 1.445 x 0. l.
`(ellipsometer), reaches a maximum of 1.455 after remaining in i
`for two weeks (40% relative humidity), and declines to 1.
`immediately after a 1000°C rapid thermal anneal (RTA) in '
`tmgen. Shrinkage, another indicator of moisture content and i. 0
`' -
`ity, is 2% after a 1-min, 450°C RTA in nitrogen and 6‘7? after
`2—min RTA at 1000°C.
`
`Compressive dielectric films are deposited to compensate 4‘
`tensile metal films, prevent delamination, and limit the growth ~
`stress‘induced metal Voids. The as-deposited film stress ,
`TEOS/Q; is tensile (300—325 MPa), increases to 440 MPa at
`'
`t ' 9.
`and returns to 300 MPa after cooling to 80C [14].
`Crack-resistance tests were performed for five different | "
`scenarios in a four-level metal structure processed through ' _
`sivation. Cracks were counted using an optical microscope I
`the material was cycled through four fumace anneals (30 mm
`450°C). The only cracks that were observed propagated
`" t
`the corners of large (200 X lOOO-um) metal pads, which W ‘;
`be excluded by standard design rules. Quantitative results for - “
`ferent experimental groups are shown in Fig. 6. The stress of. '.
`underlayer and especially the cap oxide are important to!" "
`proving crack resistance.
`Planarization processes for IMD include chemical-mec -
`.
`cal polishing (CMP) and resist or SOC etch-back
`In '
`CMI’process, thesurfaoeofthewaferisremovedbyaslurry4 " “ --
`
`
`
`Page 6 of 12
`
`
`

`

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`Page 7 0f 12
`
`Page 7 of 12
`
`

`

`

`

`
`
`Page 9 0f 12
`
`Page 9 of 12
`
`

`

`a typical planar and defect-free trench is shown in Fig. 10.
`
`high aspect ratio trenches prevents excessive erosion of the trench
`fill during subsequent oxide strips and Cleans.
`The quality of trench-fill dielectrits can be evaluated on the basis
`of film stress, gap fill, surface morphology, and wet etch rates.
`Process objectives are more challenging than the case with lMDs,
`but a much larger thermal budget allows more process flexibility.
`Film stress must be below 200 MPa due to the use of thicker films;
`wet etch rates (in HF) must approach that of thermal oxide
`since both films are etched simultaneously within the trench
`module, and the trench fill must be void- and seam-free. Smooth
`topography is desired in both IMD and trench applications to
`enable a lower particle size detection limit and to provide a fa-
`vorable surface for subsequent film nucleation.
`Trench fill is evaluated by SEM cross section after staining in
`a 10:1 BOE to highlight any low—density regions in the dielec-
`tric. Film quality improves and deposition rate decreases with in-
`creases in deposition temperature and 032R ratio. Wet etch rates
`(10:1 BOE) also decrease as anneal temperature is increased.
`Trench-fill film characteristics were evaluated over an ex-
`
`perimental range bounded by deposition temperature (400 to
`600°C) and O;:R ratio (10:1 to 75:1). Figure 8 displays SEM cross
`section micrographs comparing gap fill, after BOE stain, at the
`three different deposition temperatures at both low and high
`032R ratios.
`
`The lower temperature process results in voiding regardless
`of 032R ratio. The mid- and high—temperature processes using
`the higher 03:R ratios result in void-free fill, while the lower O;R
`ratio process results in very slight voiding. Stress of the as-deposited
`film is also a function of deposition temperature and ranges
`from 300 MPa at 400°C down to 220 MPa. Densification above
`
`8(X)°C lowers stress significantly, with values ranging from —100 to
`—125 MI’a (compressive) after annealing. Film stress after den-
`sification is independent of deposition temperature. The wet
`etch rate of the densified film is also reduced significantly —
`from 300 nm/min for the as-deposited film to 125 nm/ min.
`Trench isolation devices filled with TEOS/Q films have been
`successfully fabricated and evaluated, including 71- and p—channel
`
`88 Solid State Technology March 1004
`
`Page 10 of 12
`
`figure 8. SEM cross sections of trench-fill quality vs. deposition tem-
`perature and 032R ratio. High 032R ratios and high temperatures
`result in void-free fill.
`
`it is widely recognized that LOCOS-based technology cannot be
`extended to deep submicrometer dimensions because of lateral
`oxide encroachment and field oxide thinning in narrow isola-
`tion regions [17].
`Trench isolation has been proposed as a potential LOCOS re-
`placement in scaled and high-performance ULSI. The deposi—
`tion of void-free and seam-free fill material into narrow and
`
`Fla". 9. Field punch-through voltages for trench Isolation and PBL '
`isolation. Consistently higher punch-through voltage is obsemeu for
`trench isolation with no degradation of subthreshold 0.5-um M‘LJSFET
`characteristics.
`
`0.5-um MOSFETs, which showed no subthreshold degradation
`[14]. Functional ring oscillators were also fabricated.
`Field punch—through voltages on intrawell and interu'L‘ll i”
`lation structures are shown in Fig. 9. The results achieved with
`trench isolation were significantly better than the control whid‘
`used poly-buffered LOCOS (PBL) isolation. Punch-fluuugh volW.
`was well above 10 V and independent of field isolation width-
`A transmission electron micrograph (TEM) cross section sho '
`"—
`
`

`

`

`

`or coauthor of over 20 technical papers.
`
`Summary
`This study examines a few of the more important film character-
`istics of doped and undoped AI’CVD TEOS/Qr oxides and their
`application in submicrometer poly-metal isolation, intermetal
`spaces, and isolation trenches. Stable low-temperature (<850°C)
`flow glass processes (OazBI’TEOS) have been demonstrated and
`successfully incorporated into 0.63pm devices. Circuit yields and
`device parametrics using a mos/um05 composite [MD are
`shown tobeequivalent to PETEOS. integration of TEOS/Oi further
`benefits from CMP removal rates and dry etch rates — which
`are comparable to PETEOS — and adequate adhesion between
`TEOS/03 and PETEOS films. High punch-through voltages and
`excellent subthreshold characteristics were also achieved using a
`void-free trench fill. High-temperature densification of TEOS/Os
`eases the integration of trench—fill applications. Both film stress and
`wet etch rates are halved relative to the as—deposited values. I
`
`12. Stimokawa st 8.. 1992 53mg VLSI Tech. D19. 01 Tech. Papers. New .'
`IEEE. p. 96.
`13.1’akagiet at. IEDM 1992. IEEE. 92-703. p. 28.4.1.
`14. JP. West. H.W. Fry. 8. Poon, BA. Boeck. C.C. Yu. 1993 Proc. Mulr‘ .
`Inlaconnection. SPIE Vol. 2090. 1993. p. 119.
`15. A.V. Gelatos. J.T. Wetzel. C.J. Mogap. .J. Hectrochem. Soc, Extended .
`stracts. Vol. 96-1. Spring 1993. p. 446.
`16. A. Bose at al., Proc. 12th Int. VMIC Cont. Santa Clara. CA. 1993. p 59,
`17. T. Sugibayashi et at. Dig. Tech. Papers. 1993 ISSCC. IEEE. vol. 36, o. 50.
`16. K. Fupino et at. Proc. of 1990 VMIC Cont. June 1990. p. 191.
`
`-
`'
`,._.
`
`.
`
`.
`H. WALLACE FRY joined the Watidncrjo
`semiconductor equipment group in 1992 3 ~.
`senior marketing engineer. Mr. Fry recei
`a BS. in Chemical Engineering from the U 1
`versity of California, San Diego. His semi
`conductor experience includes work with u.
`CVD process group at MOS-11, Motorola'
`g
`first ZOO—mm wafer fabrication facility. : e
`‘5
`joining Motorola, he spent five years with -
`'
`Hughes Aircraft Co., Carlsbad Research Center, where he worked a }
`developing tetramethylcyclotetrasiloxane BPSG processes. Mr. Fry .
`-_
`an active member of the Electrochemical Society.
`
`:
`
`JEFFREY P. WEST received an MS. in E .
`trical Engineering from the University of
`> ‘
`Mexico. His Master’s degree research, . -.
`formed at Sandia National Laboratori ‘
`focused on low-temperature silicon epi .
`.
`Since graduation, he has worked in Motu .
`CMOS/BiCMOS development group, de -.
`oping and sustaining intermetal diclcc
`processes for use in advanced FSRAM a
`logic technologies.
`
`'_
`
`STEPHEN POON received the 8.5. and M
`degrees in Chemical Engineering and the MS
`degree in Electrical Engineering from the Urdv -
`versity of Texas, Austin. He joined Muto c
`i
`in 1985 and worked on etch technology de-
`velopment and integration of disposable L I ' 1’
`spacer technology. From 1987 to 1989, he
`a member of the technical staff at Microeleo“
`tronics and Computer Technology Corp
`where he worked on the development of high-density copper-pol
`imide interconnects. He returned to Motorola in 1989 and is prescn f
`engaged in technology development for sub<0.5-pm logic circuits. Mfr-
`Poon holds 6 patents and has published 15 papers.
`
`gineering and in 1984 with an M.S. in Met,-
`allurgical Engineering. He has worked for MO‘
`torola's Advanced Products RAID Lab for 01"
`nine years. For the past two years, Mr.
`'
`‘
`"
`has concentrated on plasma-enhanced CVD I
`oxides. Mr. Boeck is coauthor of 14 papers-
`
`CHRIS C. Yu received 3.5. and MS. degrer
`in Physics from the University of Missou11‘
`Kansas City in 1983 and 1984, respectively" ‘
`and a PhD. in Physics from Pennsylvafll‘
`State University in 1990. Before joining MO‘
`torola's Advanced Products R&D [ahtfaw'
`in 1992, Dr. Yu worked for Micron Tech
`ogy Inc. His current interest is in advan
`multilevel metallization for 0.25pm gt'flef“
`tion devices and beyond. Dr. Yu holds 11 patents and is the 011m“ ‘
`
`m 10. TEM micrograph ot a 0.5-pm isolation trench.
`
`Acknowledgments
`The authors wish to thank the Motorola Advanced Products
`
`Research and Development Laboratory pilot line and SEM staff;
`the Watkins-Johnson applications staff; and Dawn Kinstler
`(Motorola lnc.), Ann Warner (Watkins-Johnson Co), and Todd
`0. Curtis (Watldns-Johnson Co.), in particular, for their support
`oftliisprojecLAdditional thanlcstaoL KroppGBMASTlC) forinitial
`evaluation.
`
`2.
`
`UlbWN-‘a
`JO‘DOVO
`
`_._.
`
`T. Bonifialdet al., Semioond. Int, Vol. 16. p. 200. July 1998.
`. J, West at al., Proc. 1211: Int. VMIC Conl. Santa Clara. CA. 1992. p. 89
`.C. Noren et al., Proc. 19931nst. Environmental Sci. Mtg. p. 107.
`. S. lmai.AppI. Phys. Lett.. 60 (22). p. 2761. Jme 1, 1992.
`.J. Gonitt. J. Bactodran. Soc.. BdendedAbstracrsfmm 1993SpmgMeeting,
`Abstract No. 292. p. 439.
`. M. Moinpour at al., Hoe. 1993 ISMSS. IEEE Cat. No. 9361432805. 9. 33.
`.K. MaedaetBL SoIidStata Tedl. Vol. 36. p. 83. June 1993.
`. J. Huang et al., J. Electrochem. Soc. ExtendedAbstIacts, Vol. 934. Spring
`1993. p. 425.
`.J. Uetal.. Proc. WiFvaTPUsers Group N.C.C. A.V.S. Symp.. Sept. 1993.
`.K. Fuiino et al., Proc. 7th/nt VMIC Cont. Santa Chara. CA. 1992. p. 187
`.K. Kwok at al.. Proc. 12thlnt. Symp. Chem. Vapor Deposmon. Electrochem.
`Soc.. Pennington. NJ. 1993. p 320.
`
`40 Solid State Technology MM 1904
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`Page 12 of 12
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