`ULSI Technology
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`EDITED BY
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`C. Y. Chang
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`Chair Professor: College of Electrical Engineering and Computer Science
`National Chiao Tang University
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`Director, National Nano Device Laboratories
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`Hsinchu, Taiwan, ROC
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`S. M. Sze
`UMC Chair Professor
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`Department of Electronics Engineering
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`Director, Microelectronics and Information Systems Research Center
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`National Chiao Tung University
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`Hsinchu, Taiwan, ROC
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`THE McGRAW-HILL COMPANIES, INC.
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`Page 1 0f 19
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`TSMC Exhibit 1044
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`TSMC Exhibit 1044
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`IPR2016-01246
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`MCGraw—Hill
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`A Division of TheMcGraw-Hill Companies
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`ULSI TECHNOLOGY
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`Acknowledgments begin on page 724 and appear on this page by reference.
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`This book is printed on acid-free paper.
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`234567890DOCDOC909876
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`ISBN 0-07-063062—3
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`Copyright ©1996 by The McGraW—Hill Companies, Inc. All rights reserved. Printed in the United
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`Library of Congress Catalog Card Number: 95-81366
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`Cover photo: Electron micrograph of contact holes filled with CVD tungsten plugs (see Chapter 8).
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`p The diameter is 0.25 micron. Courtesy of the National Nano Device Laboratories, National Science
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`Council, R.0.C,
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`Page 2 of 19
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`ABOUT THE EDITORS
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`c_ Y. CHANG is Chair professor at the National Chiao Tung University and Director
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`of the National Nano Device Laboratories, Taiwan, R.O.C. He has been the Dean of
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`the College of Engineering and the Dean of the College of Electrical Engineering and
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`Computer Science. He has written a book, GaAs High Speed Devices, has published
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`more than 200 technical papers in international journals, and holds eight patents in
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`ULSI, VHIC, and optoelectronics. He has taught many electronics engineers who
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`have contributed significantly to the rapid growth of ULSI industries in Taiwan. Dr.
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`Chang was elected a Fellow of IEEE in 1988 for his “contributions to semiconductor
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`development and to education.”
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`S. M. SZE is UMC Chair Professor of the Electronics Engineering Dept. and Di—
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`rector of Microelectronics and Information Systems Research Center, the National
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`Chiao Tung University, Taiwan, R.O.C. For many years he was a member of the
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`technical staff at AT&T Bell Laboratories, Murray Hill, New Jersey. Dr. Sze has
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`made pioneering contributions to semiconductor devices and processing technolo—
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`gies, including the invention of the nonvolatile memory (1967) and the fabrication
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`of MOSFETS in the O. 1 pm regime (1982). Author or coauthor of more than 100 tech—
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`nical papers, Dr. Sze has written three books on semiconductor devices and edited
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`six books on VLSI technology, high-speed devices, semiconductor sensors, and re—
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`lated topics. He has been elected Fellow of IEEE, member of the Academia Sinica,
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`and member of the National Academy of Engineering.
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`To Our Colleagues and Students—
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`Past, Present, and Future
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`0n the Centennial of Our University—-
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`The National Chiao Tung University
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`Page 4 of 19
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`Cleanroom Technology
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`H. P. Tseng and R. Jansen
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`1.1
`Introduction
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`1.2 Cleanroom Classification
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`1.3 Cleanroom Design Concept
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`1.4 Cleanroom Installation
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`1.5 Cleanroom Operations
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`1.6 Automation
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`1.7 Related Facility Systems
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`1.8 Summary and Future Trends
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`References
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`3.5 Selective Epitaxial Growth of Si
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`Problems
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`Wafer-Cleaning Technology
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`C. Y. Chang and T. S. Chao
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`2.1 Introduction
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`2.2 Basic Concepts of Wafer Cleaning
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`2.3 Wet—Cleaning Technology
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`2.4 Dry—Cleaning Technology
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`2.5 Summary and Future Trends
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`References
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`Problems
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`Epitaxy
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`P. Wang
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`3.1
`Introduction
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`3.2 Fundamental Aspects of Epitaxy
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`3.3 Conventional Si Epitaxy
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`3.4 Low—Temperature Epitaxy of Si
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`List of Contributors
`Preface
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`Introduction
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`viii Contents
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`3.6 Characterization of Epitaxial Films
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`3.7 Summary and Future Trends
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`Problems
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`4 Conventional and Rapid Thermal Processes
`R. B. Fair
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`4.1 Introduction
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`4.2 Requirements for Thermal Processes
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`4.3 Rapid Thermal Processing
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`4.4 Summary and Future Trends
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`Problems
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`Problems
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`6.5 Ion Lithography
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`Dielectric and Polysilicon Film Deposition
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`H. C. Cheng
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`5.1 Introduction
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`5.2 Deposition Processes
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`5.3 Atmospheric—Pressure Chemical—VaporeDeposited
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`(APCVD) and Low—Pressure Chemical—Vapor—Deposited
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`(LPCVD) Silicon Oxides
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`5.4 LPCVD Silicon Nitrides
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`5.5 LPCVD Polysilicon Films
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`5.6 Plasma—Assisted Depositions
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`5.7 Other Deposition Methods
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`5.8 Applications of Deposited Polysilicon, Silicon Oxide,
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`and Silicon Nitride Films
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`5.9 Summary and Future Trends
`References
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`Lithography
`K. Nakamura
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`6.1
`Introduction
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`6.2 Optical Lithography
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`6.3 Electron Lithography
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`6.4 X—Ray Lithography
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`Low—Pressure Gas Discharge
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`Etch Mechanisms, Selectivity, and Profile Control
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`Reactive Plasma Etching Techniques and Equipment
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`Plasma Processing Processes
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`Diagnostics, End Point Control, and Damage
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`Wet Chemical Etching
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`Summary and Future Trends
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`510
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`8.2
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`8.6
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`8.7
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`Metal Deposition Techniques
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`Silicide Process
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`CVD Tungsten Plug and Other Plug Processes
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`Multilevel Metallization
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`Metallization Reliability
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`Summary and Future Trends
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`451
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`Problems
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`Process Integration
`~ C. YLuandW Y.Lee
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`Introduction
`9.1
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`Basic Process Modules and Device Considerations for
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`9.2
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`9.5
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`9.6
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`CMOS Technology
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`Bipolar Technology
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`BiCMOS Technology
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`MOS Memory Technology
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`Contents
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`ix
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`6.6 Summary and Future Trends
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`References
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`Problems
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`Etching
`Y. J. T. Lii
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`7.1
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`7.2
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`7.3
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`7.4
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`7.5
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`7.6
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`7.7
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`7.8
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`Problems
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`Metallization
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`R. Liu
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`Introduction
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`Page 7 of 19
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`x Contents
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`9.7 Process Integration Considerations in ULSI Fabrication
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`Technology
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`9.8 Summary and Future Trends
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`Problems
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`10 Assembly and Packaging
`T. Tachikawa
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`10.1
`Introduction
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`10.2 Package Types
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`10.3 ULSI Assembly Technologies
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`10.4 Package Fabrication Technologies
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`10.5 Package Design Considerations
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`10.6 Special Package Considerations
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`10.7 Other ULSI Packages
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`10.8 Summary and Future Trends
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`12.6 Effect of Scaling on Device Reliability
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`Wafer Fab Manufacturing Technology
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`T. E Shao and F C. Wang
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`11.1 What Is Manufacturing?
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`11.2 Wafer Fab Manufacturing Considerations
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`11.3 Manufacturing Start—Up Technology
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`11.4 Volume Ramp—Up Considerations
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`11.5 Continuous Improvement
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`11.6 Summary and Future Trends
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`Problems
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`Reliability
`J. T. Yue
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`12.1 Introduction
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`12.2 Hot Carrier Injection
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`12.3 Electromigration
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`12.4 Stress Migration
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`12.5 Oxide BreakdOwn
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`Appendixes
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`A. Properties of Si at 300 K
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`B. List of Symbols
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`International System of Units
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`D. Physical Constants
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`711
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`’ 709
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`Relations between DC and AC Lifetimes
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`Some Recent ULSI Reliability Concerns
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`Mathematics of Failure Distribution
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`Summary and Future Trends
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`References
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`Problems
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`C.
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`Index
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`Contents
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`xi
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`686
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`697
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`CHAPTER 7: Etching
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`AlCu etch chamber
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`TiW etch chamber
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`FIGURE 21
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`Cluster reactive ion etch tool for multilayer metal (TiW/AlCu/TiW)
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`interconnect etching.
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`7.5
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`PLASMA PROCESSING PROCESSES
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`The chemical and physical complexity of plasma—surface interactions makes com—
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`puter—based modeling and plasma simulation inadequate for developing plasma reac—
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`tors. As a result, the detailed descriptions required to guide the transfer of processes
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`from one reactor to another or to scale processes from a small to a large reactor are
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`not available. Therefore, the plasma processes for fabricating microelectronic de—
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`vices have been developed largely by time—consuming, costly, empirical methods.
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`Excellent critical dimension control and minimized profile microloading are the
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`two most important issues for ongoing research. Extensive research in plasma etch-
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`ing explores ways to optimize the performance of etching processes, characterize
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`and measure their densities, and, in general, improve our limited understanding of
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`plasma etching. See Refs. 28 and 29 on various aspects of plasma etching. Other
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`studies concentrate on the limitations of conventional rf plasma. This research led
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`still being examined.
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`Etch chemistries also play a critical role in the performance of etch pro—
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`cesses. Table 3 lists some conventional and new etch chernistries for different
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`etch processes.30 A truly useful plasma process must have a robust process window.
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`Page 10 of 19
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`Page 10 of 19
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`TA B L E 3
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`Etch chemistries of different etch processes30
`aware” rear ‘ *‘ P‘rfi‘k'7'"»e> “or:
`W:
`'i‘bva‘W’v'
`:
`2'
`'
`'
`’
`t m
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`sidewall
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`passivating
`gases
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`PolySi
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`C12 or BC13/CC14
`/CF4
`/CHCl3
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`/CHF3
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`Conventional chemistry New chemistryMaterial being etched BenefitsM
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`No carbon contamination
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`Increased selectivity to SiOz and resist
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`N0 carbon contamination
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`Higher etch rate
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`Better profile control
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`No carbon contamination
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`N2 accelerates Cu etch rate
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`Additional aluminum helps etch copper
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`No carbon contamination
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`Etch stop over TiW and TiN
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`No carbon contamination
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`Controlled etch profile
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`No carbon contamination
`Higher—selectivity trench etch
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`M
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`CFC alternatives
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`CFC alternatives
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`SiOz (BPSG)
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`CC12F2
`CF4
`C2136
`C3133
`CClez
`CHF3
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`‘
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`CC12F2
`CHF3/CF4
`CHF3/Oz
`CH3CHF2
`CF4/02
`CF4/H2
`CHF3
`CH3CI’IF2
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`_
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`C12
`BC13 + sidewall-passivating gases
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`SiCl4
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`Same as Al
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`BCl3/C12/CHF3
`SFG/Ciz/CCh
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`SiC14/C12
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`BC13/C12
`HBr/C12/02
`HBr/OZ
`Brg/SFs
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`SF6
`CF4
`SiCl4/C12
`BCl3/C12
`HBr/Clz
`BC13/C12 + N2
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`BCl3/Clz + N2 + A1
`SF5 only
`NFg/Clg
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`SR; only
`CClnglNF3
`CF4/Clz
`CF3Br
`HBr/NF3
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`‘
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`V
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`SFfi/CiZ/OZ
`CCleg
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`C1; or BC13 + sidewall—passivating gases
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`Al
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`Al-Si (1%); Cu (0.5%)
`Al—Cu (2%)
`W
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`TiW
`WSiz, TiSiz, CoSiz
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`Single—crystal Si
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`Page 11 of 19
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`CHAPTER 7: Etching
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`Developing an etch process usually means optimizing many characteristics, such as
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`etch rate, selectivity, profile control, endpoint control, damage, etc., by adjusting a
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`large number of process parameters. Because we do not fully understand etch pro—
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`cesses, systematic experiments are required to study the large number of process
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`parameters. The most common method is to use the design experiment and analyze
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`the results with a surface response methodology. In this section, several of the most
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`important etch processes for ULSI fabrication are introduced.
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`7.5.1 Silicon Trench Etching
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`pressure. Greater pressure of He results in a cooler wafer temperature.
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`As feature sizes in ULSI decrease, a corresponding decrease is needed in the area
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`occupied by both the isolation between circuit elements and the storage capacitor
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`of the DRAM memory cell. This area can be reduced by etching trenches into the
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`silicon substrate and filling them with suitable dielectric or conductive materials.
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`Silicon trenches can also be used as alignment marks for optical or electron beam
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`lithography. Deep silicon trenches, usually with a trench depth larger than 5 um, are
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`used mainly for forming trench capacitors. Shallow silicon trenches, usually with a
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`trench depth less than 1 pm, are often used for isolation between device elements.
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`To guarantee a void—free trench refill, anisotropic etching with a high etch se—
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`lectivity to mask material is desired for submicrometer—deep silicon trench etching.
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`This precludes the use of fluorocarbon chemistry, which tends to undercut the mask
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`material.18 Fluorine chemistry has a high silicon etch rate, but it has low etch se—
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`lectivity to the oxide mask and to the isotropic trench profile. However, it is often
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`used for etching shallow silicon trenches with trench depths less than 1 pm, because
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`it satisfies the requirement of etch selectivity of silicon to the photoresist mask. In
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`this section, the deep-trench etching process is discussed because of its stringent
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`requirements of etch rate, anisotropy, and selectivity.
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`Chlorine—based and bromine—based chemistries have a high silicon etch rate
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`and high etch selectivity to the silicon dioxide mask. However, chlorine—based
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`chemistries tend to give slightly isotropic trench profilest32 especially in the ion—
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`implanted phosphorus—doped region. Carbon—containing gas has been employed
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`to provide sidewall passivation to avoid undercutting from fast chlorine—silicon
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`reactions.33 The sidewall passivation layer, however, causes contamination and
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`reduces the etch selectivity of silicon to a silicon dioxide mask. A simple carbon-
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`free etch chemistry leading to minimum thickness of the sidewall passivation is
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`desired to guarantee high accuracy in the pattern transfer. As a general rule, the
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`reactivity of the halogens follows the order F > C1 > Br. Recently, bromine—based
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`chemistries have become popular for etching silicon with anisotropy and extremely
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`high selectivity to the oxide mask.34
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`Sidewall passivation protects the sidewall from lateral etch attack and local ion—
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`enhanced trenching. The desired trench shapes with smooth vertical sidewalls are
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`obtained by controlling the balance between the etch and the inhibition by sidewall
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`passivation. The sidewall shape depends significantly on the wafer temperature. In—
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`creasing temperature results in less deposition of sidewall passivation and more lat-
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`eral etching. Fig. 2210 refers to the effects of backside cooling under different He
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`Page 12 of 19
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`Page 13 0f 19
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`Page 13 of 19
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`

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`CHAPTER 7: Etching
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`357
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`Aspect ratio—dependent etching (ARDE) is often observed in submicrometer—
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`deep silicon trench etching caused bylimited ion and neutral transport Within the
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`trench. Trenches with large aspect ratios etch more slowly than trenches with small
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`aspect ratios. Ion scattering results from ion~neutral collisions in the plasma sheath,
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`and the electrical charging on the masks causes ARDE. Some neutrals are trans—
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`ported to the bottom of the trench by Knudsen diffusion, also contributing to ARDE.
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`Low gas pressure reduces the ARDE effect, and chlorine—based chemistry shows
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`less ARDE than fluorine—based chemistry during deep trench etching, because ion—
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`assisted etching is dominant in chlorine—based chemistry.35
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`7.5.2 Polysilicon and Polycide Gate Etching
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`is well known that selectivity is achieved by increasing the ratio of CF), to F atoms
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`Low-pressure chemical vapor deposited (LPCVD) polysilicon is usually used as a
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`gate material for MOS devices because of its superior interface property with thin
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`gate oxide at high temperature. Metal silicide over polysilicon has also been used
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`for the MOS gate because of its high electrical conductivity. Anisotropic etching and
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`high etch selectivity between polysilicon and the gate oxide are the most important
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`requirements for gate etching. Achieving high selectivity and etch anisotropy at the
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`same time is difficult for most ion—enhanced etching processes. Therefore, multistep
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`processing is used in which different etch steps in the process are optimized for etch
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`anisotropy and selectivity.
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`Most chlorine—based and bromine—based chemistries can be used for gate etch—
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`ing to achieve the required etch anisotropy and selectivity. The main etchant today is
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`bromine—based chemistry, because bromine gives higher etch selectivity of polysil—
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`icon to gate oxide than chlorine does. Figure 23 shows a scanning electron micro—
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`scope (SEM) cross section of a polysilicon gate etched by HBr plasma36 that has a
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`0.1 um gate width and a 45 A gate oxide thickness. The thin native oxide on top of
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`the polysilicon should be removed by fluorine—based plasma before polysilicon etch—
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`ing, i.e., initiation, to avoid any micromasking formation during polysilicon etching.
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`To further improve the selectivity of polysilicon to gate oxide requires removing
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`carbon—containing gases and carbon—containing materials from the etch process and
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`the etch reactor, because carbon tends to reduce the selectivity of polysilicon to gate
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`oxide,37 as shown in Fig. 24. It is suspected that carbon reacts with the oxygen atoms
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`of silicon. dioxide. An enhanced etch attack at the edge of the gate, a phenomenon
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`called “trenching,” is shown in Fig. 25. Trenching results in broken gate oxide and
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`is usually observed at low gas pressure. The trenching problem can be solved by
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`increasing etch selectivity, such as adding bromine— and oxygen—containing gases to
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`the etch process.
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`7.5.3 Oxide and Nitride Etching
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`An oxide etching process is often used to open a contact window down to a Silicon
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`device or metal conductor; therefore, the selectivity of $102 to Si must be high. It
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`Page 14 of 19
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`358 ULSI Technology
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`868788 EBKV
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`in the plasma.7 CHF3/CF4 chemistry is a common oxide etchant because it pro—
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`vides high selectivity to Si from carbon polymer deposition on the silicon surface
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`Therefore, a further silicon surface cleaning must be added to remove the polymer
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`passivation layer after oxide etching to avoid high contact resistance between metal
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`and silicon.
`7
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`LPCVD or plasma—enhanced CVD silicon nitride are often used as a side—
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`wall around the polysilicon gate in MOS devices for source and drain extension or
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`used as a final passivation layer. Sidewall formation for a polysilicon gate requires
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`anisotropic etching and high selectivity of silicon nitride to silicon dioxide. Si3N4
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`can be etched by both fluorine atoms and CFx—containing plasma. CF4 and CF4/Oz
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`are widely used to etch silicon nitride but are not selective to silicon or silicon
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`dioxide?8 Si3N4 can be etched anisotropically in anRIE mode with high selec—
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`tivity to Si and 8102 by CHF3/Oz, CHZFZ, or CH3F.39~40 Details of why the etch
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`mechanism results in high selectivity are not clear. Fluorine—deficient fluorocarbon
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`polymer is thought to contribute to this high selectivity.
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`FIGURE 23
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`SEM cross section of HBr—plasma—etched polysilicon gate with
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`a 0.1 pm gate width and a 45 A gate oxide thickness. (After Lii
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`et al., Ref. 36.)
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`Page 15 of 19
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`Etching of a metallization layer is a very important step in semiconductor device
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`fabrication. Aluminum and tungsten are the most popular materials used for inter—
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`COnnection, and anisotropic etching of these materials is usually required. An alu—
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`minum etch with fluorine—based chemistry does not work, because of the very low
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`vapor pressure of the etch product Ang. Chlorine—based chemistry has been used
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`for A1 etching most frequently, and bromine—based chemistry has been investigated
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`recently.41
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`CHAPTER 7: Etching
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`359
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`After
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`,d OO
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`U} C
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`With resist
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`HBr flow rate (sccm)
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`(b)
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`200
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`Selectivity(poly—Si/SiOZ)
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`J:O
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`4:.
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`SiO2 (with resist)
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`+-1—-—-—-A—-——-———*—
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`A
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`Etchingrate(um/min)
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`...._J_
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`__L.._
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`50
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`100
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`150
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`(a)
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`FIGURE 24
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`Dependence of (a) the polysilicon etch rate and (b) Si/SiOz selectivity on HBr flow rate,
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`carbon reducing Si/SiOg selectivity. (After Nakamura, Iizuka, and Yano, Ref. 37.)
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`7.5.4 Aluminum and Tungsten Metal Etching
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`Silicon
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`FIGURE 25
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`Schematic of the trenching
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`mechanism during polysilicon
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`gate etching.
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`Page 16 of 19
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`360 ULSI Technology
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`FIGURE 26
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`Formation of tungsten
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`plug in a contact hole by
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`depositing blanket LPCVD
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`W and then using RIE
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`C12 spontaneously etches clean aluminum. Chlorine has a very high chemical
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`etch rate with aluminum and tends to produce an undercut during aluminum etch—
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`ing. Carbon—containing gas is added to form sidewall passivation during aluminum
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`etching to obtain etch directionality. The A1203 layer, which is always present on
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`air—exposed aluminum, is etched very slowly in chlorine—based gases. Energetic ion
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`bombardment, for example, sputtering, is required to remove A1203 before alu—
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`minum etching. In the semiconductor industry, BCl3 plasma is often used to remove
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`A1203 on the aluminum surface.42 BClx also appears to recombine with chlorine
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`at the wafer surface to ensure an anisotropic etch profile during Al etching with a
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`Clz/BC13 mixture. A. small percentage of silicon and copper are usually added to
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`enhance the electromigration resistance of aluminum conductors, but Cu causes mi—
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`cromasking during aluminum etching with chlorine—based plasma because it gener—
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`ates low—volatility etch products. Micromasking can be suppressed by using stronger
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`ion bombardment during etching and addition of aluminum chloride gas.43 More re—
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`cently, a barrier metal layer, such as TiW and TiN, has been used to prevent Si
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`migration into Al. TiW and TiN etch readily in chlorine—based plasma.
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`Corrosion of the aluminum pattern exposure to the ambient is another problem
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`in aluminum etching. Residual chlorine on both the Al sidewall and the photoresist
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`tends to react with water to form HCl, which etches aluminum. ln—situ exposure of
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`the wafer to a CF4 discharge to exchange Cl with F and then to an oxygen discharge
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`to remove the resist, followed by immediate immersion in deionized (DI) water, is
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`successful in eliminating Al corrosion.44 High—temperature heating of the wafer to
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`evaporate chlorine or hydrolyzing chlorine with hydrogen—containing gases can be
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`used to remove chlorine trapped in the resist and the sidewall.
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`LPCVD tungsten has been widely used for contact hole filling and first—level
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`metalization because of its excellent deposition conformability. Both fluorine— and
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`chlorine—based chemistry etch W and form volatile etch products.45’46 Fluorine—
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`baSed chemistry also etches the silicon dioxide layer; thus it is very difficult to
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`obtain selectivity between W and SiOz. Chlorine—based chemistries etch tungsten
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`with selectivity to 8102. Two tungsten etch processes, blanket W etchback to form
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`a W plug and W pattern etch, are discussed briefly in this section.
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`To form a W plug, blanket LPCVD W is deposited on top of a TiN barrier layer
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`as shown in Fig. 26. Reducing loading effects during the etchback of W is very im—
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`portant to avoid a W recess in the plug. A two—step process is used for W etchback.
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`In the first step, 90% of the W is etched at a high etch rate and excellent uniformity
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`to achieve high throughput. In the second step, the etch rate is reduced to remove the
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`Before W etchback
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`Page 17 of 19
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`CHAPTER 7; Etching
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`361
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`remaining W with an etch-ant that has a high W—to—TiN—barrier—layer etch Selectivity
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`and a minimum loading effect.47 The loading effect is reduced by decreasing the gas
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`pressure and wafer temperature because of the low chemical etch rate of F with W
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`at these process conditions.
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`For W interconnect etching, the selectivity between W and the photoresist mask
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`is Very low for both fluorine and chlorine—based chemistries. N2 is added to the
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`SF6/C12 mixture to get a slight selectivity increase.48 Inorganic material, such as
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`$02, can be used as a hard mask during W etching with chlorine—based chemistry ‘
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`because of high etch selectivity of W to the hard mask.
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`7.5.5 Organic Materials Etching
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`7.5.6 Planarization Etch
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`of plasma etching and deposition. An organic material with good flow properties is
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`Oxygen plasmas have been used with a barrel reactor for resist etching since the
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`19703. Oxygen atoms are the primary species responsible for etching polymers at a
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`pressure of 1—3 torr. Oxygen atoms initiate polymer etching by extracting hydrogen
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`atoms from a polymer chain to form radicals. These radicals then react with oxy—
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`gen molecules to form volatile products under high wafer—temperature conditions or
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`under ion bombardment.
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`Recently, multilayer lithography has become increasingly important for ULSI
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`processing because it provides high resolution that is independent of the underlying
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`materials and substrate topography. The trilayer scheme is a very popular multilayer
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`lithography method. It uses a conventional resist to pattern an intermediate layer,
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`narization of the organic layer by oxygen RIE. A high degree of anis