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`United States Patent
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`5,648,284
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`[11] Patent Number:
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`Kusunoki et a].
`Jul. 15, 1997
`[45] Date of Patent:
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`[19]
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`USOOS648284A
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`[54] FIELD EFFECT TRANSISTOR INCLUDING
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`SILICON OXIDE FILM AND NITRIDED
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`OXIDE FILM AS GATE INSULATOR FILM
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`AND MANUFACTURING METHOD
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`THEREOF
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`[75]
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`Inventors: Shigeru Kusunoki; Masahide Inuishi,
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`both of Hyogo-ken. Japan
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`[73] Assignee: Mitsubishi Denki Kabushiki Kaisha.
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`Tokyo, Japan
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`[21] Appl. No.: 653,090
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`[22] Filed:
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`May 24, 1996
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`[56]
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`4,774,197
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`........................... 437/24
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`References Cited
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`U.S. PATENT DOCUMENTS
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`9/1988 Haddad et a1.
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`OTHER PUBLICATIONS
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`Kusunoki, “Hot—Canier—resistant Structure By Re—Oxi—
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`dized Nitrided Oxide Sidewall For Hogth Reliable and
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`High Performance LDD MOSFET ”, IEDM, IEEE, pp.
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`649—652. 1991.
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`Primary Examiner—Charles L. Bowers, Jr.
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`Assistant Examiner—Lynne A. Gurley
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`Attorney, Agent, or Finn—Lowe, Price, LeBlanc & Becker
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`ABSTRACT
`[57]
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`An N type field effect transistor having a higher resistivity
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`to hot carriers and exhibiting a higher current handling
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`capability even when used at a low gate voltage, and a
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`method of manufacturing such a transistor are provided. A
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`nitrided oxide film is formed on a drain avalanche hot carrier
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`injection region. The nitrided oxide film is highly resistive to
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`drain avalanche hot carriers as compared to a silicon oxide
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`film. The silicon oxide film is formed on a channel hot
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`electron injection region. The silicon oxide film is highly
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`resistive to channel hot electrons as compared to the nitrided
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`oxide film. A major portion of a gate insulator film is a
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`silicon oxide film. The silicon oxide film exhibits a higher
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`current handling capability at a low gate voltage as com-
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`pared to the nitrided oxide film.
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`7 Claims, 39 Drawing Sheets
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`Related US. Application Data
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`[60] Continuation of Ser. No. 341,952, Nov. 16, 1994, aban-
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`doned, which is a division of Ser. No. 930,932, Aug. 18,
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`1992, Pat. No. 5,369,297.
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`Foreign Application Priority Data
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`[JP]
`Japan .................................... 3-225686
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`[JP]
`Japan ............
`3-323239
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`[JP]
`Japan .................................... 4-176873
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`[30]
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`Sep. 5, 1991
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`Dec. 6, 1991
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`Jul. 3, 1992
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`[51]
`Int. Cl.6 ................................................... H01L 21/265
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`[52] US. Cl. ............................... .. 437/40 GS; 437/41 GS;
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`437/42; 437/241
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`[58] Field of Search ........................... 437/40 GS, 41 GS,
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`437/42. 241
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`Page 1 of 51
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`TSMC Exhibit 1041
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`TSMC v. IP Bridge
`IPR2016-01246
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`Page 1 of 51
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`TSMC Exhibit 1041
`TSMC v. IP Bridge
`IPR2016-01246
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`US. Patent
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`Jul. 15, 1997
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`Sheet 1 of 39
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`FIG.1
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`o
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`-~-'-‘r"'r':-.'+"‘
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`::.“;:,:i:l.1.gr;:.NO GA
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`FIG. 2
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`Page 2 0f51
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`g
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`Page 2 of 51
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`US. Patent
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`Sheet 2 of 39
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`5,648,284
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`FIG.3
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`PRIOR ART
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`US. Patent
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`Jul. 15, 1997
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`Sheet 3 of 39
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`5,648,284
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`FIG.4
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`US. Patent
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`Jul. 15, 1997
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`Sheet 4 of 39
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`5,648,284
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`VIIIJIIIIIIIIIIIJIIII"l'llfl
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`Page 5 0f51
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`US. Patent
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`Sheet 5 of 39
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`5,648,284
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`FIG.8
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`FIG.9
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`_TWInlm
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`US. Patent
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`Sheet 6 of 39
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`5,648,284
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`FIG.10
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` mwl‘.'I...".l.’l.-'l'.l“
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`%'Ill’ll’lll'lll'.'l'l'lll’a
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`Jul. 15, 1997
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`Sheet 7 of 39
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`5,648,284
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`FIG. 12
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`FIG.13
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`Sheet 8 of 39
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`US. Patent
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`Sheet 9 of 39
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`FIG.16
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`Sheet 10 of 39
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`FIG. 18
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`Sheet 11 of 39
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`FIG.19
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`Sheet 12 of 39
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`FIG.21
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`F 1G. 23
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`FIG.26
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`5,648,284
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`FIG. 28
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`FIG.30
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`Ell-"l:
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`FIG.34
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`FIG.38
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`FIG.44
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`FIG.45
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`FIG.46
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`rum: 4 ““““\““‘
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`A
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`190
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`Sheet 24 of 39
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`5,648,284
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`.
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`
`-
`N-ch MOSFETCSINGLE DRAIN)
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`:
`L/W=1.0/10.0(pm/um)
`E
`1
`
`I
`; N0 GATE
`--------- -.' -------- --.~ -------- --
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`FIG. 48
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`H
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`>
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`H
`.—
`g
`19
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`3
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`10
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`2
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`< 3
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`3 9 1
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`%
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`C12
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`Ip
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`—
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`F1649
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`1100
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`[‘c]
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`900
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`NITRIDATION TEMPERATURE
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`1000
`
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`800
`
`
`
`103
`
`10
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`
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`N-ch MOSFET(SINGLE DRAIN)
`
`
`L/W=1.0/10.0( pm/ym)
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`
`
`VD=VG=5.0V AFTER
`
`1000 sec
`------------------
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`NITRIDATION TEMPERATURE [’c]
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`1—
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`5..
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`Page 25 0f 51
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`Jul. 15, 1997
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`Sheet 25 of 39
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`5,648,284
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`FIG. 50
`
` .n_«m“NL_430I20mm
`
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`OW?1"............IMm.
`_--Lu.sI..III...I“mm._..
`.-I..-1---:uu__ux;_n.m"uuo..-ulmun+n..nIx...I--
`x__.‘.-‘_nur.....ul..A-.-u---n:---m._.__XN_u.._OCH_-r3;_i.-L-
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`w/“Lnim{HuanuHHNmIn.m_1rlum.uaIIunIn“I.ItI:x1.
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`47"-"-1TTIT--_.---L.--------
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`...l_.1_uin-.Tmu—Ia«||-..|.:
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`muwm\>\wEuu:ml
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`FIG. 51
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`
`7mm;\uEuuto:
`
`
`
`
`PT(1m0E0.V--0gmM90/wMm=nw._‘.ENhu,mmmmwe5432
`mm
`
`mU.
`
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`.-_
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`952$
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`FWC) GATE
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`1100
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`NITRIDATION TEMPERATUREch
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`Page 26 0f 51
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`Jul. 15, 1997
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`Sheet 26 of 39
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`5,648,284
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`FIG.52
`
` I
`
`
`
`l
`
`150
`
`
`
`11
`
`
`
`15b
`
`
`
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`
`FIG.53
`
`0|
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`\9\J
`
`
`
`5NES!
`\\\\\\\\\\\\\£
`
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`Page 27 0f 51
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`Sheet 27 of 39
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`5,648,284
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`US. Patent
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`FIG.54
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`3.“
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`Page 28 0f 51
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`US. Patent
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`Jul. 15, 1997
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`Sheet 28 of 39
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`5,648,284
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`US. Patent
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`Jul. 15, 1997
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`Sheet 29 of 39
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`5,648,284
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`F1058
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`33
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`29
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`31
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`Page 30 0f 51
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`Sheet 30 of 39
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`29
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`FIG.60
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`5b
`
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`
`9-
`
`5km
`
`
`
`31
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`'1‘.tat-ulnlddtultlnvnlcnnnn*“CC...-"'l.""-.'u.'.-'-.
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`33/
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`15c:
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`15!:
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`Page 31 0f 51
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`IIUDDIJUUI"l'l'."".l'.l-
`
`5b
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`O.--"l...-'--.-.'-'..-Ia.
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`5‘0 - 3!
`
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`Page 31 of 51
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`US. Patent
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`Jul. 15, 1997
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`Sheet 31 of 39
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`5,648,284
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`‘50
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`9
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`15b
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`Page 32 0f 51
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`US. Patent
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`Jul. 15, 1997
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`Sheet 32 of 39
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`5,648,284
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`F1063
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`Jul. 15, 1997
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`Sheet 33 of 39
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`5,648,284
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`'FIG.65
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`FIG.66
`
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`Ia
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`Iaanmua'tmam*
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`mttlllll'
`
`
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`
`5°
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`Page 34 0f 51
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`9
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`5b
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`Page 34 of 51
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`Jul. 15, 1997
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`Sheet 34 of 39
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`5,648,284
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`FIG.67
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`Page 35 0f 51
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`US. Patent
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`Jul. 15, 1997
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`Sheet 35 of 39
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`5,648,284
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`US. Patent
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`Jul. 15, 1997
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`Sheet 36 of 39
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`5,648,284
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`PRIOR ART
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`Page 37 0f 51
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`Jul. 15, 1997
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`Sheet 37 Of 39
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`5,648,284
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`19b
`
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`CHE
`
`P
`
`
`LOW
`CONCENTRATION
`
`
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`“ DA HC
`
`
`MEDIUM
`CONCENTRATION
`
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`DAHC
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`HIGH
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`CONCENTRATION
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`DAHC
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`| g
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`CHE
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`CHE
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`Sheet 33 of 39
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`5,648,284
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`F16.75
`
`
`3°
`
`ORAIIV AVALANCHE
`
`
`HOT CARRIER
`
`CHANNEL HOT
`
`ELECTRON
`
`
`
`
`
`1.0
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`20
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`o 0
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`SILICON OXIDE
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`NITRIOEO
`( OXIDE FILM
`
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`1D
`20
`an
`50
`so
`3.0
`
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`GATE VOLTAGE
`
`[V]
`
`
`
`
`FIG.76
`
`DRAIN AVALANCHE
`
`
`HOT CARRIER
`
`CHANNEL HOT
`
`LE
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`GATE VOLTAGE
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`[V]
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`Page 39 Of 51
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`Jul. 15, 1997
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`Sheet 39 of 39
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`5,648,284
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`F16.77
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`99109 ART
`
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`"
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`10 10pm/1.0pm
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`40 VD(V)
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`1
`FIELD EFFECT TRANSISTOR INCLUDING
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`SILICON OXIDE FILM AND NITRIDED
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`
`
`
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`OXIDE FILM AS GATE INSULATOR FILM
`
`
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`
`
`AND MANUFACTURING METHOD
`
`
`
`THEREOF
`
`
`
`
`
`
`This application is a continuation of application Ser. No.
`
`
`
`
`
`
`
`
`08/341952 filed Nov. 16, 1994 now abandoned. which
`
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`
`
`application is a division of application Ser. No. 07/930,932
`
`
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`
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`
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`
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`filed Aug. 18. 1992 US. Pat. No. 5.369.297.
`
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`
`
`2
`nitridation time, re-oxidation time, an initial thickness of
`
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`silicon oxide film and the like. That is, when a nitriding
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`atmosphere is N20, nitrogen concentration is lower as
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`compared to the case with an ammonium gas even though
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`the same parameters are employed for other parameters. As
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`re-oxidation time becomes longer, nitrogen concentration
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`
`becomes lower. Nitrogen concentration becomes higher with
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`a higher nitridation temperature, a longer nitridation time, a
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`smaller initial thickness of silicon oxide film and a higher
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`ammonium concentration.
`
`
`There are two types of hot carriers that cause a deterio-
`
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`
`
`
`ration in characteristics of MOS field etfect transistors: drain
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`avalanche hot carriers and channel hot holes (electrons). A
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`channel hot hole (electron) phenomenon indicates a case
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`where holes (electrons) traveling in a channel region 11 are
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`accelerated by an electric field around drain 3b and then
`
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`enter in a gate insulator film 6 near drain 3b as shown in FIG.
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`72. Silicon substrate, source region and gate electrode are
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`denoted with reference characters 1, 3a and 7, respectively.
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`The channel hot holes (electrons) are also called channel hot
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`carriers. In a case with an NMOS transistor, channel hot
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`carriers are channel hot electrons, while in a case with a
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`PMOS transistor, channel hot carriers are channel hot holes.
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`A description will now be given on drain avalanche hot
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`carriers with reference to FIG. 73. When accelerated carriers
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`collide with lattice of Si, electron-hole pairs are generated
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`At that time. holes (electrons) are drawn by a gate voltage
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`and enter into gate insulator film 6. It depends on the type
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`gate insulator film 6. Electrons enter in the case of an NMOS
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`transistor, while holes enter in the case of a PMOS transistor.
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`Both the channel hot holes (electrons) and the drain
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`avalanche hot carriers are generated near the drain.
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`HoweVer, it appears that the channel hot holes (electrons) are
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`generated closer to the source than the drain avalanche hot
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`carriers. If a comparison is made between a gate voltage
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`generated, the gate voltage provided with generation of the
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`channel hot holes (electrons) is higher. As the gate voltage
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`becomes higher, the holes (electrons) which enter in gate
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`insulator film 6 are largely atfected by the gate electrode.
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`That is, with a larger gate electrode, the holes (electrons)
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`which enter in the gate insulator film are more strongly
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`drawn to the gate electrode.
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`In a portion of the gate electrode, into which hot carriers
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`are entered, interface states or traps are generated, causing a
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`deterioration in characteristics of MOS field effect transis-
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`tors. Interface state is an energy level which allows
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`transmission/reception of charges to/from Si substrate in a
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`Si—SiO2 interface region. Trap is a portion that serves to
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`trap or capture conduction electrons or holes contributing to
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`electric conduction to prevent the contribution to electric
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`conduction.
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`The drain avalanche hot carriers and the channel hot holes
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`(electrons) have the following nature. With reference to FIG.
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`74, this field effect transistor has an LDD structure. A high
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`concentration source region 1911 and a high concentration
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`drain region 19b are formed to be spaced apart from each
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`other in a silicon substrate. A low concentration source
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`region 15a is formed in the inside of high concentration
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`source region 19a, while a low concentration drain region
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`15b is formed in the inside of high concentration drain
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`region 19b. Sidewall
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`formed on opposite sides of a gate electrode 7.
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`Respective amounts of injected hot carriers in respective
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`cases where the concentration of low concentration drain
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`65
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`The present invention relates generally to field effect
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`transistors and. more particularly, to a field eifect transistor
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`including a silicon oxide film and a nitrided oxide film as a
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`gate insulator film, and a method of manufacturing such a
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`field effect transistor.
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`2. Description of the Background Art
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`A nitrided oxide film formed by a rapid lamp annealing is
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`a highly reliable insulator film to dielectric breakdown. This
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`is disclosed in, for example, “Extended Abstract of the 21st
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`Conference on Solid State Devices and Materials”, Tokyo,
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`p.197.
`The nitrided oxide film is such a film that a large amount
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`of nitrogen is included in an interface between the nitrided
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`oxide film and a material beneath the nitrided oxide film.
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`With a reduction in scale of devices, it is considered that
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`such a nitrided oxide film is employed as a gate insulator
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`film of a MOS (Metal Oxide Semiconductor) field etfect
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`transistor.
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`FIG. 71 is a schematic cross-sectional view of a MOS
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`field elfect transistor with a conventional single drain struc-
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`ture. Such a MOS field efiect transistor is disclosed in, for
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`example, Digest “International Electron Device Meeting
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`1989”. p. 267. A source region 3a and a drain region 3b are
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`formed with a spacing in a silicon substrate 1 having a main
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`surface 2. A nitrided oxide film 5 is formed on main surface
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`2 between source region 3a and drain region 312. A gate
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`electrode 7 is formed on nitrided oxide film 5.
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`A description will now be made on a method of manu-
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`facturing such a MOS field effect transistor. First, silicon
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`substrate 1 with a boron concentration of approximately
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`l><1017lcm2 is prepared. A silicon oxide film of 70 A is
`formed on main surface 2 of silicon substrate 1. This silicon
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`oxide film is then nitrided by lamp annealing in an atrno—
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`sphere including ammonium. The nitridation is carried out at
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`a temperature of 900° C.—1100° C. for 10—60 seconds. After
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`the end of niuidation, the silicon oxide film is re—oxidized in
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`an oxygen atmosphere. The re-oxidation is carried out at a
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`temperature of 1000° C.—1100° C. for 10—300 seconds.
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`Thus. nitrided oxide film 5 is formed.
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`Then, polycrystalline silicon of 2000—4000 A in thickness
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`is formed on nitrided oxide film 5. The polycrystalline
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`silicon film and nitrided oxide film 5 are then patterned by
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`employing photolithography and etching technique. to form
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`gate electrode 7. Silicon substrate 1 is then implanted with
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`arsenic ions with gate electrode 7 used as a mask. Accel-
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`eration energy is 30—70 keV and a dose is 1x1015lcm2 or
`more. After that, a resulting film is annealed to form source
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`region 3a and drain region 3b. The steps of manufacturing
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`the MOS field effect transistor is over through the foregoing
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`processings.
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`The concentration of nitrogen in nitrided oxide film 5
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`depends on a nitriding atmosphere, nitridation temperature,
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`Page 41 0f 51
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`Page 41 of 51
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`

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`5,648,284
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`4
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`3
`region 15b is low. medium and high are shown in the figure.
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`Channel hot electrons are denoted with CHE, and drain
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`avalanche hot carriers with DAHC. For the channel hot
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`electrons, its peak value of the amount of injected carriers
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`does not change even if the concentration of low concen-
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`tration drain region 15b changes. For the drain avalanche hot
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`carriers. its peak value (P) of the amount of injected carriers
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`increases with an increase in concentration of low concen-
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`tration drain region 15b. In addition, the peak value (P) of
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`the drain avalanche hot carriers shifts to the side of a channel
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`region with an increase in concentration of low concentra-
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`tion drain region 15b.
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`As the gate voltage becomes higher, a hot carrier resis-
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`tivity of nitrided oxide film becomes lower than that of
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`silicon oxide film. This is described as follows. A threshold
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`value (Vm) is measured before application of stresses. and
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`then stresses are applied. As stresses, the following four
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`conditions are provided: a gate voltage of 1.0 V in absolute
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`value, a drain voltage of 6.0 V and a time of 1000 seconds;
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`a gate voltage of 2.5 V (2.0 V for PMOS) in absolute value,
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`a drain voltage of 6.0 V and a time of 1000 seconds; a gate
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`voltage of 4.0 V in absolute value, a drain voltage of 6.0 V
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`and a time of 1000 seconds; and a gate voltage of 6.0 V in
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`absolute value, a drain voltage of 6.0 V and a time of 1000
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`seconds. After stresses are applied, threshold values are
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`measured. Thus, the difference between threshold values
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`before and after the application of stresses, Le, a shift of
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`threshold value is measured. FIG. 75 shows the case with an
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`NMOS field effect transistor, and FIG. 76 shows the case
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`with a PMOS field effect transistor. The lateral axis indicates
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`a gate voltage in the application of stresses. As the amount
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`of generated hot carriers increases, the shift of threshold
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`values increases.
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`As shown in FIG. 75, in the case with the NMOS field
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`effect transistor, if a gate voltage is lower, the shift of
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`threshold value for nitrided oxygen film is smaller than that
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`for silicon oxide film. That is, the hot carrier resistivity of the
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`nitrided oxide film is higher than that of silicon oxide film.
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`However. if the gate voltage is higher, the shift of threshold
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`values for the nitrided oxide film is larger than that for the
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`silicon oxide film.
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`In the case with the PMOS field effect transistor shown in
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`FIG. 76, if the absolute value of the gate voltage is smaller,
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`the shift of threshold values for the nitrided oxide film is
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`approximately the same as that for the silicon oxide film.
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`That is, the hot carrier resistivity of the nitrided oxide film
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`is the same as that of the silicon oxide film. However, if the
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`absolute value of the gate voltage is higher, the shift of
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`threshold values for the nitride oxide film is larger than that
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`for the silicon oxide film.
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`According to “1982 Symposium on VLSI Technology
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`Digest” p.40 by Eiji Takeda et a1, it is disclosed that when
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`a gate voltage is 4 V or less, drain avalanche hot carriers are
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`liable to be generated, and when the gate voltage is 4 V or
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`more. channel hot electrons are liable to be generated.
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`Therefore, as shown in FIG. 75, in the NMOS field effect
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`transistor, the nitrided oxide film is more resistive to drain
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`avalanche hot carriers as compared to the silicon oxide film,
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`and the silicon oxide film is more resistive to channel hot
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`electrons as compared to the nitrided oxide film. In the
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`PMOS field effect transistor, as shown in FIG. 76. both the
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`silicon oxide film and the nitrided oxide film exhibit
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`approximately the same resistivity to drain avalanche hot
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`carriers, and the silicon oxide film is more resistive to
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`channel hot holes as compared to the nitrided oxide film.
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`In a CMOS (Complementary MOS) circuit, it is possible
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`that either an NMOS transistor or PMOS transistor is put in
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`10
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`Page 42 0f 51
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`a high gate voltage state. As has been described above with
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`reference to FIGS. 75 and 76, when the nitrided oxide film
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`is used as a gate insulator film, if the absolute value of a gate
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`voltage is higher than that provided when the silicon oxide
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`film is used as the gate insulator film,
`the hot carrier
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`resistivity deteriorates in both the NMOS transistor and the
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`PMOS transistor. Accordingly, when the MOS transistor
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`including the nitrided oxide film as the gate insulator film is
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`incorporated into the CMOS circuit, such a disadvantage is
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`provided that
`the hot carrier resistivity of the circuit
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`decreases as compared to the transistor including the silicon
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`oxide film as the gate insulator film.
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`FIGS. 77 and 78 are diagrams showing voltage-current
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`characteristics of the MOS field effect transistor disclosed in
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`the aforementioned document, Digest “International Elec-
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`tron Device Meeting 1989,” p. 267. FIG. 77 shows the case
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`with the NMOS transistor, and FIG. 78 shows the case with
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`the PMOS transistor. In the figures, a symbol NO indicates
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`a nitrided oxide film, and PO indicates a pure oxide film.
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`As shown in FIG. 77, when an NMOS field effect tran-
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`sistor including an NO film as a gate insulator film is
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`employed at a lower gate voltage, such an NMOS field effect
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`transistor exhibits a lower current handling capability than
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`that of an NMOS field effect transistor including the pure
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`oxide film as the gate insulator film. As shown in FIG. 78,
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`when a PMOS field eflect transistor including the NO film
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`as the gate insulator film is employed. such a PMOS field
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`effect transistor exhibits a lower current handling capability
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`at any gate voltages as compared to a PMOS field effect
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`transistor including the pure oxide film as the gate insulator
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`film. The deterioration in current handling capability means
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`a deterioration in higher speed performance of circuits.
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`As the number of traps increases, the characteristics of the
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`field eifect transistor deteriorates. It is presumed according
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`to an experiment conducted by the inventor of the present
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`application that a nitride film has more traps than a nitride
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`oxide film. This will be described in embodiments of the
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`invention.
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`SUB/[MARY OF THE INVENTION
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`One object of the present invention is to provide a field
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`effect transistor having an NO film of high hot carrier
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`resistivity at a high gate voltage.
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`Another object of the present invention is to provide a
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`field effect transistor having a higher hot carrier resistivity at
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`a high gate voltage and a low gate voltage even if including
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`a nitrided oxide film.
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`A further object of the present invention is to provide a
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`field effect transistor exhibiting a higher current handling
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`capability at a low gate voltage even if including a nitrided
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`oxide film.
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`A still further object of the present invention is to provide
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`a method of manufacturing a field effect transistor having a
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`higher hot carrier resistivity at a high gate voltage even if
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`including a nitrided oxide film.
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`A still further object of the present invention is to provide
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