.
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`UIllted States Patent
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`
`
`Manukonda et al.
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`
`[19]
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`|||||||l|||||||l|IlllllllllllllllllllIllllllllllllllIllllllllllllllllllllll
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`U5005102816A
`
`[11] Patent Number:
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`
`
`[45] Date of Patent:
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`
`5,102,816
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`Apr. 7, 1992
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`437/44
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`. 437/44
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`,437/44
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`.357/23
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`437/44
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`4,837,180 6/1989 Chad ..........
`
`
`
`6/1989 Chiu et a1
`4,843,023
`
`
`
`
`
`4,855,247
`8/1989 Ma e161.
`
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`4,873,557 10/1989 Kito
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`
`
`4,998,150
`3/1991 Rodder e
`.
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`
`
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`0173953
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`
`6/1988 European 1361.011.
`0268941
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`'
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`
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`5/1937 Japan -
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`0046763
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`
`
`
`3/1989 United Kmsdom ~
`2214349
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`
`_
`.
`_
`Pfiester, “LDD MOSFET’S Usmg Disposable Sidewall
`
`
`
`
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`
`
`
`
`
`Spacer Technology”, IEEE Electron Device Letters,
`
`
`
`
`
`
`
`Vol- 91N0~4yApn 19881911 189-192-
`
`437/34
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`437/34
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`
`
`
`Related US. Application Data
`
`
`
`
`.
`.
`
`
`
`
`
`
`
`
`Contmuation of Ser. No. 499,783, Mar. 27, 1990, aban-
`doned-
`'
`
`Int. C1.5 ................... H01L 21/336; HOIL 27/092
`
`
`
`
`
`
`
`US. Cl. .......... .
`.............
`
`
`
`437/36,"£5"7'}5Li;'437/41, 437/56; 437/67;
`
`
`
`
`3 57/23. 3
`[58] Field of Search
`437/27, 23’ 29) 30’
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`437/34, 40, 41, 44, 56, 57, 238, 241, 235,
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`357/233; 156/643, 650, 651, 652, 653, 646
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`14 Claims, 7 Drawing Sheets
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`
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`
`
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`(List continued on next page.)
`'
`'
`‘
`_
`
`
`
`Pn'f’m’ Exam’l'e’‘01‘1‘ 91‘3"th
`
`
`
`Asststant Examiner—M. W11czewsk1
`w.” w .
`A
`A
`F,
`
`
`
`
`
`gent, or mn— 1 mm .KJdd
`ttorney,
`[57]
`ABSTRACT
`
`
`.
`~
`.
`.
`Selective etching of a conformal nltnde layer overlying
`
`
`
`
`
`
`
`a conformal oxide layer and a subsequent etching of the
`
`
`
`
`
`
`
`
`
`oxide layer provide for a staircase shaped sidewall
`
`
`
`
`
`
`
`
`spacer which is used to align source and drain regions
`
`
`
`
`
`
`
`
`
`
`during implantation. Extent of the implanted n—/n+
`
`
`
`
`
`
`
`and/or —/ + re ‘ons within the substrate can be
`
`
`
`
`
`
`
`
`3‘
`P
`P
`
`
`
`
`
`
`
`tightly controlled due to the tight dimensional toler-
`ances obtained by the footprint of the spacer. Further
`
`
`
`
`
`
`
`
`the source/drain profiles can be utilized with elevated
`
`
`
`
`
`
`
`'polysilicon and elevated polysilicon having subsequent
`
`
`
`
`
`salicidafim
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`[75]
`
`
`[54] STAIRCASE SIDEWALL SPACER FOR
`
`
`
`
`IMPROVED SOURCE/DRAIN
`
`
`ARCHITECI‘URE
`
`Inventors: V. Reddy Manukouda; Thomas E.
`
`
`
`
`
`
`
`
`
`
`se'dd’ b°th °f Aust‘f" Tex“
`_
`
`
`
`
`
`
`[73] Assxgnee: Semtech, Inc., Austin, Tex.
`[211 Appl. No.: 679,160
`
`
`
`
`.
`
`[22] “Ed:
`Mar-25a 1991
`
`
`
`
`
`,
`
`
`[63]
`
`[51]
`
`
`
`[56]
`
`
`
`
`
`
`
`.....
`
`..
`
`
`
`..
`
`...... 437/41
`
`
`...... 437/44
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`357/23
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`437/34
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`437/44
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`437/34
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`437/44
`437/44
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`"437/162
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`u 437/44
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`156/643
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`437/37
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`437/57
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`437/57
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`437/34
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`437/44
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`437/34
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`437/44
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`Page 1 of 17
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`TSMC Exhibit 1039
`TSMC v. IP Bridge
`IPR2016-01246
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`

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`5,102,816
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`Page 2
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`
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`CMOS Devices with Self—Aligned Shallow—Deep
`
`
`
`
`Junctions, pp. 487—489.
`
`
`
`IEEE, Feb. 1985, Matsumoto et al., An Optimized and
`
`
`
`
`
`
`
`
`
`Reliable LDD Structure for l—p.m NMOSFET Based
`
`
`
`
`
`
`
`on Substrate Current Analysis, pp. 429—433.
`
`
`
`
`
`
`IEEE, Feb. 1986, Huang et al., A Novel Submicron
`
`
`
`
`
`
`
`
`LDD Transistor with Inverse—T Gate Structure IEDM
`
`
`
`
`
`
`86, pp. 742—745.
`
`
`
`IEEE, Oct. 1984, Oh and Kim, A New MOSFET
`
`
`
`
`
`
`
`
`
`Structure with Self-Aligned Polysilicon Source and
`
`
`
`
`
`
`Drain Electrodes, pp. 400—402.
`
`
`
`
`IEEE, Jul. 1989, Yamada et al., Spread Source/Drain
`
`
`
`
`
`
`
`
`(SSD) MOSFET Using Selective Silicon Growth for
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`OTHER PUBLICATIONS
`
`
`IBM Technical Disclosure Bulletin, v0]. 32, No. 5A,
`
`
`
`
`
`
`
`Oct. 1989, “Method for Making Lightly Doped Drain
`
`
`
`
`
`
`
`Shallow Junctions”, pp. 110—111.
`
`
`
`
`IBM Technical Disclosure Bulletin, vol. 28, No. 1, Jun.
`
`
`
`
`
`
`
`
`
`1985, “New Scheme to Form Shallow N+ and P+
`
`
`
`
`
`
`
`
`
`Junctions for MOS Devices”, pp. 366—367.
`
`
`
`
`
`
`-2244 Research Disclosure (1989) Jul., No. 303, New
`
`
`
`
`
`
`
`York, U.S., “Method for Making Devices having Re-
`
`
`
`
`
`
`
`duced Field Gradients at Junction Edges", p. 496.
`
`
`
`
`
`
`
`
`1988 Symposium on VLSI Technology, Oh et al., Si-
`
`
`
`
`
`
`
`
`multaneous Formation of Shallow-Deep Stepped Sour-
`
`
`
`
`
`ce/Drain for Sub—Micron CMOS, May 10—13, 1988, pp.
`
`
`
`
`
`
`
`
`73—74.
`
`
`IEEE, Nov. 1989, Lu et 31., Submicrometer Salicide
`
`
`
`
`
`
`
`
`64Mbit Drams pp. 2.4.1—2.4.4.
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`US. Patent
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`Apr. 7, 1992
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`Sheet 1 of 7
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`5,102,816
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`“—
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`103/0)? A277 ‘
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`Apr. 7, 1992
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`US. Patent
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`Sheet 3 of 7
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`5,102,816
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`

`spacers.
`
`2
`
`SUMMARY OF THE INVENTION
`
`
`
`
`A “staircase” gate sidewall spacer is described in
`
`
`
`
`
`
`
`which tighter dimensional tolerances of the spacer pro-
`
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`vides for a tighter control of source-drain spacing and
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`source and drain doping profiles particularly as applied
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`to “double doped” source and drain regions. The side-
`
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`wall spacer is utilized to align areas of a substrate for ion
`
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`implantation of the source and drain regions. The
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`source and drain regions can be either an n~channel
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`device or a p-channel device. By combining the n-chan-
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`nel and the p-channel, a CMOS device can be fabri-
`
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`cated.
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`After a gate is formed over a substrate, a conformal
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`oxide layer and then a conformal nitride layer are
`
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`formed. Subsequent anisotropic etching leaves an oxide
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`spacer adjacent to the gate sidewall, primarily due to
`
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`the selective etching of the overlying nitride layer.
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`After the removal of the remaining nitride by either
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`isotropic or anisotropic etching, a staircase sidewall
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`oxide spacer remains. Subsequently, an n—(or p—)
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`implant is performed, followed by an n+ or (p+) im-
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`plant to form the “double doped” source and drain
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`regions.
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`Because the first implant is performed at a higher
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`energy level, ions penetrate the lower portion of'the
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`stair case shaped spacer. The second implant is achieved
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`at a lower energy level than the first, so that the ions do
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`not readily penetrate the spacer. Thus, after annealing,
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`in which ion damage is removed and the implants are
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`controllably diffused further into the substrate, a separa-
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`tion region of n—(or p—) resides between the n+ or
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`(p+) region and the channel region. Further, because
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`the “footprint” dimensions of the spacers can be tightly
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`controlled during their formation, sharper definition of
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`the location of the source and drain regions is achieved.
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`Furthermore, considerable process simplification is
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`achieved by the process architecture of the present
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`invention. In particular, both n—— and n+(or p- and
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`p+) implants can be performed in one ion implant ma-
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`chine operation. Thus, reducing the process step count
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`and allows for cost and yield-risk reduction in manufac-
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`turing.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a cross-sectional View showing a formation
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`of a gate and subsequent oxide layer to form a prior art
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`MOS device.
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`FIG. 2 is a cross—sectional view showing a formation
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`of n—/n+ source and drain regions for the prior art
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`device of FIG. 1.
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`FIG. 3 is a cross-sectional view showing the unpre-
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`dictability of the formation of source and drain regions
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`of the prior art device of FIG. 2, due to variations in the
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`slope of the sidewall oxide.
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`FIG. 4 is a cross-sectional view of the present inven-
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`tion showing a formation of a gate on a silicon substrate
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`and a subsequent formation of an oxide layer above the
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`gate and the substrate.
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`FIG. 5 is a cross—sectional view of a formation of a
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`nitride layer over the oxide layer of FIG. 4.
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`FIG. 6 is a cross‘sectional view of a gate region of a
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`device of the present invention, in which sidewall spac-
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`ers remain after etching the oxide and nitride layers of
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`FIG. 5.
`
`FIG. 7 is a cross-sectional view of the device of FIG.
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`6 after removal of the nitride remnant on the sidewall
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`This application is a continuation, of application Ser.
`
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`
`
`No. 499,783, filed Mar. 27, 1990, now abandoned.
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`The present invention relates to the field of MOS 10
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`integrated circuits and, particularly to the process of
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`forming source and drain regions of a CMOS integrated
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`circuit device.
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`2. Prior Art
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`In the design of integrated circuits various processes 15
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`are known for fabricating the actual device. Techniques
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`have evolved over the years in which various layers are
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`formed onto a silicon substrate, wherein these layers are
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`subjected to one or more of a variety of photolitho-
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`graphic, patterning, etching, exposing, implanting steps,
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`etc., in order to form the desired device One type of
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`integrated circuit
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`(MOS) field-effect transistor (FET) in which source
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`and drain regions of the transistor are separated by a
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`channel region underlying the gate of the transistor.
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`Where the transistor is formed on the substrate, source
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`and drain regions are formed in the substrate and the
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`gate region resides above the surface of the substrate.
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`Typically the source and drain regions are formed by
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`doping the substrate in the area where these regions are
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`to be formed. Ion implantation is one technique for
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`doping the source and drain. Using gate alignment, the
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`gate or the gate and an adjacent dielectric spacer are
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`used to align the substrate area where the doping is to
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`occur. A well known practice is to provide a first im-
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`plant to define a first implanted area and a second im-
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`plant to define a second implanted area. The second
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`implanted area is the actual source or drain and the first
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`implanted area provides a graded doping or lightly
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`doped region between the source or the drain from the
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`channel, in order to provide improved device integrity,
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`especially higher breakdown drain voltages.
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`Although these techniques are well-known, the vari-
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`ous specific processes are applicable for fabricating
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`devices of a certain size. As device geometry shrinks,
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`attempts are made to form more and more transistors on
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`a given area of a semiconductor wafer. For example, a
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`semiconductor device fabricated utilizing “submicron”
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`technology will contain many more circuit elements per
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`unit area than a device fabricated using “above-micron"
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`technology. However, as device size continues to
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`shrink, the dimensional tolerances required of the vari-
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`ous formed layers and/or devices also shrink and be-
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`come more critical. Thus tolerances adequate for form-
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`ing source and drain regions for a given size device,
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`such as a device fabricated using 1.5 micron technol-
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`ogy, may be inadequate for improved devices, such as a
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`device fabricated using 0.35, 0.5 or even 0.8 micron
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`technology.
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`invention provides for an improved
`The present
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`method of forming source and drain regions in a semi-
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`conductor device, wherein the sharper definition, such
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`as tighter control of source-drain spacing and source
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`and drain doping profiles, of these regions permit for
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`the fabrication of devices using submicron technology.
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`Further, the improved method also provides for an ease
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`of manufacture in fabricating the device.
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`1
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`STAIRCASE SIDEWALL SPACER FOR
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`IMPROVED SOURCE/DRAIN ARCHITECTURE
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`5,102,816
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`5
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`Page 10 of 17
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`3
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`FIG. 8 is a cross-sectional View showing an n— im-
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`plant to form n— source and drain regions to the device
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`of FIG. 7.
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`FIG. 9 is a cross—sectional view showing an n+ im-
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`plant to form n+ source and drain regions to the device
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`of FIG. 8.
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`FIG. 10 is a cross-sectional view showing the source
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`and drain regions of the device of FIG. 9 after anneal-
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`ing, in which n—/n+ regions diffuse further into the
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`substrate.
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`FIG. 11 is a cross—sectional View showing the forma-
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`tion of sidewall spacers to respective gates of both n-
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`channel and p-channel areas of a CMOS device of the
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`present invention.
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`FIG. 12 is a cross-sectional view showing an n—
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`implant to form n— source and drain regions to the
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`device of FIG. 11.
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`FIG. 13 is a cross-sectional view showing an n+
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`implant to form n+ source and drain regions to the
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`device of FIG. 12.
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`FIG. 14 is a cross-sectional view showing a p—- im-
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`plant to form p— source and drain regions to the device
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`of FIG. 13.
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`FIG. 15 is a cross-sectional View showing a p+ im-
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`plant to form p+ source and drain regions to the device
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`of FIG. 14.
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`FIG. 16 is a cross-sectional view showing the CMOS
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`device of FIG. 15 after annealing.
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`FIG. 17 is a cross-sectional view showing an altema—
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`tive embodiment in which an elevated polysilicon layer
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`is formed above a substrate and adjacent to sidewall
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`spacers of the present invention.
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`FIG. 18 is a cross-sectional view showing a formation
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`of n—/n+ source and drain regions underlying the
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`elevated polysilicon of FIG. 17.
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`FIG. 19 is a cross-sectional view showing a CMOS
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`device of the alternative embodiment in which n—/n +
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`and p——/p+ source and drain regions are formed un-
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`derlying elevated polysilicon.
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`FIG. 20 is a cross-sectional view showing a CMOS
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`device of another alternative embodiment in which an
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`elevated polysilicon layer is formed above a substrate
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`and adjacent to sidewall spacers, but having a thickness
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`that elevates the polysilicon layer above the foot of the
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`spacer in order to implant a narrow region in the sub-
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`strate.
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`FIG. 21 is a cross—sectional view of the elevated
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`polysilicon device of FIG. 20, but having a subsequent
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`salicidation layer.
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`DETAILED DESCRIPTION OF THE PRESENT
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`INVENTION
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`A process for fabricating a semiconductor device
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`using stepped spacer for improved formation of doped
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`regions is described. A prior art technique is first de-
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`scribed in order to provide a better understanding of the
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`advantages derived by the practice of the present inven-
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`tion. In the following description, numerous specific
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`details are set forth, such as specific thicknesses, tem-
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`peratures, etc., in order to provide a thorough under-
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`standing of the present invention. It will be obvious,
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`however, to one skilled in the art that the present inven-
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`tion may be practiced without these specific details. In
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`other instances, well-known processes have not been
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`described in detail in order not to unnecessarily obscure
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`the present invention.
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`doping of the n-region. An advantage of the n—l— being
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`PRIOR ART
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`Referring to FIG. l, a prior art semiconductor device
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`M) is shown. Device 10 is a metal-oxide-scmiconductor
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`(MOS) device having a substrate 11, which substrate 11
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`typically comprised of silicon. Circuit elements
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`formed on substrate 11 are typically separated by field-
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`oxide regions, such as field-oxide regions 12 of FIG. 1.
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`A gate 14 is then formed on substrate 11. Gate 14 is
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`typically comprised of a polysilicon region 15 separated
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`from the substrate 11 by a dielectric region 16, which
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`dielectric 16 is typically comprised of an oxide such as
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`silicon oxide (SiOz).
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`Utilizing a self-aligned technique, the gate 14 is used
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`to define a channel region in the substrate 11 underlying
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`the gate 14. A source and drain regions are then subse-
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`quently defined as the regions of the substrate bounding
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`the channel region, such that the source and drain re-
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`gions do not extend appreciably into the substrate ll
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`underlying gate 14. Prior to forming the source and
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`drain regions, an oxide layer 17 is deposited.
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`By using well~known photoresist deposition, photo—
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`lithographic and etching techniques, oxide layer 17 is
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`etched to expose portions of substrate 11 for the pur-
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`pose of forming the source and drain regions as shown
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`in FIG. 2. The etching process is typically anisotropic
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`such that a portion of oxide layer 17 remains adjacent to
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`the vertical sides of gate 14. In some instances, a portion
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`of the oxide layer 17 also remains above gate 14. The
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`portion of the oxide layer 17 remaining adjacent to gate
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`14 is commonly referred to as a spacer, thus gate 14 is
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`bounded by spacer regions 22, as shown in the cross-
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`sectional illustration of FIG. 2.
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`Next, a masking technique is used to expose only
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`those areas which will be subjected to implantation. As
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`shown in FIG. 2, a n—— region 23 is formed due to an
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`n— implantation. Subsequently, a Second masking step
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`is utilized to define an area for performing the n+ im-
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`plantation. The n+ region 24 resides within n— region
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`23 and this demarcation is especially important in the
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`region proximate to the channel region underlying the
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`gate 14. An annealing step is used to anneal the source
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`and drain, which annealing step extends the n— and n+
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`regions further toward the channel region and in some
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`instances, the n—— region extends into the channel re-
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`gion, but not extending appreciably into the channel
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`region underlying the gate 14. One such prior art tech-
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`nique to form n— and n +(“double doped") source and
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`drain regions is described in Matsumoto et al., “An
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`Optimized and Reliable LDD Structure for 1-um
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`NMOSFE’I‘ Based on Substrate Current Analysis,
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`IEEE Transactions on Electron Devices, Vol. ED-32,
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`No. 2, Feb. 1985, pp 429—433, in which a lightly doped
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`drain (LDD) structure is discussed.
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`The spacers 22, in‘ conjunction with gate 14, function
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`to align the substrate 11 for the implantation step. Spac-
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`ers 22 are used to ensure that n— and n+ region 23 and
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`24 profiles are distinct and that the n—, or both 11— and
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`n+ regions 23 and 24, do not extend appreciably into
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`the channel region underlying the gate 14. Further, it is
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`to be noted that two separate masks and masking steps
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`are necessary to first implant the n— region 23 and a
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`second step to implant the n+ region 24 in order to
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`provide a separation of the n+ region from the channel
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`region for the purpose of providing better source and
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`drain isolation from the channel region. In some in-
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`stances the n+ region is doped first, followed by the
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`5,102,816
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`Page 11 of 17
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`5,102,816
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`25
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`performed first is that ion channeling effects can be
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`reduced slightly.
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`The width of the region underlying each of the side-
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`wall spacers 22 is commonly termed a “footprint”. For
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`device 10 of FIG. 2, a footprint for one of the sidewall
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`spacers 22 is shown by the footprint distance 27. It is to
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`be appreciated that the width of footprint 27 is a critical
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`measurement for determining the extent of the horizon-
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`tal penetration of n— region 23 in the substrate. A loose
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`tolerance of the width of footprint 27 will necessarily
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`result in a wide disparity of the extent of the penetration
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`of n— region 23 and, hence, will more than likely im-
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`pact the extent of the penetration of n+ region 24. The
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`recognition of this variance is a key factor to the under-
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`standing the motivation behind the practice of the pres-
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`ent invention. Therefore, it is desirable to maintain a
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`small variance about a mean value specified for the
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`width of the footprint 27.
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`As shown in FIG. 3, a variation in the slope of the
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`sidewall spacer 22 causes a corresponding difference in
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`the width of the footprint 27 and this variation in the
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`slope is illustrated by slope (shown as dotted lines) 30
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`and 31. This difference in the width of the footprint 27
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`will cause n+ region 24 and/or n— region 23 to vary
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`correspondingly (shown as doped regions 32 and 33)
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`from the channel region underlying the gate 14. Any
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`significant variation of the location of n+ region 24
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`and/or n— region 23, will ultimately affect the operat-
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`ing parameters of the device 10, such as threshold,
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`punchthrough voltage, and source-drain leakage cur‘
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`rent. It is to be noted that in the example of FIG. 3,
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`doped region 33 can extend significantly toward or
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`even into the channel region. When region 33 extends
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`appreciably into the channel region, it can present an
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`undesirable, or even fatal (in the case of extremely short
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`channel devices), condition for the transistor.
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`A variety of factors affect the dimensional width of
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`the footprint 27. More notable factors are the gate 14
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`profile, as well as its uniformity, slope of the sidewall
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`spacer 22, depositon non-uniformity of oxide layer 17
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`and etch non-uniformity of oxide layer 17 to form side-
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`wall spacer 22, the non-uniformity being across the
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`wafer. Additionally, in some instances where the slope
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`of the sidewall spacer 22 varies, during subsequent
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`metal formation steps, metal “stringers” can extend
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`from the metal contacts at the source and/or drain
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`regions, along the sidewall 22 to a gate contact line
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`residing on the upper portion of the gate 14. This condi-
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`tion can cause an electrical short of the source and/or
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`drain to the gate.
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`Finally it is to be noted that similar problems are
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`encountered in the formation of a p-channel device. The
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`p— and p+ implants are equivalent to the n— and n+
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`implants, respectively. However, the results or effects
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`of the footprint tolerance variation appears to be more
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`pronounced with n-channel devices than with p-chan-
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`nel devices. Furthermore, it is appreciated that the vari-
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`ation in the footprint 27 is less critical when applicable
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`, to a device utilizing 1.5 micron technology since the
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`tolerances are not as critical. But when a device using
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`smaller micron technology, such as 0.8, 0.5 or 0.35 mi—
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`cron technology,
`is fabricated, then these tolerances
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`become progressively more critical due to the nearer
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`spacing of device elements and contacts.
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`It is appreciated that a semiconductor device of the
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`present invention provides for the shortcomings in the
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`prior art device in order to fabricate semiconductor
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`devices utilizing submicron technology under 1.0 mi-
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`However, with device 40 of the present invention, ni-
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`crons, more notably the use of 0.8, 0.5 and 0.35 micron
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`and smaller technologies. Furthermore, it is appreciated
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`that
`techniques have been suggested for improving
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`steps for submicron “double doped” source and drain.
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`One such technique utilizing an inverse T-gate structure
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`for submicron LD transistor is described in Huang et
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`a1.,“A Novel Submicron LDD Transistor with Inverse
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`T-Gate Structure”, IEEE IDEM, 1986, pp 742—745.
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`THE PREFERRED EMBODIMENT
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`Referring to FIG. 4, a semiconductor device 40 of the
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`preferred embodiment is shown. Device 40 is a MOS
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`device having a substrate 41 which is typically com-
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`prised of silicon. Field oxide regions 42 are formed on
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`the substrate 41 to localize the formation of circuit ele-
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`ments. Field oxide regions are shown in FIG. 4 to iso-
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`late an area of device 40 for the formation of a given
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`circuit element. A gate 44 is formed on substrate 41,
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`which gate 41 is comprised of a polysilicon region 45
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`separated from the substrate 41 by a dielectric region
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`46. The dielectric region is typically comprised of an
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`oxide, such as silicon dioxide (Si02).
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`After the formation of gate 44, an oxide layer 47 is
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`deposited over the device 40. In the preferred embodi-
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`ment, oxide layer 47 is comprised of a conforrnally
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`coated silicon dioxide (Si02) and is deposited by a well-
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`known suitable chemical vapor deposition (CVD) pro-
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`cess in order to obtain the conformal topology (confor-
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`mal meaning that the deposited layer conforms to the
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`underlying topology). Such deposition of Si02 is well-
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`known in the prior art. CVD oxide layer 47 is deposited
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`to a thickness range of approximately loo—1,000 ang—
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`stroms. Si02 is preferred in that Si02 provides for mini-
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`mal and controllable interface charge states afforded by
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`Si02 on the underlying silicon.
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`Referring to FIG. 5, a CVD conformal nitride layer
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`48 is next deposited over the CVD oxide layer 47. Ni-
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`tride layer 48 is deposited by CVD, such as by thermal
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`decomposition of silane SiH4 and ammonia NH4 to a
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`thickness of approximately 100—1,000 angstroms. Thus
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`the nitride layer 48 of the preferred embodiment is com-
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`prised of silicon nitride Si3N4, although any disposable
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`material with good etch selectivity against Si02 and Si
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`can be used. Polysilicon can be used but is less preferred
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`because of its conductance should any residue remain in
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`the subsequent steps below.
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`Subsequently, both layers 47 and 48 are selectively
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`etched to expose portions of the substrate 41 between
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`the FOX regions 42 and gate 44. The exposed substrate
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`areas will later form the source and drain regions about
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`gate 44. Nitride layer 48 is etched with high selectivity
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`to Si02 first and then Si02 layer 47 is etched with high
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`selectivity to both silicon and nitride. This technique
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`allows for end-point detection and highly defined stair-
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`cas