`
`
`
`
`
`(12) United States Patent
`
`
`US 6,218,266 B1
`
`
`(10) Patent N0.:
`
`
`
`
`
`
`
`
`Sato et al.
`(45) Date of Patent:
`
`*Apr. 17, 2001
`
`
`
`USOO6218266B1
`
`
`
`
`
`(54) METHOD OF FABRICATING ELECTRONIC
`
`
`
`
`DEVICES OF THE TYPE INCLUDING
`
`
`
`
`
`SMOOTHING PROCESS USING POLISHING
`
`
`
`
`
`
`
`
`(75)
`
`
`
`Inventors: Junichi Sat0, Tokyo; Tetsuo G0ch0,
`
`
`
`
`
`Kanagawa, both of (JP)
`
`
`
`
`
`
`
`(73) Assignee: Sony Corporation, Tokyo (JP)
`
`
`
`
`
`
`
`
`(*) Notice:
`
`
`
`
`
`This patent issued on a continued pros-
`
`
`
`
`
`
`ecution application filed under 37 CFR
`
`
`
`
`
`
`1.53(d), and is subject to the twenty year
`
`
`
`
`
`
`
`
`
`patent
`term provisions of 35 U.S.C.
`
`
`
`
`
`
`154(a)(2).
`
`
`Subject to any disclaimer, the term of this
`
`
`
`
`
`
`
`patent is extended or adjusted under 35
`
`
`
`
`
`
`U.S.C. 154(b) by 0 days.
`
`
`
`
`
`
`
`
`OTHER PUBLICATIONS
`
`
`
`
`
`
`Davari et al. “A variable—stress shallow trench isolation
`
`
`
`
`
`
`
`(STI) technology with diffused sidewall doping for submi-
`
`
`
`
`
`
`
`cron CMOS” IEDM, pp. 92—95, Dec. 1988.*
`
`
`
`
`
`
`
`B. Davari et al., “A New Planarization Technique, Using a
`
`
`
`
`
`
`
`
`
`
`Combination of RIE and CMP,” IEEE—IEDM Jul. 1989, pp
`
`
`
`
`
`
`
`
`
`61—64.*
`
`S. Wolf, Silicon Processing for the VLSI Era, vol. 2, Lattice
`
`
`
`
`
`
`
`
`
`
`Press, Sunset Beach, CA, 1990, pp 237—9, 285—6.*
`
`
`
`
`
`
`
`
`G. Smith et al., “Sidewall—Tapered Oxide by Plasma—En-
`
`
`
`
`
`
`
`hanced CVD,” J. Electrochem. Soc., vol. 132, No. 11, pp
`
`
`
`
`
`
`
`
`
`
`2721—5, Nov. 1985.*
`
`
`
`K. Machida et al., “SiO2 Planarization Technology with
`
`
`
`
`
`
`
`
`Brasing and ECR Plasma .
`. ” J. Vac. Sci. Technol., B vol.
`.
`
`
`
`
`
`
`
`
`
`
`
`B—4, No. 4, pp 818—21, Jul/Aug. 1986.*
`
`
`
`
`
`
`
`
`
`
`(21) Appl. No.: 07/858,632
`
`
`
`
`
`
`(22)
`
`
`
`Filed:
`
`
`
`Mar. 27, 1992
`
`
`
`
`
`* cited by examiner
`
`
`
`
`
`
`(30)
`
`
`Mar. 28, 1991
`
`
`
`Foreign Application Priority Data
`
`
`
`
`(JP) ................................................. .. 3—089573
`
`
`
`
`
`Primary Examiner—Charles Bowers
`
`
`Assistant Examiner—Erik J Kielin
`
`
`
`(74) Attorney, Agent, or Firm—Sonnenschein, Nath &
`
`
`
`
`
`
`
`Rosenthal
`
`
`
`
`
`
`(51)
`
`
`
`Int. Cl.7 ................................................... .. H01L 21/76
`
`
`
`
`
`
`
`
`
`(52) US. Cl.
`
`
`
`
`
`........................ .. 438/427; 438/424; 438/631;
`
`
`
`438/645
`
`(58) Field of Search ................................... .. 156/643, 645;
`
`
`
`
`
`
`
`437/228, 235, 438/631, 645, 424, 427
`
`
`
`
`
`
`
`(56)
`
`
`
`(57)
`
`
`
`ABSTRACT
`
`
`
`In a method of fabricating electronic components of the type
`
`
`
`
`
`
`
`
`
`wherein trenches formed in a substrate are filled up with a
`
`
`
`
`
`
`
`
`
`
`
`filling material deposited by a deposition process achieving
`
`
`
`
`
`
`
`
`etching and deposition concurrently, the improvement which
`
`
`
`
`
`
`
`comprises portions of the filling material deposited on those
`
`
`
`
`
`
`
`
`
`portion of the substrate other than those corresponding to the
`
`
`
`
`
`
`
`
`
`
`trenches are leveled up to the same height by an additional
`
`
`
`
`
`
`
`
`
`
`
`deposition of the filling material, or alternatively by a
`
`
`
`
`
`
`
`
`
`full-surface etch back process. With this leveling of the
`
`
`
`
`
`
`
`
`
`deposited material, a subsequent polishing operation can be
`
`
`
`
`
`
`
`
`performed smoothly with high accuracy. During the polish-
`
`
`
`
`
`
`
`ing operation, the resistance between a conductive polish-
`
`
`
`
`
`
`
`stop layer on the substrate and a surface of a polishing
`
`
`
`
`
`
`
`
`
`
`member contacting the substrate is monitored to determine
`
`
`
`
`
`
`
`a polish end.
`
`
`
`
`
`
`
`9 Claims, 14 Drawing Sheets
`
`
`
`
`
`
`
`References Cited
`
`
`U.S. PATENT DOCUMENTS
`
`
`
`.................... .. 156/643
`7/1986 Mercier et al.
`4,601,781 *
`
`
`
`
`
`
`................... .. 437/228
`3/1988 Machida et al.
`4,732,761 *
`
`
`
`
`
`
`4/1988 Lasky .............. ..
`4,735,679 *
`156/636
`
`
`
`
`
`4,793,895 * 12/1988 Kaanta et al.
`156/636
`
`
`
`
`
`
`4,872,947 * 10/1989 Wang et al.
`..
`156/643
`
`
`
`
`
`
`
`4,910,155 *
`3/1990 Cote etal.
`156/637
`
`
`
`
`
`
`
`437/228
`5,026,666 *
`6/1991 Hills et al.
`
`
`
`
`
`
`. . . . . . .. 437/8
`5,036,015 *
`7/1991 Sandhu . . . . . .
`
`
`
`
`
`437/228
`5,084,419 *
`1/1992 Sakao
`
`
`
`
`
`................................ .. 437/228
`5,089,442 *
`2/1992 Olmer
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`41
`
`
`
`
`
`
`
`
`
`Page 1 of 20
`
`TSMC Exhibit 1034
`
`TSMC v. IP Bridge
`IPR2016-01246
`
`Page 1 of 20
`
`TSMC Exhibit 1034
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

`
`US. Patent
`
`
`
`Apr. 17, 2001
`
`
`
`
`Sheet 1 0f 14
`
`
`
`
`
`
`
`
`US 6,218,266 B1
`
`
`
`
`
`Fig.1A
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 2 0f 20
`
`Page 2 of 20
`
`

`

`
`US. Patent
`
`
`
`Apr. 17, 2001
`
`
`
`
`Sheet 2 0f 14
`
`
`
`
`
`
`
`
`US 6,218,266 B1
`
`
`
`
`33'
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 3 0f 20
`
`Page 3 of 20
`
`

`

`
`US. Patent
`
`
`
`Apr. 17, 2001
`
`
`
`Sheet 3 0f 14
`
`
`
`
`
`
`
`
`US 6,218,266 B1
`
`
`
`Fig.2A
`
`PRESENT INVENTION
`
`
`
`
`
`
`P
`
`(3)
`
`
`
`
`ml..-
`
`II
`
`
`
`22
`
`23
`
`
`
`
`‘
`
`
`
`Fi g . 2 B
`
`
`PRIOR AP§T
`
`
`
`
`
`
`
`
`
`
`
`
`Page 4 0f 20
`
`
`
`
`
`
`
`
`
`
`Page 4 of 20
`
`

`

`
`US. Patent
`
`
`
`Apr. 17, 2001
`
`
`
`
`
`
`
`Sheet 4 0f 14
`
`
`
`
`
`
`US 6,218,266 B1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`.
`
`.
`
`
`
`
`
`
`
`Page 5 0f 20
`
`
`
`
`
`A
`
`Page 5 of 20
`
`

`

`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`US 6,218,266 B1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ge6 0f20
`
`Page 6 of 20
`
`

`

`
`US. Patent
`
`
`
`Apr. 17, 2001
`
`
`
`Sheet 6 0f 14
`
`
`
`
`
`
`
`
`US 6,218,266 B1
`
`
`
`Fig.4A
`
`
`
`722/1°“
`
`
`
`
`
`
`
`
`
`
`
`Page 7 of 20
`
`

`

`
`US. Patent
`
`
`
`Apr. 17, 2001
`
`
`
`Sheet 7 0f 14
`
`
`
`
`
`
`
`
`US 6,218,266 B1
`
`
`
`Fig.6
`
`
`
`
`
`CENTRAL PORTION
`
`
`OF WAFER
`
`RATE
`DEPOSITION
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 8 0f 20
`
`
`
`
`
`
`PERIPHERAL
`
`
`PORTION OF
`
`WAFER
`
`
`
`
`
`Si H4/N20
`
`
`CONDITION (1)
`
`CONDITIONQ)
`
`Page 8 of 20
`
`

`

`
`US. Patent
`
`
`
`Apr. 17, 2001
`
`
`
`
`
`
`
`Sheet 8 0f 14
`
`
`
`
`
`US 6,218,266 B1
`
`
`
`Fig.7A
`
`
`
`w F
`
`
`ig.7B
`@1177 (B')
`.1 1
`
`
`
`
`
`Fig.8
`
`
`m 1
`
`
`
`Page 9 of 20
`
`

`

`
`US. Patent
`
`
`
`Apr. 17, 2001
`
`
`
`Sheet 9 0f 14
`
`
`
`
`
`
`
`
`US 6,218,266 B1
`
`
`
`
`Fig.9A
`
`
`
`
`
`41
`
`--.“-“----
`
`“.“‘-‘---
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 10 0f 20
`
`Page 10 of 20
`
`

`

`
`US. Patent
`
`
`
`Apr. 17, 2001
`
`
`
`
`Sheet 10 0f 14
`
`
`
`
`
`
`
`
`US 6,218,266 B1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 11 of 20
`
`

`

`
`
`
`
`
`
`Sheet 11 0114
`
`
`
`
`
`
`
`US. Patent
`
`
`
`A r. 17 2001
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 12 of 20
`
`

`

`
`US. Patent
`
`
`
`Apr. 17, 2001
`
`
`
`Sheet 12 0f 14
`
`
`
`
`
`
`
`
`US 6,218,266 B1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Iili‘
`
`
`
`
`
`
`
`
`
`
`
`
`22
`
`
`21
`
`Page 13 0f 20
`
`Page 13 of 20
`
`

`

`
`US. Patent
`
`
`
`Apr. 17, 2001
`
`
`
`
`
`Sheet 13 0f 14
`
`
`
`
`
`
`
`
`US 6,218,266 B1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 14 0f 20
`
`Page 14 of 20
`
`

`

`
`US. Patent
`
`
`
`Apr. 17, 2001
`
`
`
`
`Sheet 14 0f 14
`
`
`
`
`
`
`
`
`US 6,218,266 B1
`
`
`
`
`
`Fig.15
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`\LPOLISH END
`
`
`
`
`
`
`RESISTANCE(R)
`
`
`
`
`
`
`CF:
`
`THICKNESSH)
`
`
`
`Page 15 0f 20
`
`Page 15 of 20
`
`

`

`
`
`US 6,218,266 B1
`
`
`
`
`1
`METHOD OF FABRICATING ELECTRONIC
`
`
`
`DEVICES OF THE TYPE INCLUDING
`
`
`
`
`
`SMOOTHING PROCESS USING POLISHING
`
`
`
`BACKGROUND OF THE INVENTION
`
`
`
`1. Field of the Invention
`
`
`
`
`
`The present invention relates to a method of fabricating
`
`
`
`
`
`
`
`
`electronic devices of the type including a smoothing process
`
`
`
`
`
`
`
`using polishing. This invention is applicable to the produc-
`
`
`
`
`
`
`
`
`tion of various electronic materials in which A smoothing
`
`
`
`
`
`
`
`
`
`process is needed. For example, the invention is applicable
`
`
`
`
`
`
`
`
`
`to a process of fabricating semiconductor devices in which
`
`
`
`
`
`
`
`
`
`grooves or trenches formed in the surface of a substrate are
`
`
`
`
`
`
`
`
`
`
`filled up for planarization, and also to the manufacture of
`
`
`
`
`
`
`
`
`
`
`varies electronic devices such as magnetic disks in which
`
`
`
`
`
`
`
`
`
`smoothing is required.
`
`
`
`2. Description of the Prior Art
`
`
`
`
`
`
`In the production of electronic devices, smoothing must
`
`
`
`
`
`
`
`
`be achieved in various cases. For example, when grooves or
`
`
`
`
`
`
`
`
`
`
`trenches formed in the surface of a substrate are filled up
`
`
`
`
`
`
`
`
`
`
`
`with a filling material, the surface must be smoothed. In
`
`
`
`
`
`
`
`
`
`
`addition, the smoothing processes become necessary when a
`
`
`
`
`
`
`
`trench isolation, a trench capacitor or a metal wiring portion
`
`
`
`
`
`
`
`
`such as a connector plug is formed, and also when grooves
`
`
`
`
`
`
`
`
`
`
`
`or spaces are filled up to form a necessary part.
`
`
`
`
`
`
`
`
`
`
`To accomplish the smoothing, various techniques using
`
`
`
`
`
`
`
`polishing have been considered. The term “polishing” used
`
`
`
`
`
`
`
`
`herein in a comprehensive sense, i.e., to broadly refer to any
`
`
`
`
`
`
`
`
`
`
`
`type of polishing process or system which is capable of
`
`
`
`
`
`
`
`
`
`
`accomplishing the smoothing process. Since the polishing is
`
`
`
`
`
`
`
`
`a mechanical means for smoothing an object, it is broadly
`
`
`
`
`
`
`
`
`
`
`applicable to various objects without substantial restriction
`
`
`
`
`
`
`
`and capable of exhibiting good smoothing accuracy. The
`
`
`
`
`
`
`
`
`polishing is,
`therefore, attractive and promising. One
`
`
`
`
`
`
`
`example of such smoothing processes using polishing is
`
`
`
`
`
`
`
`
`reported in The Nikkei Sangyo published Oct. 2, 1990, in
`
`
`
`
`
`
`
`
`
`
`which spherical nylon tools of 10 mm in diameter are used
`
`
`
`
`
`
`
`
`
`
`
`to polish away fine projections on a magnetic disk substrate
`
`
`
`
`
`
`
`
`
`with smoothing accuracy which is about 2.5 times as high as
`
`
`
`
`
`
`
`
`
`
`
`before.
`
`However, when the polishing is employed to smoothing
`
`
`
`
`
`
`
`
`various electronic devices, we encounter various problems
`
`
`
`
`
`
`
`to be solved. A first problem is encountered when the
`
`
`
`
`
`
`
`
`
`
`polishing is effected after grooves or trenches in a substrate
`
`
`
`
`
`
`
`
`
`
`are filled up by means of a deposition process (such as the
`
`
`
`
`
`
`
`
`
`
`
`bias ECR-CVD, in particular) in which etching and depo-
`
`
`
`
`
`
`
`
`sition are achieved concurrently. In this instance, however,
`
`
`
`
`
`
`
`due to irregularity in height of the portions to be polished,
`
`
`
`
`
`
`
`
`
`
`the polishing can only be performed with insufficient accu-
`
`
`
`
`
`
`
`
`racy. A second problem is the difficulty in determining a
`
`
`
`
`
`
`
`
`
`polish end.
`
`
`The first problem will be discussed below in greater
`
`
`
`
`
`
`
`
`detail. The bias ECR-CVD or the like process which is
`
`
`
`
`
`
`
`
`
`capable of performing etching and deposition concurrently
`
`
`
`
`
`
`is an attractive technique. This is because such a deposition
`
`
`
`
`
`
`
`
`
`technique will promote micro-miniaturization of trench por-
`
`
`
`
`
`
`tions in conformity with an advance of the micro-
`
`
`
`
`
`
`
`
`miniaturization and integration of semiconductor devices,
`
`
`
`
`
`
`and also meet a demand for higher smoothing accuracies. As
`
`
`
`
`
`
`
`
`
`the miniaturizing and integration densities of semiconductor
`
`
`
`
`
`
`
`integrated circuits increase,
`the conventional selectively
`
`
`
`
`
`
`oxidized film (LOCOS) method used for isolating circuit
`
`
`
`
`
`
`
`
`elements has been replaced by the shallow trench method. In
`
`
`
`
`
`
`
`
`
`
`it
`the shallow trench method,
`is extremely effective if
`
`
`
`
`
`
`
`
`
`grooves or trenches are filled up by the bias ECR-CVD. The
`
`
`
`
`
`
`
`
`
`
`
`bias ECR-CVD accomplishes deposition and etching con-
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Page 16 0f 20
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`2
`currently and, hence, is able to fill up wide and narrow
`
`
`
`
`
`
`
`
`
`
`
`trenches (grooves) with a filling material (an insulating
`
`
`
`
`
`
`
`
`material such as SiOz) of a same thickness, thus exhibiting
`
`
`
`
`
`
`
`
`
`a perfect shallow trenching. In addition, by controlling the
`
`
`
`
`
`
`
`
`
`ratio of the etching rate to the deposition rate, it is possible
`
`
`
`
`
`
`
`
`
`
`
`
`to fill up those trenches having a relatively large aspect ratio
`
`
`
`
`
`
`
`
`
`
`not less than 1.79, for example. With this control of the ratio
`
`
`
`
`
`
`
`
`
`
`
`
`of etching rate and deposition rate, lateral leveling can be
`
`
`
`
`
`
`
`
`
`
`used. The lateral leveling is a technique to perform deposi-
`
`
`
`
`
`
`
`
`
`tion under the conditions that the etching proceeds in the
`
`
`
`
`
`
`
`
`
`lateral direction (parallel to the surface of a substrate), while
`
`
`
`
`
`
`
`
`in the vertical direction, neither etching nor deposition
`
`
`
`
`
`
`
`proceeds. Thus, etching is achieved selectively in the lateral
`
`
`
`
`
`
`
`
`direction. With this lateral leveling, it is possible to remove
`
`
`
`
`
`
`
`
`
`excess materials deposited on portions of the substrate other
`
`
`
`
`
`
`
`
`than those corresponding to trenches, thereby providing a
`
`
`
`
`
`
`
`margin or space necessary for a resist film registration or
`
`
`
`
`
`
`
`
`
`alignment.
`
`The bias ECR-CVD method or the like deposition method
`
`
`
`
`
`
`
`
`described above is, however, still not fully satisfactory
`
`
`
`
`
`
`
`because of the drawbacks discussed below.
`
`
`
`
`
`
`Since etching and deposition are achieved concurrently,
`
`
`
`
`
`
`the etching rate necessarily becomes small as a whole.
`
`
`
`
`
`
`
`
`Consequently, the throughput and productivity are relatively
`
`
`
`
`
`
`low. In addition, if the lateral leveling process is performed
`
`
`
`
`
`
`
`
`
`to provide a margin for resist registration, the throughput is
`
`
`
`
`
`
`
`
`
`reduced additional due to a small etching rate in the lateral
`
`
`
`
`
`
`
`
`
`
`direction.
`
`With the foregoing drawbacks in view, an attempt has
`
`
`
`
`
`
`
`
`
`been made to remove an excess filling material (SiOz, for
`
`
`
`
`
`
`
`
`
`
`example) by polishing, but various problems have encoun-
`
`
`
`
`
`
`
`tered in adopting the polishing process, as described below.
`
`
`
`
`
`
`
`
`
`The deposition using the bias ECR-CVD method depends
`
`
`
`
`
`
`
`
`on the substrate. Accordingly, if the conventional bias ECR-
`
`
`
`
`
`
`
`
`
`CVD method is applied to fill up grooves (trenches) 21—23
`
`
`
`
`
`
`
`
`
`in a surface of a substrate 1, as shown in FIG. 2B, a portion
`
`
`
`
`
`
`
`
`
`
`
`
`
`31 of the filling material (SiOz) deposited on a wide land A
`
`
`
`
`
`
`
`
`
`
`
`is different in height from a portion 32 of the filling material
`
`
`
`
`
`
`
`
`
`
`
`
`deposited on a narrow land B. With this difference in height,
`
`
`
`
`
`
`
`
`
`
`these portions 31, 32 are subjected to polishing at different
`
`
`
`
`
`
`
`
`
`
`points of time. In addition, if the polishing has an angle
`
`
`
`
`
`
`
`
`
`
`
`dependency,
`the irregularity in deposition height
`largely
`
`
`
`
`
`
`
`affects the precision of polishing operation. Furthermore, in
`
`
`
`
`
`
`
`
`the bias ECR plasma CVD, in particular, due to a divergent
`
`
`
`
`
`
`
`
`
`
`
`magnetic field used in this process, the thickness of a filling
`
`
`
`
`
`
`
`
`
`
`material (SiOz, for example) becomes greater in a central
`
`
`
`
`
`
`
`
`
`portion of the substrate than in a peripheral portion of the
`
`
`
`
`
`
`
`
`
`
`
`substrate. The thickness irregularity thus produced will
`
`
`
`
`
`
`
`deteriorate the quality of the subsequent polishing operation.
`
`
`
`
`
`
`
`
`A great interest has been shown toward application of the
`
`
`
`
`
`
`
`
`
`
`polishing techniques to silicon on insulator (SOI)
`
`
`
`
`
`
`
`technology, but any satisfactory solution has not been pro-
`
`
`
`
`
`
`
`
`vided heretofore due to the difficulty in determining a polish
`
`
`
`
`
`
`
`
`end.
`
`
`
`
`SUMMARY OF THE INVENTION
`
`
`
`
`With the foregoing drawbacks of the prior art in view, an
`
`
`
`
`
`
`
`
`
`
`
`object of the present invention is to provide a method of
`
`
`
`
`
`
`
`
`
`
`
`fabricating electronic devices, which is able to eliminate
`
`
`
`
`
`
`
`
`negative influences resulting from irregular deposition of
`
`
`
`
`
`
`
`material on a substrate, thereby insuring a high precision
`
`
`
`
`
`
`
`
`
`polishing of the deposited material.
`
`
`
`
`
`Another object of this invention is to provide an electronic
`
`
`
`
`
`
`
`
`
`device fabrication method which is capable of determining
`
`
`
`
`
`
`
`a polish end reliably with utmost ease.
`
`
`
`
`
`
`
`In one aspect the present invention provides a method of
`
`
`
`
`
`
`
`
`
`
`fabricating an electronic device, of the type wherein grooves
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`25
`
`
`30
`
`
`
`35
`
`
`
`40
`
`
`
`45
`
`
`50
`
`
`
`55
`
`
`
`60
`
`
`
`65
`
`
`Page 16 of 20
`
`

`

`
`
`US 6,218,266 B1
`
`
`
`
`
`
`
`
`
`
`
`3
`formed in a substrate are filled up with a filling material
`
`
`
`
`
`
`
`
`
`
`
`deposited by a deposition process in which etching and
`
`
`
`
`
`
`
`
`
`deposition are achieved concurrently, wherein the improve-
`
`
`
`
`
`
`ment comprises: leveling up the height of portions of the
`
`
`
`
`
`
`
`
`
`filling material deposited on these portions of the substrate
`
`
`
`
`
`
`
`
`other than those corresponding to the grooves; and
`
`
`
`
`
`
`
`thereafter, polishing away said portions of the filling mate-
`
`
`
`
`
`
`
`
`rial to smoothen the substrate.
`
`
`
`
`
`The leveling may be achieved by an additional deposition
`
`
`
`
`
`
`
`
`of the filling material, or alternatively by a full surface etch
`
`
`
`
`
`
`
`
`
`back process.
`
`
`In another aspect this invention provides a method of
`
`
`
`
`
`
`
`
`
`fabricating an electronic device, of the type wherein grooves
`
`
`
`
`
`
`
`
`
`formed in a substrate are filled up with a filling material
`
`
`
`
`
`
`
`
`
`
`
`deposited by a deposition process in which etching and
`
`
`
`
`
`
`
`
`
`deposition are achieved concurrently, wherein the improve-
`
`
`
`
`
`
`ment comprises: effecting said deposition process under
`
`
`
`
`
`
`
`such conditions that
`the difference in thickness of the
`
`
`
`
`
`
`
`
`
`deposited filling material between a central portion and a
`
`
`
`
`
`
`
`
`
`peripheral portion of the substrate is canceled out; and
`
`
`
`
`
`
`
`
`
`thereafter, polishing the substrate to smooth the same.
`
`
`
`
`
`
`
`
`In a further aspect the invention provides a method of
`
`
`
`
`
`
`
`
`
`
`fabricating an electronic device, of the type wherein grooves
`
`
`
`
`
`
`
`
`
`formed in a substrate are filled up with a filling material
`
`
`
`
`
`
`
`
`
`
`
`deposited by a deposition process in which etching and
`
`
`
`
`
`
`
`
`
`deposition are achieved concurrently, wherein the improve-
`
`
`
`
`
`
`ment comprises: after said deposition process, effecting an
`
`
`
`
`
`
`
`
`additional deposition process under such conditions that the
`
`
`
`
`
`
`
`
`ratio of deposition rate to etching rate is greater at a
`
`
`
`
`
`
`
`
`
`
`
`peripheral portion than at a central portion of the substrate,
`
`
`
`
`
`
`
`
`
`
`thereby reshaping the filling material deposited on the
`
`
`
`
`
`
`
`
`substrate by the first deposition process; and thereafter,
`
`
`
`
`
`
`
`
`polishing the substrate to smooth the same.
`
`
`
`
`
`
`
`In still another aspect the invention provides a method of
`
`
`
`
`
`
`
`
`
`
`fabricating an electronic device, of the type including a
`
`
`
`
`
`
`
`
`
`smoothing process achieved by polishing with a polishing
`
`
`
`
`
`
`
`
`member, wherein improvement comprises: forming a con-
`
`
`
`
`
`
`ductive polish-stop layer over a substrate; effecting said
`
`
`
`
`
`
`
`smoothing process; and during said smoothing process,
`
`
`
`
`
`
`monitoring the electric resistance between the substrate and
`
`
`
`
`
`
`
`a surface of the polishing member contacting the substrate,
`
`
`
`
`
`
`
`
`thereby determining a polish end according to changes in
`
`
`
`
`
`
`
`
`electric resistance.
`
`
`The above and other objects, features and advantages of
`
`
`
`
`
`
`
`
`
`the present invention will become more apparent from the
`
`
`
`
`
`
`
`
`
`following description taken in conjunction with the accom-
`
`
`
`
`
`
`
`panying drawings.
`
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`
`
`
`
`FIGS. 1A through ID are cross-sectional views showing
`
`
`
`
`
`
`
`sequential steps of fabricating an electronic device accord-
`
`
`
`
`
`
`
`ing to a first embodiment of this invention;
`
`
`
`
`
`
`
`
`FIGS. 2A and 2B are cross-sectional views showing an
`
`
`
`
`
`
`
`
`advantage of the present invention over the prior art;
`
`
`
`
`
`
`
`
`
`FIGS. 3A through 3D are cross-sectional views showing
`
`
`
`
`
`
`
`sequential steps of fabricating an electronic device accord-
`
`
`
`
`
`
`
`ing to a second embodiment of this invention;
`
`
`
`
`
`
`
`
`FIGS. 4A and 4B are cross-sectional views showing a
`
`
`
`
`
`
`
`
`
`central portion and a peripheral portion, respectively, of a
`
`
`
`
`
`
`
`
`
`wafer processed in accordance with a third embodiment of
`
`
`
`
`
`
`
`
`
`this invention;
`
`
`FIG. 5 is a cross-sectional view in the direction perpen-
`
`
`
`
`
`
`
`
`
`dicular to the sectional plane of FIGS. 4A and 4B;
`
`
`
`
`
`
`
`
`
`
`FIG. 6 is a graph showing the principle of operation of the
`
`
`
`
`
`
`
`
`
`
`
`third embodiment in conjunction with the relation between
`
`
`
`
`
`
`
`
`the deposition rate and the SiH4/NZO ratio;
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`25
`
`
`30
`
`
`
`35
`
`
`
`40
`
`
`
`45
`
`
`50
`
`
`
`55
`
`
`
`60
`
`
`
`65
`
`
`Page 17 0f 20
`
`4
`
`FIGS. 7A and 7B are cross-sectional views similar to
`
`
`
`
`
`
`
`
`
`FIGS. 4A and 4B, but showing the condition after lateral
`
`
`
`
`
`
`
`
`
`
`leveling process is performed;
`
`
`
`
`FIG. 8 is a cross-sectional view showing the thickness
`
`
`
`
`
`
`
`
`uniformity of the wafer obtained after the lateral leveling
`
`
`
`
`
`
`
`
`process;
`
`FIGS. 9A and 9B are cross-sectional views showing a
`
`
`
`
`
`
`
`
`
`central portion and a peripheral portion, respectively, of an
`
`
`
`
`
`
`
`
`
`electronic device as they are subjected to a first processing
`
`
`
`
`
`
`
`
`
`
`step of a semiconductor fabrication method according to a
`
`
`
`
`
`
`
`
`fourth embodiment of this invention;
`
`
`
`
`
`FIGS. 10A and 10B, 11A and 11B, and 12A and 12B are
`
`
`
`
`
`
`
`
`
`
`
`
`cross-sectional views similar to FIGS. 9A and 9B, but
`
`
`
`
`
`
`
`
`
`showing second,
`third and fourth succeeding processing
`
`
`
`
`
`
`
`steps of the fourth embodiment;
`
`
`
`
`
`FIG. 13 is a cross-sectional view showing a first step in a
`
`
`
`
`
`
`
`
`
`
`fifth embodiment of this invention;
`
`
`
`
`
`FIG. 14 is a cross-sectional view similar to FIG. 13, but
`
`
`
`
`
`
`
`
`
`
`showing a second step of the fifth embodiment;
`
`
`
`
`
`
`
`
`FIG. 15 is a fragmentary cross-sectional view, with parts
`
`
`
`
`
`
`
`
`shown in circuit diagram, of a third step of the fifth embodi-
`
`
`
`
`
`
`
`
`
`
`ment; and
`
`
`FIG. 16 is a graph illustrative of the principle of operation
`
`
`
`
`
`
`
`
`
`of the fifth embodiment.
`
`
`
`
`DETAILED DESCRIPTION OF THE
`
`
`
`INVENTION
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The invention will be described in greater detail with
`
`
`
`
`
`
`
`
`reference to certain preferred embodiments shown in the
`
`
`
`
`
`
`
`accompanying drawings.
`
`
`FIGS. 1A through 1D show a first embodiment of the
`
`
`
`
`
`
`
`
`
`
`invention which is applied in a shallow trench
`present
`
`
`
`
`
`
`
`
`
`isolation used for isolating component elements of a semi-
`
`
`
`
`
`
`
`conductor integrated circuit.
`
`
`
`In this embodiment, a silicon semiconductor substrate 1
`
`
`
`
`
`
`
`
`shown in FIG. 1A is used. The substrate 1 has grooves or
`
`
`
`
`
`
`
`
`
`
`
`
`trenches 21—23 formed in its surface. The trenches 21—23 are
`
`
`
`
`
`
`
`
`
`
`filled up with a filling material 3 by a deposition process in
`
`
`
`
`
`
`
`
`
`
`
`
`which etching and deposition are achieved concurrently. In
`
`
`
`
`
`
`
`
`this instance, portions 31a, 31b, 32, 33 (FIG. 1B) of the
`
`
`
`
`
`
`
`
`
`
`
`filling material 3 which are deposited on portions of the
`
`
`
`
`
`
`
`
`
`
`surface of the substrate 1 other than those corresponding to
`
`
`
`
`
`
`
`
`
`
`the trenches 21—23 are leveled up until they have substan-
`
`
`
`
`
`
`
`
`
`tially a same height, as shown in FIG. 1C, generally indi-
`
`
`
`
`
`
`
`
`
`
`cated by reference characters 31a', 31b', 32', 33', respec-
`
`
`
`
`
`
`
`
`tively. Subsequently, a smoothing process depending on the
`
`
`
`
`
`
`
`
`polishing operation is effected to obtain a planar structure
`
`
`
`
`
`
`
`
`
`shown in FIG. 1D.
`
`
`
`
`The leveling process in this embodiment is achieved by an
`
`
`
`
`
`
`
`
`
`
`additional deposition of filling material 3 (SiOz,
`in this
`
`
`
`
`
`
`
`
`
`embodiment). As described later in greater detail, the filling
`
`
`
`
`
`
`
`
`
`material SiO2 3 is deposited additionally during which time
`
`
`
`
`
`
`
`
`
`a lowest deposited portion 32 is etched into a substantially
`
`
`
`
`
`
`
`
`
`
`flat shape by the lateral leveling etching. Thus, the structure
`
`
`
`
`
`
`
`
`
`
`shown in FIG. 1C is obtained.
`
`
`
`
`
`
`Stated more specifically, a laminated structure composed
`
`
`
`
`
`
`
`of a polish-stop layer 41 of Silicon Nitride (Si3N4) and an
`
`
`
`
`
`
`
`
`
`
`etch-stop layer 42 of SiO2 for stopping etching action on the
`
`
`
`
`
`
`
`
`
`
`
`Si3N4 polish-stop layer 41 is formed over the surface of a
`
`
`
`
`
`
`
`
`
`
`silicon substrate 1. Then, a trench pattern for isolating
`
`
`
`
`
`
`
`
`
`elements is prepared by photolithography and silicon trench
`
`
`
`
`
`
`
`
`etching, so that shallow grooves or trenches 21—23 are
`
`
`
`
`
`
`
`
`
`formed in the silicon substrate 1, as shown in FIG. 1A. The
`
`
`
`
`
`
`
`
`
`
`
`
`
`thickness of the Si3N4 polish-stop layer 41 is 500 A, for
`
`
`
`
`
`
`
`
`
`
`example, and the thickness of the SiO2 etch-stop layer 42 is
`
`
`
`
`
`
`
`
`
`
`
`
`Page 17 of 20
`
`

`

`
`
`US 6,218,266 B1
`
`
`
`5
`
`
`
`100 A, for example. The aspect ratio of the narrow trenches
`
`
`
`
`
`
`
`
`
`22, 23 is greater than 1.79. The invention is suitably appli-
`
`
`
`
`
`
`
`
`
`
`cable to the trenches of this nature.
`
`
`
`
`
`
`
`Then, the trenches 21—23 are filled up by the bias ECR-
`
`
`
`
`
`
`
`
`
`
`CVD. In practice, inside walls of the trenches 21—23 are
`
`
`
`
`
`
`
`
`
`
`oxidized prior to the bias ECR-CVD process. Conditions for
`
`
`
`
`
`
`
`
`
`the bias ECR-CVD are as follows.
`
`
`
`
`
`
`Etching gas: SiH4/N20=20/35 SCCM
`
`
`
`
`
`
`
`
`
`
`Gas pressure: 7><10'4 Torr (0.093 Pa)
`Microwave: 1000 W
`
`
`
`RF bias: 500 W
`
`
`
`
`With this bias ECR-CVD process, the trenches 21—23 are
`
`
`
`
`
`
`
`
`
`filled up with a filling material 3, as shown in FIG. 1B. A
`
`
`
`
`
`
`
`
`
`
`
`
`
`portion 32 of the filling material deposited on a narrow land
`
`
`
`
`
`
`
`
`
`
`extending between the narrow trenches 22 and 23 is smaller
`
`
`
`
`
`
`
`
`
`
`in height than portions 31a, 31b, 32, 33 of the filling material
`
`
`
`
`
`
`
`
`
`
`
`
`3 deposited on wide lands. The height of the portion 22 of
`
`
`
`
`
`
`
`
`
`
`
`
`the filling material which is deposited on the wide land
`
`
`
`
`
`
`
`
`
`
`extending between the narrow trench 22 and the wide trench
`
`
`
`
`
`
`
`
`
`
`21 is the substantially the same as, or slightly smaller than,
`
`
`
`
`
`
`
`
`
`
`
`the height of the adjacent portions 31a, 31b of the deposited
`
`
`
`
`
`
`
`
`
`
`
`filling material.
`
`
`According to the conventional technology, a smoothing
`
`
`
`
`
`
`
`process is then started, with the trenches 21—23 filled up with
`
`
`
`
`
`
`
`
`
`
`
`the filling material 3 such as shown in FIG. 1B. However, in
`
`
`
`
`
`
`
`
`
`
`
`the embodiment of this invention, the bias ECR-CVD still
`
`
`
`
`
`
`
`
`
`continues so that an additional deposit of filling material
`
`
`
`
`
`
`
`
`
`(SiOz) 3 is formed. With this additional depositing, a lowest
`
`
`
`
`
`
`
`
`
`
`one 33 of the deposited SiO2 portions 31a, 31b, 33 to be
`
`
`
`
`
`
`
`
`
`
`
`
`removed is leveled up until it has the same height as the
`
`
`
`
`
`
`
`
`
`
`
`
`other SiO2 portions 31a, 31b, on the wide lands. Astructure
`
`
`
`
`
`
`
`
`
`
`
`thus obtained is shown in FIG. 1C. As is apparent from FIG.
`
`
`
`
`
`
`
`
`
`
`
`
`1C, all the deposited SiO2 portions 31a', 31b', and 33' have
`
`
`
`
`
`
`
`
`
`
`
`the same height.
`
`
`
`Thereafter, an excessive SiO2 is removed by polishing,
`
`
`
`
`
`
`
`
`whereby a smoothed structure such as shown in FIG. 1D is
`
`
`
`
`
`
`
`
`
`
`
`obtained. The polishing process used here may be of the
`
`
`
`
`
`
`
`
`
`
`conventional
`type or of the type using the nylon balls
`
`
`
`
`
`
`
`
`
`
`described above. For the polishing process, the structure
`
`
`
`
`
`
`
`
`preferably has patterns of the same width which are formed
`
`
`
`
`
`
`
`
`
`
`by using a stencil structure as described in Japanese Patent
`
`
`
`
`
`
`
`
`
`
`
`Application No. 3-24041 filed by to the present assignee.
`
`
`
`
`
`
`
`
`
`Subsequently, the Si3N4 polish-stop layer 41 is etched off
`
`
`
`
`
`
`
`
`as required. In this instance, due to the presence of the SiO2
`
`
`
`
`
`
`
`
`
`
`
`
`etch-stop layer 42, the base silicon substrate 1 is not affected
`
`
`
`
`
`
`
`
`
`
`
`at all by the etching process. With this etching, the SiO2
`
`
`
`
`
`
`
`
`
`
`
`slightly projects from the trenches 21—23, so that the dielec-
`
`
`
`
`
`
`
`
`
`tric breakdown strength of the structure is improved.
`
`
`
`
`
`
`
`
`As described above, the trenches 21—23 are filled up by
`
`
`
`
`
`
`
`
`
`the bias ECR-CVD which accomplishes etching and depo-
`
`
`
`
`
`
`
`sition concurrently, and then an excessive filling material
`
`
`
`
`
`
`
`
`(SiOz) deposited on portions of the substrate 1 other than
`
`
`
`
`
`
`
`
`
`
`those corresponding to the trenches 21—23 is smoothed by
`
`
`
`
`
`
`
`
`
`polishing. According to the first embodiment of this
`
`
`
`
`
`
`
`
`invention, before the polishing is effected,
`the excessive
`
`
`
`
`
`
`
`
`SiO2 is leveled up to the same height. Accordingly, as
`
`
`
`
`
`
`
`
`
`
`against the prior art such as shown in FIG. 2B, the deposited
`
`
`
`
`
`
`
`
`
`
`
`
`SiO2 portions in the first embodiment are uniform in height,
`
`
`
`
`
`
`
`
`
`
`as shown in FIG. 2A. With this uniform height, the polishing
`
`
`
`
`
`
`
`
`
`
`
`accuracy is not affected by the pattern of deposited material,
`
`
`
`
`
`
`
`
`
`
`and the throughput can, therefore, be improved.
`
`
`
`
`
`
`
`A second embodiment of this invention will be described
`
`
`
`
`
`
`
`
`below with reference to FIGS. 3A through 3D.
`
`
`
`
`
`
`
`
`Likewise the first embodiment described above, a lami-
`
`
`
`
`
`
`
`nated structure composed of a polish-stop layer 41 of Si3N4
`
`
`
`
`
`
`
`
`
`and an etch-stop layer 42 of SiO2 is formed over the surface
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`25
`
`
`30
`
`
`
`35
`
`
`
`40
`
`
`
`45
`
`
`50
`
`
`
`55
`
`
`
`60
`
`
`
`65
`
`
`Page 18 0f 20
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`6
`of a silicon substrate 1. Then, a trench pattern for isolating
`
`
`
`
`
`
`
`
`
`elements is formed in the silicon substrate 1 by photolithog-
`
`
`
`
`
`
`
`
`
`raphy and silicon trench etching,
`thus forming shallow
`
`
`
`
`
`
`
`
`grooves or trenches 21—23 in the silicon substrate 1, as
`
`
`
`
`
`
`
`
`
`
`shown in FIG. 3A. The thickness of the Si3N4 polish-stop
`
`
`
`
`
`
`
`
`
`
`
`layer 41 is 1000 A (100 nm),
`for example. The SiO2
`
`
`
`
`
`
`
`
`
`
`etch-stop layer 42 has the same thickness as that in first
`
`
`
`
`
`
`
`
`
`
`
`embodiment described above.
`
`
`
`Then, the trenches 21—23 are filled up by the bias ECR-
`
`
`
`
`
`
`
`
`
`
`CVD. The bias ECR-CVD process is performed under the
`
`
`
`
`
`
`
`
`
`following conditions.
`
`
`Gas: SiH4/N20=7.5/35 SCCM
`
`
`
`
`
`
`
`
`Gas pressure: 7><10'4 Torr (0.093 Pa)
`Microwave: 1000 W
`
`
`
`RF bias: 500 W
`
`
`
`
`With this bias ECR-CVD process, the trenches 21—23 are
`
`
`
`
`
`
`
`
`filled up with a filling material 3, as shown in FIG. 3B.
`
`
`
`
`
`
`
`
`
`
`
`
`Subsequently, a full-surface etch back process is per-
`
`
`
`
`
`
`
`formed such that a deposited SiO2 portion 32 which is
`
`
`
`
`
`
`
`
`
`smaller in height than a wider deposited SiO2 portion 31 is
`
`
`
`
`
`
`
`
`
`
`completely removed. Conditions for the etch back process
`
`
`
`
`
`
`
`are as follows.
`
`
`
`Etching gas: CHF3/02=75/8 SCCM
`
`
`
`Gas pressure: 0.05 Torr (6.65 Pa)
`
`
`
`
`
`
`
`Applied electric power: 0.23 W/cm2
`
`
`
`
`With this etch back process, a structure shown in FIG. 3C
`
`
`
`
`
`
`
`
`
`
`is obtained. An SiO2 portion on the wide land formed after
`
`
`
`
`
`
`
`
`
`
`the etch back process is designated by 31'. It is preferable
`
`
`
`
`
`
`
`
`
`
`that
`the thickness of the Si3N4 polish-stop layer 41 is
`
`
`
`
`
`
`
`
`
`variable with the amount of etch back.
`
`
`
`
`
`
`
`Thereafter, polishing is eff