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`United States Patent
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`Konaka et a1.
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`[19]
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`[11] Patent Number:
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`[45] Date of Patent:
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`4,651,411
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`Mar. 24, 1987
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`FOREIGN PATENT DOCUMENTS
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`5/1983 Japan.
`58.73163
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`1/1984 Japan ........................... 29/576 W
`19348
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`181062 10/1984 Japan ..................................... 29/578
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`OTHER PUBLICATIONS
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`“A New Buried-Oxide Field Isolation for VLSI De-
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`vices”, K. Kurosawa et a1; Jun. 22—24, 1981, 39th An-
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`nual Device Research Conference, Santa Barbara, CA.
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`“A New Bird’s—Beak Free Field Isolation Technology
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`for VLSI Devices” Kurosawa et :11; Dec. 7-9, 1981,
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`IEDM Technical Digest, International Electron De-
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`vices Meeting, Washington, DC.
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`Primary Examiner—Brian E. Hearn
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`Assistant Examiner—John T. Callahan
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`Attorney, Agent, or Firm—Oblon, Fisher, Spivak,
`McClelland & Maier
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`ABSTRACT
`[57]
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`A method of manufacturing a MOS device wherein a
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`semiconductor substrate is selectively etched to form a
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`groove in a field region and an element formation re-
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`gion surrounded by the groove such that an angle 0 is
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`formed between a wall of the groove and a first imagi-
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`nary extension of a top surface of the element formation
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`region, the angle 9 satisfying the relation, 70°§0§90°.
`Then, a field insulating film is deposited in the groove,
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`and a MOS transistor is formed in the element forma-
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`tion region. The element formation region has source,
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`drain and channel regions of a field effect transistor
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`therein and a gate electrode formed on a gate insulating
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`film on the channel region. The gate electrode extends
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`onto the surface portion of the field insulating film. The
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`thickneSS of an upper portion of the
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`above a first imaginary extension of an interface be_
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`tween the gate insulating film and the gate electrode is
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`formed smaller than that of a lower portion of the field
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`Insulating film below the first magmary mamm-
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`6 Claims, 12 Drawing Figures
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`[54] METHOD OF MANUFACTURING A MOS
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`DEVICE WHEREIN AN INSULATING FILM
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`IS DEPOSITED IN A FIELD REGION
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`Masami Konaka, Kawasaki; Naoyuki
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`Inventors:
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`Shigyo; Ryo Dang, both of
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`Yokohama, all of Japan
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`Tokyo Shibaura Denki Kahushiki
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`Keisha, Kawasaki, Japan
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`[75]
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`[73] Assignee:
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`[21] Appl. No.: 744,899
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`[22] Filed:
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`Jun. 17, 1985
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`Related US. Application Data
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`Continuation of Ser. No. 435,663, Oct. 21, 1982.
`[63]
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`Foreign Application Priority Data
`[30]
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`Oct. 27, 1981 [JP].
`Japan ................................ 56-171784
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`Int. 01.4 ...................... H01L 21/76; H01L 29/78
`[51]
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`[52] US. Cl. ................................... 29/576 w; 29/571;
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`l48/DIG. 50
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`[58] Field of Search ............ .. 29/571, 576 w; 357/49,
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`357/50, 54, 23 cs; 156/643; 148/DIG. 50;
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`427/93
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`References Cited
`U.S. PATENT DOCUMENTS
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`8/1973 Richman ......................... 357/23 CS
`3,751,722
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`3,970,486 7/1976 Kooi .........
`......... 357/50
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`9/1976 Brand ...........
`357/23 CS
`3,979,765
`
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`.... ..
`4,001,465
`1/ 1977 Graul et al.
`. ........ 357/50
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`4,013,484 3/ 1977 Boleky et al.
`357/23 CS
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`5/1977 Richman .,,_..
`,,_., 357/50
`4,023,195
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`4,044,452
`8/1977 Abbos et a1.
`.. 357/23 CS
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`4,104,086
`8/1978 Bondur et 31.
`29/576 W
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`4,307,180 12/1981 Pogge ..............
`29/576 W
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`'‘
`‘‘''gig/3:,
`gall
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`4:407:85] 10/1983 K:::;wa'"""""""
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`4,462,847 7/1934 Thompson et a1.
`............. 29/576 w
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`3/1985 Godejahn, Jr.
`. .....
`.. .. ... .. 29/571
`4,506,437
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`4,541,167 9/ 1985 Havemann et a1.
`........... .. 29/576 W
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`[56]
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`Page 1 0”
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`TSMC Exhibit 1032
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`TSMC v. IP Bridge
`IPR2016-01246
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`TSMC Exhibit 1032
`TSMC v. IP Bridge
`IPR2016-01246
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`US. Patent Mar.24, 1987
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`Sheetl of5_
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`4,651,411
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`FIG.
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`(PRIOR ART)
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`FIG.
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`EFFECTIVE CHANNEL WIDTH
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`weff
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`LLJ
`21°
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`C> C
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`31—
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`O 3
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`5Lu
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`U. S. Patent Mar. 24, 1987
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`Sheet2 of5
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`4,651,411
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`FIG.
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`( PRIOR ART)
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`“\mm“
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`FIG.
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`4
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`EFFECTIVE CHANNEL WIDTH
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`Weff
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`THRESHOLDVOLTAGE T
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`US. Patent Mar. 24, 1987
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`Sheet3 of5
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`4,651,411
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`4,651,411
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`1
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`METHOD OF MANUFACTURING A MOS DEVICE
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`WHEREIN AN INSULATING FILM IS DEPOSITED
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`IN A FIELD REGION
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`This application is a continuation of application Ser.
`No. 435,663, filed Oct. 21, 1982.
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`BACKGROUND OF THE INVENTION
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`The present invention relates to a method of manu-
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`facturing a MOS device having a structure where an
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`insulating film is deposited in a field region.
`A semiconductor device such as a memory device
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`using a MOSFET shown in FIG. 1 is known which has
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`a coplanar (or LOCOS) structure to increase packing
`density and improve reliability. The semiconductor
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`device comprises a p-type silicon substrate 1, a field
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`oxide film 2 selectively formed in the field region, a gate
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`oxide film 3 formed on an element formation region
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`around the field oxide film 2, a gate electrode 4 formed
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`on the gate oxide film 3, and an ion-doped layer 5 which
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`functions as a channel stopper and which is formed in
`the silicon substrate 1 under the field oxide film 2. The
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`coplanar structure has advantages in that indentation of
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`the element surface is small since part of the field oxide
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`excellent step coverage is obtained in the aluminum
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`elements,
`wiring which connects
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`thereby providing a highly reliable semiconductor LSI.
`However, lateral extrusions B of this structure which
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`are called bird’s beaks are formed in an oxide film, as
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`shown in FIG. 1, adversely affecting microminiaturiza-
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`tion of the element.
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`The narrower the effective channel width Weff of the
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`MOSFET is, the greater the adverse effect. The actual
`thickness of the gate oxide film 3 becomes greater than
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`a desired thickness thereof, thus increasing variation in
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`the threshold voltage. In the worst case, the thickness of
`the gate oxide film becomes substantially the same as
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`that of the field oxide film. As a result, the source-drain
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`path is open. As shown in FIG. 2, the threshold voltage
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`VT of the MOSFET is increased when the effective
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`channel width Weff is decreased, thus resulting in the
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`so-called narrow channel effect.
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`FIG. 3 is a schematic sectional view of a MOSFET
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`having a BOX (Buried-Oxide Isolation) structure which
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`solves the problem of the bird’s beak encountered in the
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`coplanar structure. The MOSFET comprises a silicon
`substrate 1, a silicon oxide film 6 deposited by low-tem-
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`perature epitaxial growth in a groove with vertical
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`walls, a gate oxide film 3 formed on the element forma-
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`tion region surrounded by the silicon oxide film 6, a gate
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`electrode 4 formed on the gate oxide film 3, and an
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`ion-doped layer 5 which functions as a channel stopper
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`and which is formed in the silicon substrate beneath the
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`silicon oxide film 6. Since the silicon oxide film 6 is
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`formed in this MOSFET without involving high-tem-
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`perature thermal oxidation, the bird’s beaks are not
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`tage in that a MOSFET is formed which has a desired
`effective channel width. However, we found by experi-
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`ments that when the gate electrode 4 extends onto the
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`surface portion of the silicon oxide film 6, the threshold
`voltage VT of the MOSFET decreases with a decrease
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`in the effective channel width Weff, as shown in FIG. 4.
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`Generally, the electrical characteristics of the MOS-
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`FET must not depend on the effective channel width.
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`SUMMARY OF THE INVENTION
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`It is an object of the present invention to provide a
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`method of manufacturing a MOS device having an
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`insulator isolation structure wherein dependence of the
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`threshold voltage on the effective channel width is
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`slight, while a substrate surface is kept as smooth as
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`invention, there is provided a method of manufacturing
`a MOS device, comprising: selectively etching a semi-
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`conductor substrate to form a groove in a field region
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`and an element formation region surrounded by the
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`groove such that an angle 0 is formed between a wall of
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`the groove and a first imaginary extension of a top
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`surface of the element formation region, with the angle
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`9 satisfying the relation, 70‘é0é90‘. Then, a field
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`insulating film is deposited in the groove. The element
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`formation region has source, drain and channel regions '
`of a field effect transistor therein and a gate electrode
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`formed on a gate insulating film on the channel region.
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`The gate electrode extends onto the surface portion of
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`the field insulating film. The thickness of an upper por—
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`tion of the field insulating film above a first imaginary
`extension of an interface between the gate insulating
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`film and the gate electrode is smaller than that of a
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`lower portion of the field insulating film below the first
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`imaginary extension.
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`According to the above method, the threshold volt-
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`age drop which occurs due to the narrow channel effect
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`is prevented. Therefore, the threshold voltage of the
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`MOS device produced according to the present inven-
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`tion does not significantly depend on the effective chan-
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`nel width.
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`Furthermore, the method of the invention may in-
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`clude forming the insulating film may with a two-layer
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`structure. If the permittivity of the upper insulating film
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`portion is smaller than that of the lower insulating film
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`portion, the extent of projection of the insulating film
`can be decreased. As a result, excellent step coverage of
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`the wiring layer is provided, thus improving the reliabil-
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`When the insulating film is formed of silicon oxide, an
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`angle 0 formed by the wall of the groove and the imagi-
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`nary extension of the top surface of the element forma-
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`tion region may be determined to satisfy the relation
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`77° §0§90° to decrease the height of the projection of
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`the insulating film. When the insulating film is formed of
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`silicon nitride, the angle 0 may be determined to satisfy
`the relation 70“§0§90°.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`Other objects and advantages will be apparent from
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`the following description taken in conjunction with the
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`accompanying drawings, in which:
`FIG. 1 is a sectional view of a conventional MOS
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`device having a coplanar structure;
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`FIG. 2 is a graph showing the threshold voltage of
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`channel width thereof;
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`FIG. 3 is a sectional view of a conventional MOS
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`device having a BOX structure;
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`FIG. 4 is a graph showing the threshold voltage of
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`channel width thereof;
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`FIG. 5 is a sectional view of a MOS semiconductor
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`device according to a first embodiment of the present
`invention;
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`Page 7 of 9
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`4,651,411
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`3
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`FIG. 6 is a graph showing the variation in the thresh-
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`old voltage as a function of the thickness ratio tl/t2,
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`that is, as a function of an extent of projection of the
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`insulating film deposited in the groove formed in the
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`field region;
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`FIGS. 7A to 7D are sectional views for explaining
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`the steps of manufacturing a MOS device according to
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`the present invention;
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`FIG. 8 is a sectional view of a MOS device according
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`to a second embodiment of the present invention; and
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`FIG. 9 is a sectional view of a MOS device according
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`to a third embodiment of the present invention.
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`DETAILED DESCRIPTION OF THE
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`PREFERRED EMBODIMENTS
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`A MOS device according to a first embodiment of the
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`present invention will be described with reference to
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`FIG. 5. A groove 12 which has a substantially vertical
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`wall is formed around an element formation region 11 in
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`which source, drain and channel regions of the MOS-
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`FET are formed. An insulating film such as a silicon
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`oxide film 17 is deposited in the groove 12 by low-tem-
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`perature epitaxial growth. An ion-doped layer 15 as a
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`channel stopper is formed in the surface layer portion of
`the semiconductor substrate 10 beneath the silicon
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`oxide film 17. A gate oxide film 13 of SiOz is formed on
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`the surface of the element formation region 11. A
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`, *polysilicon gate electrode 14 is formed on the gate oxide
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`film 13. The gate electrode 14 extends onto the surface
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`' portion of the silicon oxide film 17. The silicon oxide
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`film 17 projects by a thickness t1 above an imaginary
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`extension of the interface between the gate oxide film 13
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`and the gate electrode 14. The silicon oxide film 17 is
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`embedded to a thickness t2 under the imaginary exten-
`Sion.
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`FIG. 6 is a graph for explaining the variation AVT in
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`the threshold voltage as a function of the ratio tl/t2.
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`The overall thickness (t1+t2) of the silicon oxide film
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`17 is kept constant. Note that the variation AVT in the
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`threshold voltage indicates a difference between the
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`threshold voltage of a transistor which has a sufficiently
`wide effective channel width Weff and the threshold
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`voltage of a transistor which has an effective channel
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`width Weff of 0.2 p. The above data is obtained by
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`computer simulation under the following conditions:
`the impurity concentration Nsub of the silicon substrate
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`10 is 2X 1015 cmj3; the thickness TOX of the gate oxide
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`film 13 is 1,000 A; the total thickness tl+t2 of the sili-
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`con oxide film 17 of the field region is 5,000 A; and the
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`relative permittivities es of the gate oxide film 13 and
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`the silicon oxide film 17 are both 3.9. If a tolerance for
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`the variation AVT in the threshold voltage is :20 mV
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`in the LSI design, the thickness ratio tl/t2 is preferably
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`in the range of 0.65ét1/t2< 1. Within this range, the
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`dependency of the threshold voltage of the MOSFET
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`on the effective channel width Weff is eliminated.
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`A method for manufacturing a MOS device accord-
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`ing to the present invention will be described with refer-
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`ence to FIGS. 7A to 7D. As shown in FIG. 7A, a silicon
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`substrate 10 is selectively etched to form a groove 12 in
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`the field region. The groove has a substantially vertical
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`wall. An impurity is ion-implanted in the bottom of the
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`groove 12 to form a channel stopper 15. A silicon oxide
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`film 17 is deposited by chemical vapor deposition in the
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`groove 12. The above steps are the same as those in the
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`conventional BOX structure method.
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`As shown in FIG. 7B, an element formation region 11
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`surrounded by the silicon oxide film 17 is selectively
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`lo
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`Page 8 of 9
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`4 .
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`etched so as to define the thickness of the upward pro-
`jection of the silicon oxide film 17 which must be
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`smaller than that of the embedded portion thereof. As
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`shown in FIG. 7C, a gate oxide film 13 is formed on the
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`element formation region 11. Furthermore, a polysili-
`con gate electrode 14 is formed on the gate oxide film 13
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`and on the silicon oxide film 17.
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`The structure of FIG. 78 can be provided without
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`etching the silicon substrate 10. This may be achieved
`by obtaining the structure of FIG. 7A without remov-
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`ing the etching mask (e.g. Al film, Si3N4 film, photore-
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`sist film, etc.) used in cutting the groove 12 and then by
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`removing the etching mask thereafter.
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`A MOS device according to a second embodiment of
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`the present invention will be described with reference
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`to FIG. 8. In this embodiment, an insulating film of
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`silicon nitride is deposited in the groove 12. An insulat-
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`ing films 17a and 17b having a two-layer structure are
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`formed in a groove 12 of a silicon substrate 10. The
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`MOS device of this embodiment is the same as that of
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`the first embodiment, except that an upper layer 17a is
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`formed of silicon oxide having a relative permittivity of
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`3.9, and that a lower layer 17b is formed of silicon ni-
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`tride having a relative permittivity of about 7. The
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`relative permittivity of the upper layer 17a is smaller
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`than that of the lower layer 17b. As a gate oxide film 13,
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`use is made of a 1,000 A thick silicon nitride film which
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`is formed by a direct nitrogenization. The same refer-
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`ence numerals used in FIG. 5 denote the same parts in
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`FIG. 8, and a detailed description thereof will be omit-
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`ted. In the above structure, the thickness ratio tl/t2 for
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`substantially eliminating the variation AVT in the
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`threshold voltage can be smaller than if in the first em-
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`bodiment the film 17 is formed of silicon nitride alone,
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`because the relative permittivity is smaller than in such
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`first embodiment. As a result, the thickness t1 can be
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`decreased, so that excellent step coverage of the wiring
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`layer can be provided and a highly reliable semiconduc-
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`tor device can be obtained. More specifically, the thick-
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`ness t1 can be reduced to half. The structure of FIG. 8
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`may be provided in the following steps.
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`First, a silicon nitride film is deposited in place of the
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`silicon oxide film 17 shown in FIG. 7A. The surface
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`portion of the silicon nitride film is then etched. 0n the
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`entire surface of the structure thus obtained there is
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`deposited a silicon oxide film. A photoresist film is
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`coated on the silicon oxide film. The photoresist film
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`has a flat surface. Both the photoresist film and the
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`silicon oxide film are etched at substantially the same
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`rate until the upper surface of the substrate is exposed.
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`The surface portion of the substrate is then etched. The
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`surface of the substrate is nitrided, thus forming a gate
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`insulating film 13. Alternatively, the surface of the sub-
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`strate may be oxidized, thus forming a gate insulating
`film 13 of silicon oxide.
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`A MOS device according to a third embodiment of
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`the present invention will be described with reference
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`to FIG. 9. The MOS device of this embodiment is the
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`same as that in FIG. 5, except that the wall of a groove
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`12 of a silicon substrate 10 is inclined to form an angle
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`0 smaller than 90° with respect to the imaginary exten-
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`sion of the top surface of an element formation region
`11. The same reference numerals used in FIG. 5 denote
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`the same parts in FIG. 9, and a detailed description
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`thereof is omitted. When the angle 0 is set to 80°, the
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`thickness ratio t1/t2 for substantially eliminating the
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`variation AVT in the threshold voltage can be smaller
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`than when the angle 0 is set to 90°. The thickness t1 of
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`5
`the insulating film portion which projects above the
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`imaginary extension of the interface between a gate
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`oxide film 13 and the gate electrode 14 can be decreased
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`as compared with that in the first embodiment. As a
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`result, excellent step coverage can be provided, and the
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`reliability of the semiconductor device is greatly im-
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`proved. In the third embodiment in which the film 17 is
`formed of silicon oxide, 3 maximum effect is obtained
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`when the angle 0 satisfies a relation 77°§0§90°. If the
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`insulating film 17 is formed of silicon nitride, a maxi-
`mum effect is obtained when the angle 0 satisfies a rela-
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`tion 70°§0§90°.
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`What we claim is:
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`l. A method of manufacturing a MOS device, com-
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`prising steps of: selectively etching a semiconductor
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`substrate to form a groove in a field region and an e1e~
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`ment formation region surrounded by said groove with
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`an angle formed between a wall of said groove and a
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`first imaginary extension of a top surface of said element
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`formation region, the angle satisfying a relation,
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`70'§0§90';
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`depositing a field insulating film in said groove by
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`chemical vapor deposition; and
`forming a gate electrode on a gate insulating film on
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`said substrate, said gate electrod extending onto the
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`surface portion of said field insulating film, a thick-
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`ness of an upper portion of said field insulating film
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`above a first imaginary extension of an interface
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`between said said gate insulating film and said gate
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`electrode having a predetermined value greater
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`than zero and being smaller than that of a lower
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`portion of said field insulating film below the first
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`Page 9 of 9
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`6
`imaginary extension; and wherein said semiconduc-
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`tor substrate is formed of silicon, said field insulat-
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`ing film is formed of silicon oxide, and a ratio of the
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`thickness of said upper portion of said field insulat-
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`ing film above the first imaginary extension to that
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`of said lower portion of said field insulating film
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`below the first imaginary extension is greater than
`0.65 and lower than 1.
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`2. The method according to claim 1, wherein said
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`field insulating film is formed of silicon oxide, and the
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`angle 9 satisfies the relation:
`77'_S_0§90'.
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`3. The method according to claim 1, wherein said
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`field insulating film is formed of silicon nitride.
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`4. The method according to claim 1, comprising:
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`forming a channel stopper in a surface layer of said
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`semiconductor substrate beneath of said field insu-
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`lating film.
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`5. The method according to claim 1, comprising:
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`forming said field insulating film with a two-layer
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`structure consisting of two insulating material lay-
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`ers having different relative permittivities, a per-
`mittivity of an upper insulating material
`layer
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`above the first imaginary extension being smaller
`than that of a lower insulating material layer below
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`the first imaginary extension.
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`6. The method according to claim 5, comprising:
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`forming said upper insulating material layer of silicon
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`oxide; and
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`forming said lower insulating material layer of silicon
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`nitride.
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`I!
`*
`t
`t
`ll
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`10
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`15
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`25
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`30
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`35‘
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`45
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`50
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`55
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`65
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`Page 9 of 9
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