Specification
`
`
`
`Title of the Invention: METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
`
`Claims:
`
`1. A method for a semiconductor device, comprising steps of:
`
` forming of trench separation regions comprising a flange part in a semiconductor substrate,
`respectively;
`
` forming a silicide layer on the surface of the semiconductor substrate; and
`
` forming of diffusion layers under the silicide layer.
`
`2. The method for a semiconductor device according to claim 1, wherein
`
` the diffusion layers are formed by solid-phase diffusion from the silicide layer.
`
`3. A method for a semiconductor device, comprising steps of:
`
` forming of separation regions on a semiconductor substrate by selective oxidation;
`
` forming a silicide layer on the surface of the semiconductor substrate; and
`
`Page 1 of 21
`
`TSMC Exhibit 1027
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

` forming of diffusion layers under the silicide layer by oblique ion implantation.
`
`4. A method for a semiconductor device, comprising steps of:
`
` forming of separation regions on a semiconductor substrate by selective oxidation;
`
` forming a silicide layer on the surface of the semiconductor substrate; and
`
` oblique ion implantation of impurities into the silicide layer, and forming of diffusion layers
`by solid-phase diffusion from the silicide layer.
`
`
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`[Industrial field of application]
`
` The present invention relates to a method for manufacturing a semiconductor device having
`diffusion layers under a silicide layer.
`
`
`
`[Summary of the Invention]
`
` The present invention is a method for manufacturing a semiconductor device having diffusion
`layers under a silicide layer so as to achieve reduction of a junction leakage current and
`improvement of junction withstand voltage, by having a step to form trench separation regions
`having a flange part on a semiconductor substrate, respectively; a step to form a silicide layer on
`the surface of the semiconductor substrate; and a step to form diffusion layers under a silicide
`layer.
`
` Further, in the manufacturing method of the present invention above, the reduction of a
`junction leakage current and the improvement of junction withstand voltage are achieved by
`forming the diffusion layers by solid-phase diffusion from the silicide layer.
`
` Further, the present invention is a method for a semiconductor device so as to achieve
`reduction of a junction leakage current and improvement of junction withstand voltage, by
`having a step to form separation regions on a semiconductor substrate by selective oxidation; a
`step to form a silicide layer on the surface of the semiconductor substrate; and a step to form
`diffusion layers under the silicide layer by oblique ion implantation.
`
` In addition, the present invention is a method for a semiconductor device, so as to achieve
`further reduction of a junction leakage current and further improvement of junction withstand
`voltage, by having a step to form separation regions on a semiconductor substrate by selective
`oxidation; a step to form a silicide layer on the surface of the semiconductor substrate; and a step
`to obliquely implant impurity ions into the silicide layer, and to form diffusion layers by solid-
`phase diffusion from the silicide layer.
`
`
`
`Page 2 of 21
`
`

`

`
`
`[Prior Art]
`
` Recently, in association with the increase of information, speed-up of IC, which is used for a
`computer element, is in demand to process a massive volume of data. As one method for this IC
`speed-up, a titanium salicide technology is attracting attention. For example, when an inverter
`CMOS ring oscillator is produced with a 0.5 µm rule, response speed without using any salicide
`is 90 psec, but it has already known that the speed will be increased to approximately 60 psec if
`titanium silicide is used.
`
` In the meantime, a necessity of a high-voltage transistor is increased in association with
`miniaturization and diversification of semiconductor elements, and high-pressure resistance of an
`MOS transistor is emphasized especially in a Bi-CMOS transistor. The titanium salicide
`technology is used for speed-up in this MOS transistor, as well.
`
` Fig. 14 shows one example of a conventional MOS transistor using titanium salicide. In this
`drawing, (1) represents a first conductive-shaped silicon substrate and (2) represents an element
`separation region by selective oxidation (LOCCS), and a gate electrode (4) with, for example,
`polycrystalline is formed on the surface of the substrate (1) via a gate insulating film (3), and,
`second conductive-shaped diffusion layers (5) and (6) to be a source and a drain across the gate
`electrode (4), respectively. A titanium silicide layer (i.e., titanium salicide) (7) is selectively
`formed on these diffusion layers (5) and (6), and a source electrode (9) and a drain electrode (9),
`for example, made of aluminum, are connected via contact holes of an interlayer insulating film
`(8), respectively.
`
` Such MOS transistor using titanium salicide is disclosed in Japanese Patent Application Laid-
`Open No. S63-84064, as well.
`
`
`
`[Problem to be Solved by the Invention]
`
` Now, in the MOS transistor described above, deterioration of voltage resistance and a leakage
`current at a junction part have become problems. As causes of the deterioration of voltage
`resistance and the leakage current at a junction part in the MOS transistor, ones due to an effect
`of ion implantation damage (crystal defect) (13) at the time of forming the source/drain diffusion
`layers (5) and (6) using an ion implantation method as shown in Fig. 15 and due to a silicon
`crystal defect (14) on the interface between the element separation region (2) and the silicon
`substrate (1) have been discovered. In addition, when a titanium silicide (TiSi2) layer (7) is
`selectively formed on the surfaces of the diffusion layers (5) and (6), if the conventional
`configuration is used, it has already been confirmed that a junction leakage current is increased
`due to diffusion of titanium along an end edge of the element separation region (2) as shown in
`Fig. 16, and the junction withstand voltage is deteriorated according to experiments.
`
`Page 3 of 21
`
`

`

` In light of the issues above, in a semiconductor device having diffusion layers under a silicide
`layer, the present invention is to provide a method for manufacturing a semiconductor device
`enabling reduction of the junction leakage current and improvement of the junction withstand
`voltage.
`
`[Means for Solving the Problem]
`
` The method for manufacturing a semiconductor device relating to the present invention
`includes a step to form trench separation regions (25) having a flange part (29a) (or (25a)) on a
`semiconductor substrate (21); a step to form a silicide layer (31) on a surface of the
`semiconductor substrate; and a step to form diffusion layers (32) and (33) under the silicide layer
`(31). Here, the order of the formation step of the silicide layer (31) and the formation step of the
`diffusion layers (32) and (33) is reversible. Further, for the formation of the diffusion layers (32)
`and (33), an ion implantation method, a solid-phase diffusion method and the like are usable.
`
` Further, the present invention is constituted so as to form the diffusion layers (32) and (33) by
`solid-phase diffusion from the silicide layer (31) in the manufacturing method above.
`
` Further, the method for manufacturing a semiconductor device relating to the present
`invention includes a step to form separation regions (51) on a semiconductor substrate (21) due
`to selective oxidation; a step to form a silicide layer (31) on a surface of the semiconductor
`substrate; and a step to form diffusion layers (32) and (33) under the silicide layer (31) by
`oblique ion implantation. Here, the order of the formation step of the silicide layer (31) and the
`formation step of the diffusion layers (32) and (33) is reversible.
`
` In addition, the method for manufacturing a semiconductor device relating to the present
`invention includes a step to form separation regions (51) on a semiconductor substrate (21) due
`to selective oxidation; a step to form a silicide layer (31) on a surface of the semiconductor
`substrate; and a step to obliquely implant impurities (38) into the silicide layer (31) and to form
`diffusion layers (32) and (33) by solid-phase diffusion.
`
`
`
`[Operation]
`
` According to the First Invention, since the trench separation regions (25) having a flange part
`(29a) (or (25a)) are formed on the semiconductor substrate (21) and the silicide layer (31) is
`formed on the surface of the semiconductor substrate, the formation of the silicide layer (31)
`along an interface between the trench separation regions (25) and semiconductor substrate (21) is
`prevented by the flange parts (29a) (or (25a)), and the joint leakage current is reduced and the
`joint withstand voltage is also improved [at the junction part].
`
` According to the Second Invention, since the diffusion layers (32) and (33) are formed by the
`solid-phase diffusion from the silicide layer (31) where impurities have been further induced in
`the First Invention, a crystal defect due to the ion implantation will not occur, and in addition, the
`junction leakage current is reduced and the junction withstand voltage is improved.
`
`Page 4 of 21
`
`

`

` According to the Third Invention, since the diffusion layers (32) and (33) are formed by
`oblique ion implantation into the semiconductor substrate (21) where the separation regions (51)
`are formed by selective oxidation, deep diffusion layers (32) and (33) are formed even at the end
`portion of the separation region (51), and the position of the junction part becomes deeper than
`the position diffused along the end portion of the separation region (51). Therefore, the titanium
`diffusion along the end portion of the separation region (51), i.e., the junction leakage current
`based on the silicide layer (31) is reduced, and the junction withstand voltage is also improved.
`
` According to the Fourth Invention, the silicide layer (31) is formed on the surface of the
`semiconductor substrate (21) where the separation regions (51) due to the selective oxidation
`have been formed, and impurities are obliquely implanted into the silicide layer (31) and the
`diffusion layers (32) and (33) are formed by the solid-phase diffusion from this silicide layer
`(31); thus, a junction part is formed at a position, which is deeper than the silicide layer (31),
`even under the end part of the separation region (51), and because of the phase-solid diffusion, a
`crystal defect like the one due to the ion implantation will never occur. Therefore, the junction
`leakage current is further reduced compared to the Third Invention, and, the junction withstand
`voltage is further improved.
`
`
`
`[Embodiment]
`
` Hereafter, embodiments of the method for manufacturing a semiconductor device according to
`the present invention are explained with reference to drawings. Furthermore, each embodiment
`indicates a case of applying [the present invention] to manufacturing of an MOS transistor.
`
` Fig. 1 shows the First Embodiment of the present invention. First, as shown in Fig. 1A,
`trenches (22) for inter-element separation are formed in a first principal surface of a first
`conductive-shaped (for example, p-shaped or n-shaped ) silicon substrate (21).
`
` Next, as shown in Fig. 1B, an SiO2 layer (23) is formed including the substrate surface so as
`to implant SiO2 into the trenches (22) using, for example, a bias EDR plasma CVD method or
`the like. After that, resist masks (24) are formed on the SiO2 layer (23) corresponding to the
`trenches (22), respectively. Then, the SiO2 layer (23) other than the trenches (22) is selectively
`removed by, for example, etching back, and the so-called trench separation regions (25) where
`an upper part is projected from the principal surface of the substrate (21), respectively, are
`formed as shown in Fig. 1C.
`
` Next, as shown in Fig. 1D, a gate electrode (28), for example, made from polycrystalline
`silicon, is formed on a predetermined area of an element formation region (26) separated by the
`trench separation regions (25) via a gate insulating film (27). Furthermore, the gate electrode
`(28) may be formed with tungsten silicide or others. Next, as shown in Fig. 1E, after a SiO2
`layer (29) is deposited and formed on a front surface, the SiO2 layer (29) is etched back by
`anisotropic etching, such as reactive ion etching (RIE), and SiO2 sidewall parts (29a) are formed
`on the sidewalls on upper-side protrusion parts of the trench separation regions (25). At this time,
`
`Page 5 of 21
`
`

`

`the SiO2 sidewall parts (29a) are simultaneously formed on the sidewall of the gate electrode
`(28), as well. In the trench separation regions (25), the trench separation regions (25) having the
`SiO2 sidewall parts, i.e., the flange parts (29a) are formed .
`
` Next, after a titanium (Ti) layer (30) is deposited and formed as shown in Fig. 1G, a titanium
`silicide (TiSi2) layer (31) is formed only on a silicon exposed portion using an RTA method
`(annealing at a high temperature in a short time) as shown in Fig. 1H, and an unreacted titanium
`layer (30) is removed by etching using, for example, ammonia hydrogen peroxide water or the
`like, and a so-called titanium salicide is formed. Furthermore, at this time, even though the
`titanium silicide layer (31) is formed on the gate electrode (28) made from polycrystalline silicon,
`as well; no silicide layer is formed when MSix is formed as the gate electrode (28).
`
` Next, as shown in Fig. 1I, second conductive-shaped impurities (if these are n-shaped , for
`example, they are arsenic (As), and if these are p-shaped , for example, they are boron (B)) (38)
`are induced by ion implantation or the like.
`
` Next, as shown in Fig. 1J, an interlayer insulating film (for example, SiO2) (34) is formed, and
`impurities in the titanium silicide layer (31) are solid-phase-diffused into the silicon substrate
`(21) by annealing at approximately 850 °C, and the diffusion layers (32) and (33) to be source
`and drain are formed, respectively.
`
` Subsequently, contact holes are formed in an interlayer insulating film (34), and electrodes
`(35) and (36), for example, made of aluminum, to be a source electrode and a drain electrode,
`which are connected to the titanium silicide layer (31) via these contact holes, respectively, are
`formed and a target MOS transistor (37) shown in Fig. 1K is obtained.
`
` According to the manufacturing method above, after the trench separation regions (25) having
`the SiO2 sidewall part (29a) at the upper side are formed, the titanium silicide layer (31) is
`formed, thus, the titanium silicide layer (31) is formed separately from the interface between the
`trench separation regions (25) and the silicon substrate (21) by the SiO2 sidewall parts (29a) of
`the trench separation regions [(25)]. Therefore, titanium will not be diffused along the interface
`with the silicon substrate (21) from the end edge of the separation regions (25), and the junction
`leakage current in the diffusion layers (32) and (33) can be reduced and the junction withstand
`voltage can be improved. Fig. 3 shows a characteristic diagram of reverse voltage — junction
`leakage current in the case of not forming a so-called flange part at the upper side of the
`conventional trench separation regions; and Fig. 4 shows a characteristic diagram of reverse
`voltage — junction leakage current in the case of not forming a so-called flange part at the upper
`side of the conventional trench separation regions according to the present invention. According
`to these characteristics diagrams in Figs. 3 and 4, the junction leakage current is lower and the
`junction withstand voltage is better in the MOS transistor relating to the present invention.
`Further, in the present embodiment, since impurities are induced into the titanium silicide (31)
`and the diffusion layers (32) and (33) are formed due to the solid-phase diffusion from this, no
`crystal defect will occur at the junction part; therefore, the junction leakage current can be further
`reduced and the junction withstand voltage can be further improved. Fig. 5 shows a
`
`Page 6 of 21
`
`

`

`characteristic diagram of reverse voltage — junction leakage current in the case of forming a
`source region and a drain region by conventional ion implantation; and Fig. 6 shows a
`characteristic diagram of reverse voltage — junction leakage current in the case of forming a
`source region and a drain region by the solid-phase diffusion relating to the present invention.
`According to these characteristic diagrams of Figs. 5 and 6, it is ascertained that the junction
`leakage current is much lower and the junction withstand voltage is much higher in the case of
`forming the diffusion layers by the solid-phase diffusion.
`
` Fig. 2 shows a second embodiment of the present invention. In the present embodiment, first,
`as shown in Fig. 2A, trenches (40) for interlayer separation are formed on one principal surface
`of the first conductive-shaped (for example, p-shaped or n-shaped ) silicon substrate (21).
`These trenches (40) are formed to have a T-shaped cross section formed with a deep trench part
`(40a) and a wide part (40b), which is wider than the width of the trench part (40a), at the upper
`end.
`
` Next, as shown in Fig. 2B, the SiO2 layer (23) is formed by including the substrate surface so
`as to implant SiO2 into the trenches (40) using, for example, the bias BCR plasma CVD method
`or the like.
`
` Next, as shown in Fig. 2C, after the entire SiO2 layer (23) is etched back so as to level (or
`substantially level) the SiO2 layer (23) in portions corresponding to the trenches (40) with the
`principal surface of the substrate (21), the resist masks (24) are selectively deposited and formed
`only on the SiO2 layer (23) of the trench (40).
`
` Next, the SiO2 layer (23) on the substrate surface other than the trenches (40) is removed via
`the resist masks (24), and then, the resist masks (24) are removed and the trench separation
`regions (25) having the flange part (25a) at the upper side are formed as shown in Fig. 2D.
`
` Next, as shown in Fig. 2E, the gate electrode (28), for example, made of polycrystalline silicon
`is formed on a predetermined area in the element formation region (26), which is separated by
`the trench separation regions (25), via the gate insulating film (27). Then, the SiO2 sidewall part
`(29a) is formed on the sidewall of the gate electrode (28) by deposition formation of SiO2 and
`anisotropic etching.
`
` Next, after the titanium (Ti) layer (30) is deposited and formed on the entire surface as shown
`in Fig. 2F, the titanium silicide (TiSi2) layers (31) are formed only on the silicon exposed
`portions by annealing at a high temperature in a short time as shown in Fig. 2G, and the
`unreacted titanium layer (30) is removed by etching with, for example, ammonia hydrogen
`peroxide water or the like, and a so-called titanium salicide is formed.
`
` Next, as shown in Fig. 2H, second conductive-shaped impurities (if these are n-shaped , for
`example, they are arsenic (As), and if these are p-shaped , for example, they are boron (B)) (38)
`are induced into the titanium silicide layer by ion implantation or the like. Next, as shown in Fig.
`2I, an interlayer insulating film (for example, SiO2) (34) is formed, and impurities in the
`
`Page 7 of 21
`
`

`

`titanium silicide layer (31) are solid-phase-diffused by annealing at approximately 850 °C to
`form the diffusion layers (32) and (33) to be source and drain, respectively.
`
` Subsequently, contact holes are formed in the interlayer insulating film (34), and for example,
`the electrode (35) and (36), which are made of aluminum, to be a source electrode and a drain
`electrode, which are connected to the titanium silicide layer (31) via these contact holes, are
`formed, and a target MOS transistor (41) shown in Fig. 2J is obtained.
`
` Even in such manufacturing method, after the trench separation regions (25) having the flange
`part (25a) are formed, the titanium silicide layer (31) is formed; thus, as similar to the
`embodiment in Fig. 1, the diffusion of titanium along the interface between the separation
`regions (25) and the silicon substrate (21) is prevented, and reduction of the junction leakage
`current and improvement of the junction withstand voltage at the diffusion layers (32) and (33)
`can be achieved. Further, since the diffusion layers (32) and (33) are formed due to solid-phase
`diffusion, as similar to the embodiment above, the junction leakage current can be further
`reduced, and the junction withstand voltage can be further improved.
`
` Furthermore, in the examples shown in Figs. 1 and 2, after the titanium silicide layer (31) is
`formed, the diffusion layers (32) and (33) are formed by the solid-phase diffusion from the
`titanium silicide layer (31), but it is also possible to form the titanium silicide layer (31) after the
`diffusion layers (32) and (33) are formed by ion implantation, and it is also possible to form the
`diffusion layers (32) and (33) by ion implantation after the titanium silicide layer (31) is formed.
`Even in such case, the junction leakage current and the junction withstand voltage can be
`improved by forming the flange part (25a) or (29a) at the upper sides of the trench separation
`regions (25), respectively.
`
` Fig. 7 shows the Third Embodiment of the present invention. In the present embodiment, first,
`after an interelement separation region (51) by selective oxidation (LOCOS) is formed on one
`principal surface of the first conductive-shaped (for example, p-shaped or n-shaped ) silicon
`substrate (21) as shown in Fig. 7A, the gate electrode (28), for example, made of polycrystalline
`silicon is formed on a predetermined area in the element formation region (26) via the gate
`insulating film (27), and in addition, the SiO2 sidewall part (29a) of the gate electrode (28) is
`formed as similar to the embodiments above.
`
` Next, as shown in Fig. 7B, after the titanium (Ti) layer (30) is deposited and formed on the
`entire surface, the titanium silicide (TiSi2) layer (31) is formed by annealing at a high
`temperature in a short time and by removal of an unreacted titanium layer thereafter, and a so-
`called titanium salicide is formed. When this titanium silicide layer (31) is formed, titanium is
`diffused along the interface between the separation region (51), and the silicon substrate (21)
`from the end edge of the interelement separation region (51), and the titanium silicide layer (31)
`is formed along this interface.
`
` Next, as shown in Fig. 7D, the second conductive-shaped impurities (if these are n-shaped ,
`for example, they are arsenic (As), and if these are p-shaped , for example, they are boron (B))
`
`Page 8 of 21
`
`

`

`(38) ... , the diffusion layers (32) and (33) to be source and drain are formed, respectively. In the
`present embodiment, while a semiconductor wafer, i.e., the substrate (21) or an ion implantation
`gun (52) arranged at a predetermined angle is rotated, the ion implantation is performed by
`varying the angle of the ion implantation gun (52) or the substrate (21) within the range of 90 °
`to 30 °. Fig. 9 is an example to implant ions by varying [the angle of] the ion implantation gun
`(52) within the range of 30 ° to 90 ° while the silicon substrate, i.e., the semiconductor wafer
`(21) is rotated. This results in implantation of impurity ions even along the lower side of the
`interelement separation region (51) due to the selective oxidation, and the diffusion layers (32)
`and (33) having sufficient junction depth are formed.
`
` Subsequently, the interlayer insulating film (34) is formed, and contact holes are formed and
`for example, aluminum electrodes (35) and (36) to be a source electrode and a drain electrode,
`which are connected to the titanium silicide layer (31), are formed, and a target MOS transistor
`(53) shown in Fig. 7E is obtained.
`
` According to such manufacturing method, because [the diffusion layers (32) and (33)] are
`formed by varying the ion implantation angle within the range of 30 ° to 90 °, a sufficiently deep
`junction is obtained even under the end part of the interelement separation region (51). In other
`words, the junction position becomes deeper than the titanium diffusion position to be formed
`along the end part of the interelement separation region. Therefore, the junction leakage current
`based on the titanium diffusion along the end part of the interelement separation region (51) can
`be reduced, and, the junction withstand voltage can be improved.
`
` Furthermore, in the example shown in Fig. 7, after the titanium silicide layer (31) is formed,
`the diffusion layers (32) and (33) are formed by ion implantation, but the titanium silicide (31)
`can be formed after the diffusion layers (32) and (33) are formed, and a similar effect can be
`obtained even in this case.
`
` Fig. 8 shows the Fourth Embodiment of the present invention. In the present embodiment, the
`processes from Figs. 8A to 8C are similar to those in the Third Embodiment shown in Figs. 7A
`to 7C. Then, after the titanium silicide layer (31) is formed, the wafer (21) or the ion
`implantation gun is rotated by varying the ion implantation angle within the range of 30 ° to 90 °
`as similar to the embodiment above shown in Fig. 8D and the second conductive-shaped
`impurities (38) are induced into the titanium silicide layer (31).
`
` Next, as shown in Fig. 8E, the interlayer insulating film (34) is formed, and impurities in the
`titanium silicide layer (31) are solid-phase-diffused into the silicon substrate (21) by annealing at
`approximately 850 °C, and the diffusion layers (32) and (33) to be source and drain are formed,
`respectively.
`
` Subsequently, contact holes are formed in the interlayer insulating film (34), and for example,
`aluminum electrodes (35) and (36) to be a source electrode and a drain electrode, which are
`connected to the titanium silicide layer (31) via these contact holes, respectively, and a target
`MOS transistor (55) shown in Fig. 8F is obtained.
`
`Page 9 of 21
`
`

`

` According to such manufacturing method, since the second conductive-shaped impurities (38)
`are induced by varying the ion implantation angle after the titanium silicide layer (31) is formed,
`these impurities (38) are sufficiently induced into the entire titanium silicide layer (31), i.e., a
`portion along the end part of the interelement separation region (51). Then, since the diffusion
`layers (32) and (33) are formed due to the solid-phase diffusion from this titanium silicide layer
`(31), junction with the substrate (21) shall be formed deeper than the titanium silicide layer (31)
`even in the portion corresponding to the end part of the interelement separation region (51).
`Therefore, the junction leakage current and the junction withstand voltage based upon the
`titanium diffusion along the end part of the interelement separation region (51) can be improved,
`and, crystal defects will not occur at the time of the ion implantation because of the solid-phase
`diffusion, and the junction leakage current and the junction withstand voltage can be further
`improved.
`
` Next, a method for improving the film quality of the titanium silicide layer is explained.
`
` As described above, as one of the causes to increase the junction leakage current in association
`with the formation of a titanium silicide, titanium diffusion along the end part of the interelement
`separation region due to selective oxidation is exemplified, and as another cause, because of the
`non-uniformity of the reaction of the titanium silicide, the titanium silicide layer and the junction
`part may partially approximate. As one of the causes not to unify the reaction of this titanium
`silicide, the poor surface morphology of the titanium layer (15) at the time of forming the
`titanium layer (15) by sputtering as shown in Figs. 13A to 13C is reflected. In other words, a
`leakage current (18) easily occurs at a portion where the titanium silicide layer (17) and the
`junction part (j) approximate. Furthermore, in the diagrams, (1) represents a first conductive-
`shaped silicon substrate, (2) represents an interelement separation region, (15) represents a
`titanium layer, and (17) represents a titanium silicide layer.
`
` As a method to improve this, to eliminate the non-uniformity of the reaction at the time of
`forming the titanium silicide layer, high-frequency bias at approximately 50 W or direct-current
`bias is added at the time of titanium sputtering to form a titanium layer. When the titanium layer
`is formed by bias sputtering as mentioned above, in the surface morphology, obtainment of 16
`times or greater flatness is confirmed according to observation with an electron scanning
`microscope (SEM) compared to the titanium layer formed by sputtering without adding any bias.
`The surface morphology is improved by adding the bias, but the titanium film thickness
`distribution within a wafer is worsened. A curve (I) in Fig. 10 indicates variation of the titanium
`film thickness within a 5-inch wafer relative to bias sputter power. Further, Fig. 11 shows a rate
`of deposition of the titanium layer within a 5-inch wafer using the RF bias power as a parameter.
`The symbols 1 to 9 indicate a point within the semiconductor wafer (21), respectively. The
`symbol  indicates film thickness in the horizontal direction, and the symbol (cid:1) indicates film
`thickness in the vertical direction. It is ascertained that the titanium film thickness distribution is
`worsened as the bias power is increased. According to the results in Figs. 10 and 11 above,
`approximately 50 W of the bias power is suitable. Fig. 12 shows a difference of the junction
`
`Page 10 of 21
`
`

`

`leakage currents between in the case of depositing titanium by bias sputtering and further
`forming a titanium silicide layer and in the case of depositing titanium by sputtering without
`adding bias, and in the titanium silicide layer where titanium has been deposited by bias
`sputtering, the junction leakage current is reduced.
`
` In the meantime, conventionally, as described above, because of poor surface morphology of
`the titanium silicide layer (it also causes roughness on the titanium silicide (TiSi2) surface by
`thermal stress due to a rise of the temperature on the occasion of reaction of titanium silicide
`(TiSi2) to 800 °C to 900 °C), roughness occurs to the interlayer insulating film on the upper
`layer. Consequently, a trouble, such as not enabling accurate exposure on the occasion of
`forming a minute fine pattern, may occur.
`
` As a method for eliminating this surface roughness on the titanium silicide layer, after the
`titanium silicide layer is formed, annealing at a temperature close to a melting point of the
`titanium silicide (1,540 °C) for an extremely short time using the RTA method or the like is
`applied, and the titanium silicide layer reflows. This improves the surface morphology. For
`example, after annealing of the formed titanium silicide layer at 800 °C to 900 °C for several
`tens of seconds, if an excimer laser at 1,400 mJ/cm2 is irradiated for a short time (for example,
`for 7 seconds) and the titanium silicide layer reflows, it has been confirmed that the surface
`roughness would be eliminated and the flatness of the titanium silicide layer would be improved.
`Therefore, even in the formation step of the minute mask pattern after the formation of the
`interlayer insulating film on the upper layer, accurate exposure can be conducted.
`
` Furthermore, although each embodiment above is a case of applying to the MOS transistor, the
`present invention is applicable even in a method for manufacturing other bipolar transistor.
`
`
`
`[Effect of the Invention]
`
` According to the method for manufacturing a semiconductor device, in the manufacturing of a
`semiconductor device having diffusion layers under a silicide layer, formation of trench
`separation regions having a flange part at the upper side, respectively, enables prevention of
`titanium diffusion along the interface between the separation regions and the semiconducto