Filed on behalf of Godo Kaisha IP Bridge 1
`
`By: Neil F. Greenblum (ngreenblum@gbpatent.com)
`
`Greenblum & Bernstein, P.L.C.
`
`1950 Roland Clarke Place
`
`Reston, VA 20191
`
`Tel: 703-716-1191
`
`Fax: 703-716-1180
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Case IPR2016-012461
`U.S. Patent No. 7,126,174
`____________
`
`PATENT OWNER’S RESPONSE
`
`
`
`
`Mail Stop PATENT BOARD, PTAB
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`1 Case IPR2016-01247 has been consolidated with this proceeding.
`
`
`
`
`
`

`

`TABLE OF CONTENTS
`
`
`
`I.
`
`II.
`
`Page
`INTRODUCTION ....................................................................................... 1
`
`STATEMENT OF MATERIAL FACTS IN DISPUTE ............................... 1
`
`III.
`
`SUMMARY OF PATENT OWNER’S ARGUMENT ................................. 1
`
`IV. THE PERTINENT LAW ............................................................................. 3
`
`A. Obviousness Must Be Established By Showing How The
`References Would Be Combined ....................................................... 4
`
`B.
`
`C.
`
`Petitioner Bears The Burden of Persuasion ........................................ 5
`
`Obviousness Cannot Be Proven By Conclusory Statements ............... 5
`
`V.
`
`TECHNICAL BACKGROUND .................................................................. 7
`
`VI. THE ‘174 PATENT ....................................................................................14
`
`A. Generally ..........................................................................................14
`
`B.
`
`C.
`
`Independent Claim 1 .........................................................................22
`
`The Dependent Claims ......................................................................23
`
`VII. LEVEL OF ORDINARY SKILL ................................................................23
`
`VIII. THE PRIOR ART .......................................................................................24
`
`A. U.S. Patent No. 5,153,145 (“Lee”) ....................................................24
`
`B.
`
`U.S. Patent No. 5,021,353 (“Lowrey”) ..............................................27
`
`C. U.S. Patent No. 5,539,229 (“Noble”) ................................................32
`
`D. U.S. Patent No. 4,506,434 (“Ogawa”) ..............................................37
`
`E.
`
`Other Unexplained “Prior Art” .........................................................40
`
`IX. CLAIM CONSTRUCTION ........................................................................41
`
`X. ARGUMENT..............................................................................................43
`
`A. Why The References Are Not Combinable .......................................43
`
`B.
`
`Lee In Combination With Noble/Ogawa Do Not Render The
`Challenged Claims Obvious ..............................................................49
`
`1.
`
`2.
`
`Petitioner’s Position ................................................................49
`
`Lee and Noble/Ogawa Are Not Combinable To Arrive At
`The Claimed Invention ...........................................................50
`
`
`
`i
`
`

`

`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`Lee And Ogawa Are Not Combinable To Arrive At the
`Claimed Invention ..................................................................59
`
`Substituting The Trench Isolation of Noble/Ogawa Into
`Lee Conflates Two Contradictory Designs ..............................63
`
`A Combination Of Lee And Noble/Ogawa Would Be Non-
`Functional ...............................................................................69
`
`No “Second” L-Shaped Sidewalls ...........................................70
`
`Lee Was Aware Of Trench Isolation But Chose Not To
`Implement It ...........................................................................72
`
`Any “Second” Sidewalls On The Interconnection Would
`Not Have An “L” Shape..........................................................73
`
`Lee In Combination With Noble Also Would Not Disclose
`“First Silicide Layers Formed On Regions Located On
`The Sides Of The First L-Shaped Sidewalls Within The
`Active Area.” ..........................................................................79
`
`10.
`
`Petitioner’s Proposed Silicide “Layer” Is Portrayed To Be
`A Small Diameter Circular Element (Wire Or Cylinder)
`That Runs Along The Gate Width Of The Device ...................81
`
`11. Conclusions Regarding Claim 1 ..............................................83
`
`12. Dependent Claims ...................................................................84
`
`a.
`
`b.
`
`c.
`
`d.
`
`e.
`
`f.
`
`g.
`
`Lee In Combination With Noble/Ogawa Would Not
`Render Claims 2 And 6 Obvious ...................................84
`
`Lee In Combination With Noble/Ogawa Would Not
`Render Claims 3 And 15 Obvious .................................84
`
`Lee In Combination With Noble/Ogawa Would Not
`Render Either Claims 5 And 16 Obvious ......................85
`
`Lee In Combination With Noble/Ogawa Would Not
`Render Claims 7, 17, And 18 Obvious ..........................86
`
`Lee In Combination With Noble/Ogawa Would Not
`Render Claim 9 Obvious ...............................................86
`
`Lee In Combination With Noble/Ogawa Would Not
`Render Claim 10 Obvious .............................................87
`
`Lee In Combination With Noble/Ogawa Would Not
`Render Claim 11 and 12 Obvious .................................89
`
`
`
`ii
`
`

`

`h.
`
`Lee In Combination With Noble/Ogawa Would Not
`Render Claim 14 Obvious .............................................90
`
`13. Conclusions Regarding Lee and Noble/Ogawa .......................91
`
`C.
`
`Lowrey In Combination With Noble/Ogawa Do Not Render The
`Challenged Claims Obvious ..............................................................94
`
`1.
`
`2.
`
`Petitioner’s Position ................................................................94
`
`A POSITA Would Not Substitute The Trench Isolation Of
`The Types Disclosed In Noble Or Ogawa For The LOCOS
`Isolation Of Lowrey ................................................................94
`
`3.
`
`Lowrey ....................................................................................95
`
`a.
`
`Standard Planarization of the Lowrey Device Would
`Ruin the Lowrey Device ................................................99
`
`b.
`
`Lowrey Does Not Have L-Shaped Sidewalls ............... 102
`
`Noble .................................................................................... 104
`
`Ogawa .................................................................................. 106
`
`Lowrey Used LOCOS Despite Earlier Familiarity With
`STI ........................................................................................ 110
`
`Substituting The Trench Isolation Of Noble/Ogawa Into
`Lowrey Conflates Two Contradictory Device Designs .......... 111
`
`The Combination Of References Fails To Disclose “First”
`L-Shaped Sidewalls Formed Over The Side Surfaces of
`the Gate Electrode – or – “Second” L-Shaped Sidewalls
`Formed On the Side Surfaces Of The Interconnect ............... 117
`
`Nothing Suggests That L-Shaped Sidewalls Would Form
`On The Interconnection ........................................................ 118
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`10. Conclusions Regarding Claim 1 ............................................ 120
`
`11. Dependent Claims ................................................................. 121
`
`a.
`
`b.
`
`c.
`
`Lowrey In Combination With Noble/Ogawa Would
`Not Render Claims 4, 5, 8, and 16 Obvious ................ 122
`
`Lowrey In Combination With Noble/Ogawa Would
`Not Render Claims 9 and 10 Obvious ......................... 122
`
`Lowrey In Combination With Noble/Ogawa Would
`Not Render Claims 11 and 12 Obvious ....................... 122
`
`
`
`iii
`
`

`

`d.
`
`Lowrey In Combination With Noble/Ogawa Would
`not Render Claim 14 Obvious ..................................... 124
`
`12. Conclusions Regarding Lowrey And Noble/Ogawa .............. 125
`
`XI. CONCLUSION ........................................................................................ 128
`
`
`
`
`
`iv
`
`

`

`TABLE OF AUTHORITIES
`
`
`CASES
`
`Allied Erecting and Dismantling Co., Inc. v. Genesis Attachments, LLC,
` 825 F.3d 1373 (Fed. Cir. 2016) ............................................................................ 7
`Arendi S.A.R.L. v. Apple Inc.,
` 832 F.3d 1355 (Fed. Cir. 2016) ............................................................................ 6
`Godo Kaisha IP Bridge 1 v. Broadcom Limited et al.,
` USDC EDTEX 2:16-cv-00134-JRG-RSP ...........................................................41
`Hockerson-Halberstadt, Inc. v. Avia Group Int’l,
` 222 F.3d 951 (Fed. Cir. 2000) .............................................................................82
`In re Giannelli,
` 739 F.3d 1375 (Fed. Cir. 2014) ............................................................................ 6
`In re Lee,
` 277 F.3d 1338 (Fed. Cir. 2002) ............................................................................ 7
`In re Magnum Oil Tools International, Ltd.,
` 829 F.3d 1364 (Fed. Cir. 2016) ............................................................................ 5
`In re Marcel Van Os et al.,
` Appeal No. 2015-1975 (Fed. Cir. Jan. 3, 2017) .................................................... 6
`In re Oelrich,
` 666 F.2d 578 (C.C.P.A. 1981) .............................................................................81
`In re Warsaw Orthopedic, Inc.,
` 832 F.3d 1327 (Fed. Cir. 2016) ............................................................................ 6
`In re Wright,
` 569 F.2d 1124 (CCPA 1976)...............................................................................82
`Innogenetics, N.V. v. Abbott Labs.,
` 512 F.3d 1363 (Fed. Cir. 2008) ....................................................................... 4, 44
`Intri–Plex Technologies, Inc. and MMI Holdings, Ltd. v. Saint-Gobain
`Performance Plastics Rencol Limited,
` IPR2014-00309, Paper 83 (PTAB, March 23, 2015) ..........................................40
`Kinetic Concepts, Inc. v. Smith & Nephew, Inc.,
` 688 F.3d 1342 (Fed. Cir. 2012) ....................................................................... 4, 44
`Kingbright Elecs. Co. v. Cree, Inc.,
` IPR2015-00746, Paper 8 (PTAB, Aug. 20, 2015) ...............................................40
`
`
`
`v
`
`

`

`
`Knauf Insulation, Inc. v. Rockwool Int’l A/S,
` 2017 U.S. App. LEXIS 3450 (Fed. Cir. 2017).....................................................81
`KSR Int’l Co. v. Teleflex Inc.,
` 550 U.S. 398 (2007) .......................................................................................... 4, 7
`Personal Web Technologies, LLC, v. Apple, Inc.,
` 121 USPQ2d 1578 (Fed. Cir. 2017) ............................................................ 2, 5, 44
`Pfizer, Inc. v. Apotex, Inc.,
` 480 F.3d 1348 (Fed. Cir. 2007) ............................................................................ 7
`Phillips v. AWH Corp.,
` 415 F.3d 1303 (Fed. Cir. 2005) ...........................................................................41
`Rudolph Techs., Inc. v. Camtek, Ltd.,
` 2016 U.S. App. LEXIS 23256 (Fed. Cir. 2016) .................................................... 4
`
`STATUTES
`
`35 U.S.C. § 103(a) ................................................................................................. 1
`35 U.S.C. § 311(b) ................................................................................................40
`35 U.S.C. § 316(e) ................................................................................................. 5
`
`REGULATIONS
`
`37 C.F.R. § 42.100(b) ...........................................................................................41
`37 C.F.R. § 42.120 ................................................................................................. 1
`
`
`
`
`vi
`
`

`

`
`
`Exhibit
`No.
`
`2001
`
`2002
`
`2003
`
`2004
`
`EXHIBIT LIST
`
`Description
`
`Substitute Declaration of Dr. E. Fred Schubert,
`Ph.D. in support of Patent Owner’s Preliminary
`Response filed in IPR2016-01246 on October 5,
`2016.
`
`Schematic illustration of the Chemical Mechanical
`Polishing process from Steigerwald, Murarka, and
`Gutmann, Chemical Mechanical Planarization of
`Microelectronic Materials (1997).
`
`Schematic illustration of the Chemical Mechanical
`Polishing process from the Motorola Company.
`SCSolutions.com. Accessed September 30, 2016.
`http://www.scsolutions.com/chemical-mechanical-
`planarization-cmp-controllers-0.
`
`Photograph of a Chemical Mechanical Polishing
`Tool from the Applied Materials Company.
`BusinessWire.com. Accessed October 5, 2016.
`http://www.businesswire.com/news/home/20040711
`005007/en/Applied-Materials-Revolutionizes-
`Planarization-Technology-Breakthrough-Reflexion.
`
`2005
`
`Troxel, Boning, McIlrath “Semiconductor Process
`Representation.” Wiley Encyclopedia of Electrical
`and Electronics, pp.139 –147 (1999).
`
`2006
`
`U.S. Patent No. 6,052,319 to Jacobs.
`
`2007
`
`U.S. Patent No. 6,952,656 to Cordova et al.
`
`2008
`
`Hunt, “Low Budget Undergraduate
`Microelectronics Laboratory.” University
`Government Industry Microelectronics Symposium,
`pp.81-87 (2006).
`
`
`
`
`
`vii
`
`Newly
`Submitted
`
`Served
`only
`
`
`
`
`
`
`
`
`
`
`
`
`
`

`

`Exhibit
`No.
`
`Description
`
`Newly
`Submitted
`
`2009
`
`U.S. Patent No. 7,074,709 to Young.
`
`
`
`
`
`2010
`
`2011
`
`2012
`
`2013
`
`2014
`
`2015
`
`2016
`
`2017
`
`2018
`
`2019
`
`2020
`
`2021
`
`Burckel, “3D-ICs created using oblique processing.”
`Advanced in Patterning Materials and Processes
`XXXIII, pp. 1–12 (2016).
`
`Substitute Declaration of Dr. E. Fred Schubert,
`Ph.D. in support of Patent Owner’s Preliminary
`Response filed in IPR2016-01247 on October 7,
`2016.
`
`Served
`only
`
`Declaration of Dr. E. Fred Schubert, Ph.D. in
`support of Patent Owner’s Response filed in
`IPR2016-01246 on March 24, 2017.
`
`Thompson, L. F. “An Introduction to Lithography.”
`Introduction to Microlithography, ACS Symposium
`Ser., American Chemical Society, pp. 1-13 (1983).
`
`CA1275846 C to Roland et al.
`
`U.S. Patent No. 5,314,843 to Yu et al.
`
`U.S. Patent No. 5,231,306 to Meikle et al.
`
`U.S. Patent No. 4,529,621 to Ballard.
`
`U.S. Patent No. 5,310,624 to Ehrlich.
`
`U.S. Patent No. 5,097,422 to Corbin, II et al.
`
`Declaration of Amanda Dove.
`
`U.S. Patent No. 4,952,524 to Lee et al.
`
`x
`
`x
`
`x
`
`x
`
`x
`
`x
`
`x
`
`x
`
`x
`
`x
`
`
`
`viii
`
`

`

`Description
`
`Newly
`Submitted
`
`x
`
`x
`
`x
`
`x
`
`x
`
`x
`
`Exhibit
`No.
`
`2022
`
`2023
`
`2024
`
`2025
`
`2026
`
`Bryant, A.; Haensch, W.; Geissler, S; Mandelman,
`Jack; Poindexter, D.; and Steger, M. “The Current-
`Carrying Corner Inherent to Trench Isolation.”
`IEEE Electron Device Letters, Vol. 14, No. 8, pp.
`412-414 (1993).
`
`Ohe, Kikuyo; Odanaka, Shinji; Moriyama, Kaori;
`Hori, Takashi; and Fuse, Genshu. “Narrow-Width
`Effects of Shallow Trench-Isolated CMOS with n+-
`Polysilicon Gate.” IEEE Transactions on Electron
`Devices, Vol. 36, No. 6, pp. 1110-1116 (1989).
`
`Shigyo, N.; Wada, T.; Fukuda, S.; Hieda, K.,
`Hamamoto, T.; Watanabe, H.; Sunouchi, K.; and
`Tango, H. “Steep Subthreshold Characteristic and
`Enhanced Transconductance of Fully-Recessed
`Oxide (Trench) Isolated 1/4 µm Width MOSFETs.”
`1987 International Electron Devices Meeting, pp.
`636-639 (1987).
`
`Furukawa, T., and Mandelman, J.A. “Process and
`Device Simulation of Trench Isolation Corner
`Parasitic Device.” Journal Of The Electrochemical
`Society, Vol. 135, No. 8, p. 358C, Item 236 (1988).
`
`“Structural Analysis Sample Report” downloaded
`from
`https://www.chipworks.com/TOC/Structural_Analy
`sis_Sample_Report.pdf (2008).
`
`2027
`
`U.S. Patent No. 4,776,922 to Bhattacharyya et al.
`
`
`
`ix
`
`

`

`Exhibit
`No.
`
`Description
`
`Newly
`Submitted
`
`Subbanna, S.; Ganin, E.; Crabbé, E.; Comfort, J.;
`Wu, S.; Agnello, P.; Martin, B.; McCord, M.;
`Newman, H. Ng. T.; McFarland, P.; Sun, J.; Snare,
`J.; Acovic, A.; Ray, A.; Gehres, R.; Schulz, R.;
`Greco, S.; Beyer, K.; Liebmann, L.; DellaGuardia,
`R.; Lamberti, A. “200 mm Process Integration for a
`0.15 µm Channel-Length CMOS Technology Using
`Mixed X-Ray / Optical Lithography.” Proceedings
`of 1994 IEEE International Electron Devices
`Meeting, pp. 695-698 (1994).
`
`Chung, J.; Jeng, M.-C.; Moon, J.E.; Wu, A.T.;
`Chan, T.Y.; Ko, P.K.; Hu, Chenming. “Deep-
`Submicrometer MOS Device Fabrication Using a
`Photoresist-Ashing Technique.” IEEE Electron
`Device Letters, Vol. 9. No. 4, pp. 186-188 (1988).
`
`Tanaka, Tetsu; Suzuki, Kunihiro; Horie, Hiroshi;
`Sugii, Toshihiro. “Ultrafast Low-Power Operation
`of p+-n+ Double-Gate SOI MOSFETS.” 1994
`Symposium on VLSI Technology Digest of Technical
`Papers, pp. 11-12 (1994).
`
`2028
`
`2029
`
`2030
`
`2031
`
`WIPO Publication No. WO 90/05377 to Lowrey.
`
`2032
`
`Kaufman, F. B.; Thompson, D. B.; Broadie, R. E.;
`Jaso, M. A.; Guthrie, W. L.; Pearson, D. J.; and
`Small, M. B. “Chemical‐Mechanical Polishing for
`Fabricating Patterned W Metal Features as Chip
`Interconnects.” Journal of The Electrochemical
`Society, Vol. 138, No. 11, pp. 3460-3465 (1991).
`
`x
`
`x
`
`x
`
`x
`
`x
`
`
`
`x
`
`

`

`Exhibit
`No.
`
`Description
`
`Newly
`Submitted
`
`Landis, H.; Burke, P.; Cote, W.; Hill, W.; Hoffman,
`C.; Kaanta, C.; Koburger, C.; Lange, W.; Leach, M.;
`and Luce, S. “Integration of chemical-mechanical
`polishing into CMOS integrated circuit
`manufacturing.” Thin Solid Films, Vol. 220, No. 1-
`2, pp.1-7 (1992).
`
`Library of Congress Catalog Record of
`Steigerwald, Murarka, and Gutmann, Chemical
`Mechanical Planarization of Microelectronic
`Materials (1997).
`
`Library of Congress Catalog Record of Introduction
`to Microlithography, ACS Symposium Ser.,
`American Chemical Society (1983).
`
`Library of Congress Catalog Record of IEEE
`Electron Device Letters, Vol. 14, No. 8 (1993).
`
`Library of Congress Catalog Record of IEEE
`Transactions on Electron Devices, Vol. 36, No. 6
`(1989).
`
`Front cover and table of contents of 1987
`International Electron Devices Meeting (1987).
`
`Front cover of Proceedings of 1994 IEEE
`International Electron Devices Meeting (1994).
`
`2033
`
`2034
`
`2035
`
`2036
`
`2037
`
`2038
`
`2039
`
`x
`
`x
`
`x
`
`x
`
`x
`
`x
`
`x
`
`
`
`xi
`
`

`

`I.
`
`INTRODUCTION
`
`Pursuant to 37 C.F.R. § 42.120, Patent Owner Godo Kaisha IP Bridge 1
`
`(“Patent Owner”) respectfully asserts that Petitioner Taiwan Semiconductor
`
`Manufacturing Company Limited (“Petitioner”) has failed to prove that claims 1-
`
`12 and 14-18 (“challenged claims”) of U.S. Patent No. 7,126,174 (Exhibit 1001,
`
`“the ‘174 Patent”) are unpatentable under 35 U.S.C. § 103(a) as obvious over the
`
`asserted combinations of U.S. Patent No. 5,153,145 (Lee)(Exhibit 1002); U.S.
`
`Patent No. 5,021,353 (Lowrey)(Exhibit 1017); U.S. Patent No. 5,539,229
`
`(Noble)(Exhibit 1015); and/or U.S. Patent No. 4,506,434 (Ogawa)(Exhibit
`
`1010)(collectively “the Cited Prior Patents”).
`
`II.
`
`STATEMENT OF MATERIAL FACTS IN DISPUTE
`
`Petitioner did not submit a statement of material facts in its IPR petition. As
`
`such, no response is due.
`
`III. SUMMARY OF PATENT OWNER’S ARGUMENT
`
`Petitioner has elected not to explain how the prior art elements would be
`
`assembled to arrive at the claimed inventions. Petitioner submits that: “The
`
`complexity of IC fabrication and the technical community’s recognition of that
`
`premise are not at issue in these proceedings.” Paper 13, p.7.
`
`Patent Owner submits that the technical community’s recognition of the
`
`complexities of IC fabrication go to the heart of the issue in this case. It is
`
`
`
`1
`
`

`

`precisely why Petitioner has the burden of establishing how the identified
`
`components could be assembled by the POSITA to arrive at the claimed invention
`
`given the numerous fabrication considerations that must be taken into account.
`
`The amount of explanation needed to meet the governing legal
`
`standards to enable judicial review and to avoid judicial
`
`displacement of agency authority-necessarily depends on
`
`context. A brief explanation may do all that is needed if, for
`
`example, the technology is simple and familiar and the prior art
`
`is clear in its language and easily understood. See Ariosa, 805
`
`F.3d at 1365-66. On the other hand, complexity or obscurity of
`
`the technology or prior-art descriptions may well make more
`
`detailed explanations necessary.
`
`Personal Web Technologies, LLC, v. Apple, Inc., 121 USPQ2d 1578, 1584 (Fed.
`
`Cir. 2017).
`
`Numerous references attest to the complexities involved (see Exhibits 2013 -
`
`2019) and every patent cited in this case goes to great length to describe the
`
`fabrication sequence that is contemplated. Exhibit 2012, ¶61. Petitioner’s premise
`
`is a smokescreen to hide their inability to establish that a POSITA would combine
`
`the teachings of their references in a way that is possible and makes sense.
`
`The Petition fails to establish that it would have been obvious to a person of
`
`ordinary skill in the art (“POSITA”) to modify the semiconductor device formed
`
`by LOCOS (Local Oxidation of Silicon) disclosed in Lee or Lowrey with the
`
`
`
`2
`
`

`

`shallow trench isolation (STI) disclosed in Noble or Ogawa, to arrive at the
`
`invention recited in the challenged claims. Petitioner’s obviousness arguments fail
`
`to demonstrate that there is a reasonable likelihood that at least one of the
`
`challenged claims is unpatentable because:
`
`1.
`
`Petitioner has failed to explain how the primary and secondary
`
`references would be combined, in other than conclusory terms.
`
`2.
`
`A POSITA would not have combined the Cited Prior Patents to arrive
`
`at the inventions recited in the challenged claims.
`
`3.
`
`Even if the references are combined, they would still not teach some
`
`of the claimed elements.
`
`IV. THE PERTINENT LAW
`
`Semiconductor devices are made by complicated sequences of layering,
`
`etching, oxidizing, etc. They are not simple mechanical cases where anything one
`
`can imagine, a POSITA could make or would want to make. Exhibit 2013, p. 5;
`
`Exhibit 2014, p.4; Exhibit 2015, 2:52-61; Exhibit 2016, 2:19-24; Exhibit 2017,
`
`6:23-31; Exhibit 2018, 1:18-29; Exhibit 2019, 2:9-19.; Exhibit 2012, ¶61.
`
`Petitioner does not explain how the processes of the Cited Prior Patents would
`
`have been combined by a POSITA to arrive at the claimed invention.
`
`
`
`3
`
`

`

`A. Obviousness Must Be Established By Showing How The
`References Would Be Combined
`
`
`The Board observed that “Claim 1 is an apparatus claim, not a method
`
`claim” and “does not recite anything about how those components are formed.”
`
`Decision, pp.16-17.
`
`Most respectfully, it is not seen how an obviousness analysis can be
`
`undertaken in this case, without both a rationale of why such a combination would
`
`be desirable and how such a combination could be achieved. “A factfinder should
`
`be aware, of course, of the distortion caused by hindsight bias and must be cautious
`
`of arguments reliant upon ex post reasoning.” Rudolph Techs., Inc. v. Camtek, Ltd.,
`
`2016 U.S. App. LEXIS 23256 (Fed. Cir. 2016)(citing KSR Int’l Co. v. Teleflex
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`Inc., 550 U.S. 398, 421 (2007)). Indeed, one must “‘be careful not to allow
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`hindsight reconstruction of references to reach the claimed invention without any
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`explanation as to how or why the references would be [modified] to produce the
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`claimed invention.’” Kinetic Concepts, Inc. v. Smith & Nephew, Inc., 688 F.3d
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`1342, 1368 (Fed. Cir. 2012)(quoting Innogenetics, N.V. v. Abbott Labs., 512 F.3d
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`1363, 1374 n.3 (Fed. Cir. 2008))(emphasis added).
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`In an analogous situation, the Federal Circuit reversing the PTAB, held:
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`Indeed, the Board nowhere clearly explained, or cited evidence
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`showing, how the combination of the two references was
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`supposed to work.
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`
`
`4
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`

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`Personal Web Technologies, LLC, v. Apple, Inc., 121 USPQ2d at 1584 (emphasis
`
`in original).
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`The patent in that case related to methods or devices for performing methods
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`of locating data and controlling access to data by giving a data file a substantially
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`that depends on the file’s content. Id., at 1579. Although related to software, the
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`point is that when combining references, an obviousness determination requires an
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`explication of how the teachings would be combined to operate. When combining
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`semiconductor device features from two distinct devices, the fabricated features are
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`inseparable from how the features are formed during the fabrication process. If the
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`processes of laying down the features are incompatible, absent some other
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`additional teaching, the proposed combination will not result in a workable device.
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`B.
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`Petitioner Bears The Burden of Persuasion
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` “‘In an inter partes review, the burden of persuasion is on the petitioner to
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`prove ‘unpatentability by a preponderance of evidence,’ 35 U.S.C. § 316(e), and
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`that burden never shifts to the patentee.’” In re: Magnum Oil Tools International,
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`Ltd., 829 F.3d 1364, 1375 (Fed. Cir. 2016).
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`C. Obviousness Cannot Be Proven By Conclusory Statements
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`“To satisfy its burden of proving obviousness, a petitioner cannot employ
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`mere conclusory statements. The petitioner must instead articulate specific
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`
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`5
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`

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`reasoning, based on evidence of record, to support the legal conclusion of
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`obviousness.” Id., at 1380 (emphasis added).
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`A conclusory assertion by the Board that “‘appears to’ support its finding
`
`does not equate to the reasoned explanation needed to support it conclusion.” See
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`Synopsys, 814 F.3d at 1322; see also Lee, 277 F.3d at 1345 (“The [PTAB] cannot
`
`rely on conclusory statements when dealing with…prior art and specific claims,
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`but must set forth the rationale on which it relies.”)In re Warsaw Orthopedic, Inc.,
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`832 F.3d 1327, 1335 (Fed. Cir. 2016) (emphasis added). Arendi S.A.R.L. v. Apple
`
`Inc., 832 F.3d 1355, 1362 (Fed. Cir. 2016)(reversing the PTAB’s determination
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`[...] because the PTAB’s decision was conclusory and unsupported by substantial
`
`evidence); In re Giannelli, 739 F.3d 1375, 1380 (Fed. Cir. 2014)(reversing
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`affirmance of examiner’s rejection where the PTAB analysis “contained no
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`explanation why or how a person having ordinary skill in the art would modify”
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`the prior art to arrive at the claimed invention).
`
`In In re Marcel Van Os et al., Appeal No. 2015-1975 (Fed. Cir. Jan. 3,
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`2017), the Federal Circuit critiqued a conclusory obviousness analysis. While
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`directed to the “why,” rather than the “how,” the decision is nevertheless directly
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`applicable to this case. “But the flexibility afforded by KSR did not extinguish the
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`factfinder’s obligation to provide reasoned analysis. Instead, KSR specifically
`
`instructs that when determining whether there would have been a motivation to
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`6
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`

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`combine, the ‘analysis should be made explicit.’” Id., p.4 (citing KSR at 418).
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`“[T]o invoke ‘common sense’ or any other basis for extrapolating from prior art to
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`a conclusion of obviousness, [the factfinder] must articulate its reasoning with
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`sufficient clarity for review.” Id., p.5. “The agency tribunal must make findings of
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`facts, and present its reasoning in sufficient detail that the court may conduct
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`meaningful review of the agency action.” Id., pp.5-6. (citing In re Lee, 277 F.3d
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`1338, 1346 (Fed. Cir. 2002)).
`
`
`
`The proper test is “whether ‘a skilled artisan would have been motivated to
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`combine the teachings of the prior art references to achieve the claimed
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`invention.’” Allied Erecting and Dismantling Co., Inc. v. Genesis Attachments,
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`LLC, 825 F.3d 1373, 1381 (Fed. Cir. 2016)(quoting Pfizer, Inc. v. Apotex, Inc., 480
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`F.3d 1348, 1361 (Fed. Cir. 2007).
`
`V. TECHNICAL BACKGROUND
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`Integrated circuits (ICs) are highly complex electrical systems located on a
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`small microstructured silicon chip (Si chip). An integrated circuit can have
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`millions of transistors that process, store, and transport information.
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`Transistors or groups of transistors generally need to be electrically isolated
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`from one another, which is accomplished by electrical isolation features. A group
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`of transistors may form a small functional unit such as an inverter unit, which is
`
`accomplished by electrically interconnecting several transistors with each other by
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`
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`7
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`

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`means of interconnects. These interconnects can have a relatively short length
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`(“local interconnects”), medium length (“interconnects”) or a relatively long length
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`(“global interconnects” or “Al or Cu interconnects”). These components, i.e.,
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`transistors, isolation features, and interconnects, are the elementary components of
`
`a Si IC that are necessarily found in all Si ICs. Exhibit 2012, ¶¶41-49, 63, 103.
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`A transistor, specifically the field-effect transistor (FET), uses an electric
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`field (“field effect”) in order to create charge carriers in the transistor’s channel
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`region. The channel region connects the source (S) with the drain (D). The source
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`and drain are separated by a gate (G) that controls the flow of charge in the channel
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`between the source and drain. Exhibit 2012, ¶¶41-42.
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`The gate typically has a three-layer stack consisting of a gate metal or metal-
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`like material (M), a gate dielectric or oxide (O), and a semiconductor (S), thereby
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`forming the MOS layer stack or gate layer stack. Transistors based on the MOS
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`layer stack are called MOSFETs. The circuit layout is the result of (i) the circuit
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`functionality designed by design engineers, and (ii) the designed circuit’s
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`implementation on an IC chip fabricated by a processing sequence devised by
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`process engineers. Exhibit 2012, ¶¶43-45.
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`The processing sequence takes place in a fabrication facility, including a
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`first group of fabrication processes called front end of line (FEOL) processes, and
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`a second group of fabrication processes called back end of line (BEOL) processes.
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`
`
`8
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`

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`The FEOL processes include the fabrication of the transistors (MOSFETs)
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`including the silicidation2 of source, gate, and drain. The BEOL processes include
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`the fabrication of metal-based interconnect lines and associated dielectric layers
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`(interlayer dielectrics or ILDs) that electrically insulate the metal interconnects
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`from each other. Exhibit 2012, ¶46.
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`IC processing requires (i) high spatial precision during lithography (to attain
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`very small patterns) and (ii) cleanliness (to avoid contaminations). The processing
`
`of Si wafers proceeds in a strict sequence of processing steps (or processing
`
`modules) that are carefully chosen in sequence and content. For example, the gate
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`stack of a transistor requires the availability of a Si substrate, followed by the
`
`deposition or growth of the gate dielectric (commonly an oxide), and concluded by
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`the deposition of the gate conductor. This processing sequence is mandatory, and it
`
`would become ineffectual if it were altered. That is, certain elements of an IC may
`
`
`2 The word "silicidation" describes the process of forming a metal silicide.
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`"Salicidation" means "Self-Aligned Silicidation" and thus is a specific variant of
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`the silicidation process. At the present time, silicidation and salicidation are
`
`common processes in the Si IC industry. The term "silicidation" is used throughout
`
`this Response.
`
`
`
`
`
`9
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`require the preexistence of other elements and rely on their presence for the proper
`
`functioning of the ensemble of elements. For example, the source/drain dopant
`
`implant requires the presence of the gate so that the gate can mask the channel
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`region from the subsequent implantation ion beam, i.e., the gate enables the proper
`
`definition of the source/drain implanted regions. Such an implantation in which
`
`the source/drain regions are automatically aligned with the gate electrode is
`
`referred to as a “self-aligned implantation process.” Exhibit 2012, ¶¶47-49.
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`Exhibit 2013, p. 5; Exhibit 2014, p.4; Exhibit 2015, 2:52-61; Exhibit 2016, 2:19-
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`24; Exhibit 2017, 6:23-31; Exhibit 2018, 1:18-29; Exhibit 2019, 2:9-19.
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`A series of individual processing steps constitute a “processing module”. It
`
`is generally not possible to reverse the sequence of processing steps within a
`
`module. For example, the formation of shallow trench isolation (STI) constitutes a
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`processing module that involves: (i) trench etching, (ii) trench refill with silicon
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`dioxide, and (iii) planarization. These steps are the major steps of the trench
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`isolation module.3 Exhibit 2012, ¶50.
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`Planariz