Thin Solid Films, 220 ( 1992) I-1 Integration of chemical-mechanical polishing into CMOS integrated circuit manufacturing Howard Landis, Peter Burke, William Cote, William Hill, Cheryl Hoffman, Carter Kaanta, Charles Koburger, Walter Lange, Micheal Leach and Stephen Lute IBM Technology Products, Essex Junction, VT 05452 (USA) Abstract Planarization by chemical-mechanical polishing (CMP) has been exploited by IBM in the development and manufacture of CMOS products since 198.5. Among the products that use this technology are the 4-Mbit DRAM (which uses polysilicon, oxide, tungsten-line and tungsten-stud planarization) and its logic family (which uses four oxide and four tungsten-stud planarization steps). CMP is also used in the planarization of oxide shallow isolation trenches, as in the 16-Mbit DRAM. Reduced sensitivity to many types of defects is possible with CMP. A wafer that is truly flat is easier to clean, eliminates step coverage concerns, provides for better photolithographic and dry etch yields, and generally minimizes complications from prior level structures. Oxide CMP reduces sensitivity to certain pre-existing defects, such as crystalline inclusions or foreign material in an interlevel dielectric. Metal CMP can reduce the incidence of intralevel shorts relative to conventional RIE processing. Random defects associated with CMP, such as slurry residues and mechanical damage, are controlled by careful optimization of the post-polish clean and of the polish process itself. Systematic defects, such as incomplete planarization over very large structures, are controlled by process optimiza- tion and prudent design limitations. These include such things as constraints on the image size, the distance between images, and/or the local pattern density. Since its introduction in the 4-Mbit DRAM, there has been a steady increase in the use of chemical-mechanical polishing in IBM CMOS products. The number of steps, processes and materials polished continue to rise, both in current and planned future products. Individual applications range from the simple removal of back-side films to complex insulator or metal planarization requiring high removal uniformity. The process tolerances delivered by CMP have decreased faster than image size, even in the face of dramatic increases in circuit and layout complexity. CMP tools are installed in IBM semiconductor manufacturing and development sites worldwide. Chemical- mechanical polish processes and applications provide unique leverage to IBM products, and are a crucial part of both current and planned IBM CMOS technologies. 1. Introduction In semiconductor manufacturing, the pace of techno- logical change requires decreasing the cost yet increas- ing the performance of each new product. This is accomplished by both decreasing the size and increasing the complexity of the structures built on silicon. Future DRAM and CMOS logic products will have smaller devices and denser packing, as well as more levels of photolithography and more levels of wiring. As more layers are built on the silicon surface, it is found that problems with non-planarity become severe [l-6]. Three that impact yield and performance are poor step coverage of deposited films, depth-of-focus of high performance photo tools and residual material after dry etching (Fig. 1). Precision grinding and polishing have long been used for fine glass- and metal-working [7- 111. Although wafer polishing has had an ongoing role in the manu- facture of semiconductor substrates [ 121, and despite numerous research publications [ 13 -231 and patents [24-281, polishing has only recently begun to be recog- nized as a viable tool for large scale manufacturing of integrated circuits [29-361. Today, many of the skills of the lensmaker and silversmith are put to use in the chemical-mechanical polishing (CMP) areas of IBM’s semiconductor manufacturing lines. A CMP tool, reduced to its essentials, consists of a polishing pad affixed to a circular polishing table, and a carrier to hold a wafer against the pad (Fig. 2). Both the table and the carrier are made to rotate (usually in the same direction) as the front of the wafer is pressed down against the pad and polishing slurry is dispensed onto the pad. A typical slurry is water-based and contains both abrasive and chemical additives. The combination of mechanical abrasion and chemical etch causes material to be removed from the surface of the wafer. Protrusions erode more efficiently than re- cessed areas. This leads to planarization of the wafer surface. Elsevier Sequoia
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`Fig. I. Schematic of a trench-style DRAM highlighting some prob- lems associated with non-planarity. Poor step coverage and etch residuals are concerns of locations (A), (B) and (C). The step size (S) should be much less than the depth of focus of the photo tool. I Wafer I Table I I l-4 I I Fig. 2. Schematic diagram of a chemicalLmechanica1 polish tool Among the significant tool parameters are the wafer pressure, the table and carrier speeds, and the mechanics of the wafer carrier. The important process variables include the polish pad and its condition, the slurry, the slurry flow, and the process temperature. Besides these obvious controls, there are many subtle tool- and process- specific variables that profoundly influence the character of the CMP process. Thoroughly understanding and properly controlling these subtle influences are crucial for successful implementation of CMP in manufacturing. 2. Applications Figure 1 depicts a cross-section of an unplanarized deep-trench-style DRAM, as might be found in the 4-Mbit generation. From the deep trench to the metal levels, each structure that introduces topography makes subsequent processing more difficult. CMP is used to improve the planarity of these structures. In deep-trench processing, when a vertical reactive ion etch (RIE) process is used to clear polysilicon fill from a wafer surface, a center seam is propagated down into the trench, and a step forms at the trench edge during overetch. These defects make it difficult to reli- ably cover the trench with another film, such as a strap. Chemicallmechanical polishing, however, is a horizon- tal process: with polysilicon CMP, a seam does not propagate, and a step does not form at the trench edge. Because polysilicon slurries can be quite selective to oxide and nitride masking films [ 161, the polish process stops short once the silicon nitride layer is reached (Fig. 3). Polysilicon CMP was judged to be a more cost-effec- tive and robust method than RIE for removal of the polysilicon overburden. This CMP process was adopted early in the development cycle of the IBM 4-Mbit DRAM and subsequent programs. A second source of topography is the isolation level. Shallow oxide-filled isolation trenches are an attractive alternative to standard recessed oxide (ROX). Besides improving planarity, shallow trench isolation (STI) also eliminates the ROX “bird’s beak” (Fig. l), allowing greater circuit density. The ST1 planarization process for the 16-Mbit DRAM [30] employs a combination of Silicon Nitride Polish,-Stop Layer Fig. 3. SEM cross-sections of polysilicon deep trenches planarized by CMP.
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`H. Landis et al. 1 Chemica- mechanical polishing in CMOS integrated circuits 3 Silicon Nitride Polish-Stop Layer (a) 1.0 pm Isolation (b) 1.0 pm Fig. 4. SEM cross-sections of submicrometer shallow trench isolation test structures. A very thin nitride polish-stop (a) was used to improve flatness after the silicon nitride polish-stop layer was stripped (b). photolithography, spin-apply and blanket etch-back to remove most of the oxide overburden. Oxide polishing is used for final planarization down to a silicon nitride polish stop (Fig. 4). Because CMOS devices are very sensitive to damage in the silicon substrate, the ST1 polish process must have very high uniformity and low defect densities. After isolation, the next level that can obviously benefit from planarization is ILD-I, the interlevel dielectric underneath Metal-l. Reflow of a doped glass [37-411 is often used to minimize the surface angle of this film at gate conductor edges, reducing defects from poor step coverage at Metal-l. But viscous flow can only produce local smoothing [42, 431; planarization over many micrometers is needed to eliminate metal- etch residuals, and planarization over many millimeters is required to alleviate photolithographic depth-of-focus limitations. Oxide polishing proved capable of provid- ing global planarization over these ranges [44-471. Since there is no built-in stop-layer for a “blind polish” of this type, high repeatability and uniformity (across the chip, wafer and lot) are critical to the success of ILD polishing. Substantial increases in final chip yields caused the 4-Mbit and subsequent programs to incor- porate ILD-1 polishing in their process flows. Because the high temperatures needed for reflow can be impractical after the first metal level is defined, there is an even greater need for using CMP to planarize ILD-2, the dielectric underneath Metal-2. The adoption of this process by the 4-Mbit program marked the first use of oxide polishing in an IBM DRAM [29]. Vertical vias are critical to wiring metal levels on a tight pitch. Just as with the deep storage trenches, a RIE process to remove the overburden of metal pro- duces two characteristic via defects: the center seam and the edge step. Metallic liners such as titanium can recess quickly during tungsten RIE, causing a possible third via defect, the edge seam (Fig. 1). In addition, CVD tungsten films are very rough, demanding increased overetch and thereby worsening the three via defects described above. On the other hand, tungsten chemi- cal-mechanical polish has proven to be a reliable high- yield process for via formation. Reliability results from the improved flatness afforded by CMP, while yield improvements arise from the ability of tungsten chemi- cal-mechanical polishing to remove random defects (foreign material) from the surface of the wafer. Tung- sten-stud polishing is used in the 4-Mbit DRAM and subsequent programs. Etched tungsten lines are plagued by some of the same defects as traditionally etched vertical tungsten vias. Because of these problems, an inlaid metal, or “damascene”, process was developed and implemented in 4-Mbit manufacturing [34]. In this process, trenches for the Metal-l conductor are etched in ILD-1 just after the stud holes. A single CVD tungsten deposition then fills the stud holes and the Metal-l trenches, and a single tungsten polish removes the tungsten overburden (Fig. 5). Tungsten damascene not only reduced intra- level shorts, it reduced the overall process cost as well. (With damascene Metal-l, the wafer surface remains flat, so there is no need for ILD-2 planarization.) A scanning electron microscopy (SEM) cross-section of a 4-Mbit DRAM chip is shown in Fig. 6. Chemical- Metal Conta let Fit1 ud -1 Fig. 5. SEM cross-section of Metal-l lines and contact studs from a 4-Mbit DRAM chip.
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`4 H. Lundis et al. / Chemicul mrchunid poli.rhing in CMOS intqrurrcl circuiu Fig. 6. SEM cross-section of a 4-Mbit DRAM chip. mechanical polishing was used to planarize the polysili- con deep trench (not shown), oxide ILD-1, tungsten Metal-l and vias. 3. Manufacturability To understand how CMP is used in a manufacturing environment, it is necessary to first examine the limita- tions of the process. The four phenomena that can most constrain the CMP process are non-uniformity, round- ing, dishing and erosion [34]. These effects are illus- trated in Fig. 7. Non-uniformity refers to polish-rate Non-Unilormity r____-__--_-------~ Rounding _---____-________ 1 \ Dishing r--\ Erosion -\ \ ‘9 /----\ ,/---,, /Y---y\ /y- LJ LI Ll Fig. 7. Non-uniformity, rounding, dishing and erosion can limit the performance of CMP processes. variations, which can occur across a wafer, across a lot, and lot-to-lot. Rounding refers to the ineffective planarization of wide features, and is most common in oxide polishing. Dishing refers to the thinning of the fill material in the center of a wide inlaid trench (ST1 or metal damascene). Erosion results from the inability of the polish stop to completely arrest the polish process; it is most severe when the trench area fraction is high (as in some damascene applications) or when the polish selectivity is low (as with STI). Both dishing and erosion are worsened by overpolishing (Fig. 8). Non-uniformity, rounding, dishing and erosion can be mitigated by process and design changes. The tool, the polish pad and the process all strongly affect non- uniformity. The choice of polish pad has the greatest influence on rounding and dishing: hard, incompress- ible pads planarize best. Erosion depends on the selec- tivity, so the materials set and the slurry chemistry strongly influence erosion. Design rules can also help insure product quality. Automated layout and checking r (a) Nominal Endpoint Linewidth (pm) (b) 25% Overpolish 1 10 100 1 Linewidth (pm) L 0' 00 Fig. 8. Sample data from a damascene metal polish process using a hard
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`and exhibiting approximately 4O:l polish selectivity. The contours represent the normalized line thickness after CMP at (a) nominal endpoint. and (b) after 25% overpolish. For example. the 0.0 contour indicates that 90’%, of the original line thickness is maintained after CMP. Wide lines are measured in the center, where they are thinnest.
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`H. Lundis et al. 1 Chemi~al~~mechuniccrl polishing in CMOS integruted circuits tools guarantee that feature widths and area fractions remain within appropriate bounds, while technology decisions, such as fully landed contacts, can ease some uniformity requirements. BPSG Uniformity requirements vary from level to level. Certain CMP processes, like tungsten studs and polysil- icon deep trench planarization, have a wide process window. This is because a large overpolish can be used to compensate for any non-uniformity. (Small feature sizes limit rounding and dishing, while high polish selectivities minimize erosion.) Other processes, such as STI, ILD and Metal-l, have very tight uniformity requirements. If the 60 tolerance exceeds the product requirement, closed-loop control can reduce non-uni- formity and increase yield. An operator can adjust the polish time if measurements indicate a drift in the polish rate, or an integrated measurement system can provide this feedback for each wafer, but true closed- loop control requires in situ endpoint detection. By minimizing within-wafer variations, and by employing closed-loop control where required, the uniformities for all of the CMP processes discussed in this paper have been sufficient to produce parts with consistently high yield. Fig. 9. Crystalline inclusions that occasionally form in BPSG during reflow anneal can be a source for “stringers”, or etch residuals. after metal RIE. Polishing the ILD-I dielectric proved to be very effective at planarizing these random defects. Damage to the isolation edge or nitride stop-layer can result in an electrical failure if the underlying silicon is affected [48]. ST1 microscratches are controlled by elim- inating process-generated defects and by insuring the cleanliness of the polishing environment. In general, it is more difficult to planarize a wafer than it is to keep it planar. With ILD oxide polishing there is no stop-layer, so the uniformity of the polished film is tightly bound to the uniformity of the polish process itself. But if the wafer is already flat, a dama- scene process can decouple the final film thickness from the polish uniformity. Assuming adequate selectivity, a stop-layer will locally arrest the polish process when endpoint is reached, allowing other areas of the wafer to “catch up”. This effect can provide a substantial process window for well-designed damascene levels [ 341. But the wafer must be truly flat for the damascene process to succeed. The high conformality of the de- posited material guarantees that any void or local depression on the wafer surface would be filled, and the high polish selectivity of a good damascene process insures that the unwanted fill material would remain after polishing. Instead of creating defects, CMP more often acts to remove existing defects. Metal “stringers”, or etch residuals, can form at the edges of large crystalline inclusions that sometimes appear in BPSG during reflow (Fig. 9). Oxide CMP proved effective at pla- narizing these inclusions. Before damascene Metal-l was implemented in our 4-Mbit program, this source of tungsten etch residuals was eliminated by the fully planar surface provided by oxide CMP. In many other cases, including tungsten polishing, CMP has demon- strated a unique ability to effectively remove many pre-existing random defects. 4. Extendability CMP can be extended to more levels, more materials, smaller dimensions and tighter tolerances to satisfy the requirements of future semiconductor products. An obvious manufacturability issue is cleanliness. Oxide and tungsten-stud CMP are used repeatedly to Successful cleaning procedures are designed to take make 0.7~urn CMOS logic chips with four levels of advantage of the flatness of a polished wafer. Since metal (Fig. 10) [33]. The planarization and vertical slurry abrasive is the only type of particle on a polished studs provided by CMP allow the first three metal levels wafer, cleaning procedures are further optimized for the to be fabricated at nearly the same wired pitch (the last different CMP slurries. The success of the many diverse level is built at a relaxed pitch for other reasons). Good polishing operations used at IBM attests to the low early yields [33] are evidence of the ready extendability defect densities achievable with CMP. of CMP to many levels. Scratches in the polished films or etch stops are another concern. Polishing pressures often exceed 5 x lo4 N/m’ ( 7 lb in2), so any foreign particles be- tween the wafer and the polish pad can cause damage. Shallow trench isolation is a particularly sensitive test. As successive generations move to smaller structures and tighter tolerances, two general rules become appar- ent. (1) Small isolated features, planarize best. Wide features (because of rounding and dishing) and dense areas (because of erosion) are more difficult. (2) The
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`H. Lords
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`et ul.
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`Chemicul~mec~huniccrl polishing
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