1110
`
`Narrow-Width Effects of Shallow Trench-Isolated
`CMOS with n+-Polysilicon Gate
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 36. NO. 6. JUNE 1989
`
`KIKUYO OHE, SHINJI ODANAKA, KAORI MORIYAMA, TAKASHI HORI, MEMBER, IEEE, A N D
`GENSHU FUSE
`
`Abstract-This paper describes the narrow-width effects of n- and
`p-MOSFET’s with shallow trench isolation. The MOSFET’s with n+-
`polysilicon gates were fabricated down to channel widths of 0.5 pm by
`using a novel planarization process with an etch stop. The threshold
`behavior is characterized as a function of both the sidewall-implanted
`boron and the threshold adjustment implant doses, using the experi-
`mental data and three-dimensional process/device simulations. The
`trench-isolated n-MOSFET shows the narrow-width effect with the ex-
`cess boron doses implanted in the sidewalls. It is found that the lateral
`diffusion of sidewall-implanted boron induces enhancement of the edge
`current although the devices show narrow-width effects. The trench-
`isolated p-MOSFET’s show narrow-width effects under the buried-
`channel mode and the inverse-narrow-width effect when the surface
`channel conditions dominate at threshold. It is found that the narrow-
`width effect of p-MOSFET’s strongly depends on the threshold adjust-
`ment by means of the counter doping.
`
`I. INTRODUCTION
`T is well known that MOSFET’s with shallow trench
`
`I isolation (fully recessed isolation oxide) show an in-
`
`verse-narrow-width effect based on fringing electric fields
`111. This increases the contribution of the channel edge
`current to the total channel current as the channel width
`is reduced. It has been shown that this effect depends on
`the isolation oxide structure [ 2 ] , the slope of the trench
`isolation oxide [3], and is enhanced by the fixed charge
`densities Q,, at the interfaces of the isolation oxide [2],
`14). To suppress this undesirable structural effect, the
`proper boron implantation into the tapered sidewalls 151,
`[6] and the use of large tilt angles during implantation into
`the sidewalls [7] have been proposed. The development
`of n f -polysilicon gate CMOS with trench isolation re-
`quires study concerning the threshold behavior for the
`surface n-MOSFET’s with boron-implanted sidewalls and
`buried p-MOSFET’s. Until now, however, the threshold
`characteristics of the n-MOSFET’s using boron-im-
`planted sidewalls have not been investigated in detail and
`the buried p-channel mode has not been considered as an
`important factor in characterizing the structural effects of
`trench isolation.
`In this paper, the narrow-width effect of trench-isolated
`n- and p-MOSFET’s is characterized by using both ex-
`
`Manuscript received September 13, 1988; revised January 16, 1989.
`The review of this paper was arranged by Associate Editor P.K. KO.
`The authors are with the Semiconductor Research Center, Matsushita
`Electric Industrial Company. Ltd., Moriguchi, Osaka 570, Japan.
`IEEE Log Number 8927650.
`
`perimental data and numerical results from a three-dimen-
`sional proceddevice integrated simulator-SMART
`[SI,
`[9]. Section I1 briefly describes the trench-isolation tech-
`nology with a novel planarization process [lo] for fabri-
`cating the trench-isolated MOSFET’s. In Section 111, the
`experimental technique and simulation method are de-
`scribed. In Section IV, the characteristics of n-MOS-
`FET’s are studied as a function of boron doses for side-
`wall implantation. The scaling of the channel width is also
`discussed. In Section V, the characteristics of p-MOS-
`FET’s are studied as a function of BF2 doses used for the
`threshold adjustment. The results clarify the channel width
`dependence of the sidewall-implanted boron profile (for
`n-channel) and conduction mechanisms (for p-channel) for
`the inverse-narrow-width and narrow-width effects at
`threshold.
`
`11. PLANARIZATION PROCESS
`
`For this work, the test devices were fabricated with
`trench isolation using a newly developed planarization
`process called ‘‘Planarization with the resist/oxide/resist
`and poly silicon (PRORPS)” [lo]. In this section, the
`trench-isolation process of PRORPS is briefly described.
`The fabrication process for PRORPS is shown in Fig.
`1. As shown in Fig. l(a), a thermal Si02 film is formed
`to a thickness of 50 nm. A polysilicon film is formed on
`the S O 2 , and it is used as a buffer of the subsequent etch-
`back process. An LPCVD Si02 film is deposited, and
`shallow vertical trenches 0.8 pm deep are formed by dry
`etching. Boron ions are implanted into the trench side-
`walls of n-channel device regions with a large tilt angle,
`while p-channel device regions are covered with a resist.
`A thin thermal Si02 film is formed in the trench regions.
`During this oxidation step, the polysilicon film and silicon
`substrate are slightly rounded due to the “bird’s beak”
`phenomena.
`In Fig. l(b) the trenches are filled with LPCVD Si02.
`A resist, thin sputtered Si02 film, and a second resist layer
`are formed.
`In Fig. l(c) the second photoresist film is etched to the
`surface of the sputter-deposited S O 2 . The Si02 film, re-
`sist film, and LPCVD Si02 are etched to the polysilicon
`surface using the RIE technique.
`Then, as shown in Fig. l(d), the polysilicon and ther-
`mal Si02 layers are etched to the silicon surface, and a
`
`0018-9383/89/0600-1110$01.00 O 1989 IEEE
`
`Page 1 of 7
`
`IP Bridge Exhibit 2023
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`
`

`

`OHE et al.: NARROW-WIDTH EFFECTS O F SHALSOW TRENCH-ISOLATED CMOS
`
`1111
`
`0 5,02 I rn Poly-s, m 5,0211
`
`0 0 - - 5 0
`
`I c
`0 w
`0 1
`
`1
`
`5. 1 . 7 ~ 1 0 1 7
`6 3 . 2 ~ 1017
`7 . 6 . 4 ~ 1017
`
`BORON
`1 2 0 x 1 0 1 6
`2 4 0 x 1 0 1 6
`3 8 0 x 1 0 1 6
`4 1 6 x 1 0 1 7
`1
`I
`1 5
`1 0
`LATERAL POSITION (pm)
`Fig. 2. The simulated impurity profile of the n-MOSFET with the sidewall
`implantation. The channel width is 1.36 pm and a sidewall boron dose
`of 2.0 x 10’j cm-’ is implanted at 80 keV with 8 degrees.
`
`0 0
`
`I
`0 5
`
`I
`2 0
`
`2 5
`
`1
`
`8
`
`.
`
`1
`
`
`
`1
`
`1
`
`1
`
`Fig. 1 . Schematics of the PRORPS fabrication sequence
`
`thermal Si02 film is formed for the threshqld adjustment
`implantation. At this implantation step, the SiO, surface
`of the trench-isolation region is higher than that of the
`active device region since the polysilicon buffer layer used
`for etch back and as an oxidation mask, and some of the
`thermal SiO, has been removed.
`
`111. EXPERIMENTAL RESULTS AND SIMULATIONS
`The n- and p-MOSFET’s were fabricated using the
`trench-isolation technology mentioned in Section 11. The
`measured devices have a channel length of 0.88 pm, a
`gate oxide of 10.0-nm thickness, and a trench depth of
`0.8 pm. The channel widths are I .36, 1.06, 0.86, 0.66,
`and 0.46 pm, respectively.
`To form the sidewall boron profile in the n-MOSFET’s,
`boron doses of 2.0 x 1013 cmp2 and 4.0 x lOI3 cmP2
`were implanted at 80 keV with the tilt angle of 8 degrees,
`which was measured from the surface normal. The im-
`plant angle as measured from the trench surface normal
`becomes very large.
`The buried p-MOSFET’s with n+-pockets, used as ef-
`ficient punchthrough stops [ 111, were fabricated in a con-
`ventional n-well with a peak concentration of 1.5 x 10l6
`~ r n - ~ . The p-channel devices have BF2-implanted source-
`drain junctions of 0.27 pm and sidewall spacers of 0.2
`pm. BF, doses of 1.0 X 10l2 cm-*, 1.7 x 10” cmP2,
`and 3.2 X 10” cm-2 were implanted at 50 keV as counter-
`doping for obtaining three different threshold voltages.
`
`To understand the channel width dependence of the
`threshold behavior in the above test devices, the SMART
`program [8], [9] has been used, which is a three-dimen-
`sional process/device integrated simulator based on the
`finite-difference approach. The device structure and im-
`purity diffusion were obtained by means of the process
`simulator SMART-P based on input of the fabrication se-
`quence. The SMART-P program contains a numerical ox-
`idation model based on the slow incompressible viscous
`flow of the oxide and a numerical model of interstitial-
`assisted oxidation-enhanced diffusion (OED). The impur-
`ity profiles of the large tilt angle implanted ions are cal-
`culated along the trench structure by using a rotation
`transformation of the coordinates. The threshold voltage
`is defined by the gate voltage at a fixed channel current
`given by In = 50 nA X W / L .
`Fig. 2 shows a simulated impurity profile and isolation
`oxide shape of the n-MOSFET’s fabricated according to
`the PRORPS process. The channel width is 1.36 pm and
`the sidewall-implanted boron dose is 2.0 x lOI3 cm-2. At
`the top corner of the silicon the higher boron concentra-
`tion is formed by sidewall implantation. The simulated
`shape of the “bird’s beak” is underestimated because the
`simulation does not include an oxidation model for poly-
`silicon [9].
`
`IV. SURFACE n-CHANNEL MOSFET
`Fig. 3 compares the experimental data and simulated
`results of threshold voltage versus channel width for three
`kinds of trench-isolated n-MOSFET’s when the drain bias
`V, = 0.1 V and the substrate bias VSub = 0.0 V. As shown
`in Fig. 3, the simulated results give good agreement with
`the experimental data. As expected, the results show the
`inverse-narrow-width effect for the device without the bo-
`ron-implanted sidewalls and narrow-width effects that are
`related to the boron dose implanted in the sidewalls. The
`simulations were also performed with a fixed charge den-
`sity Q,, = 1.0 X 10” cmP2 and without Q,,
`at the inter-
`face of the trench-isolation oxide, respectively. The fixed
`
`Page 2 of 7
`
`

`

`1112
`
`EEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 36. NO. 6, JUNE 1989
`
`SIMULATION With Qox 1.0x10”cm~2 -
`-----
`
`0
`c
`
`L=0.88pm V D = O . ~ V
`
`THRESHOLD ADJUSTMENT IMPLANT
`
`4 . 0 ~ 1012 crn-2
`
`L = 0.88um
`
`’JG =Vth
`
`n
`7
`
`I-
`
`t, 1.5
`” 1.0
`E E
`3
`z
`2
`Y 0.5
`
`2 Y
`
`0’4
`
`0.5
`
`1.5
`
`0.0
`
`0.7 0.8 0.9 1.0
`0.4 0.5 0.6
`0.3
`0.1 0.2
`NORMALIZED CHANNEL WIDTH (pm)
`I
`Fig. 4. Electron current densities at 6 nm deep from the silicon surface.
`The sidewall boron dose is 2.0 x IO” cm-’. The channel widths are
`1 .o
`1.36, 0.63, and 0.46 p n , respectively
`CHANNEL WIDTH (pm)
`Fig. 3. Comparison between the experimental data and the simulations of
`the threshold voltage versus the channel width for three kinds of trench-
`isolated n-MOSFET’s.
`
`charge density Q,, at the interface of the trench sup-
`presses the narrow-width effect and, as Sugino er al. [2]
`pointed out, it enhances the inverse-narrow-width effect.
`For the n-MOSFET’s with boron-implanted sidewalls,
`this narrow-width effect constrains the scaling of the
`channel width.
`To understand the narrow-width effect shown in Fig. 3,
`we can see in Fig. 4 the simulated electron current dens-
`ities at a depth of 6 nm from the silicon surface versus the
`channel width normalized by the long-channel width of
`1.36 pm. The device channel widths are 1.36, 0.63, and
`0.46 pm, respectively. For these devices, the boron dose
`in the sidewalls is 2.0 X lOI3 cm-* and the oxide charge
`is 1.0 x 10” cm-2. In the case of the 1.36-pm channel
`width device, the edge current is suppressed by the doping
`gradient in the sidewalls. On the other hand, in the case
`of the 0.46-pm channel width device, it is found that the
`edge currents increased dramatically. This result implies
`that controllability by means of sidewall-implanted boron
`for suppressing the edge current is lost. The significant
`result is that the edge current is enhanced with the reduc-
`tion of the channel width although the corresponding re-
`sults in Fig. 3 show the narrow-width effect.
`To investigate this phenomenon, Fig. 5 shows the sim-
`ulated redistribution of boron to a depth of 6 nm from the
`silicon surface versus the normalized channel width for
`the same devices as considered in Fig. 4. The boron con-
`centration at the channel edge region is higher than that
`at the center of the channel for W = 1.36 pm. As the
`channel width is reduced, the boron implanted in the side-
`walls extends toward the center of the channel and, hence
`its concentration is gradually increased. Finally, the bo-
`ron concentration in the center of the channel becomes
`higher than that at the edge of the channel due to the de-
`pletion effects of the boron redistribution. Because of this
`
`-
`“
`6
`0 -
`E
`
`-
`
`4.0
`
`SIDEWALL IMPLANT
`2 . 0 ~ 1013cm-2 , 80 kev
`THRESHOLD ADJUSTMENT IMPLANT
`
`0.0
`
`0.4 0.5 0.6
`0.7
`0.1 0.2 0.3
`0.8 0.9
`NORMALIZED CHANNEL WIDTH
`Fig. 5. Simulated surface boron concentration versus the normalized chan-
`nel width for the devices in Fig. 4.
`
`1.0
`
`lateral diffusion of the sidewall boron into the narrow-
`channel region, the devices show the narrow-width effect
`while the edge current is enhanced. As a result, the scal-
`ing of the channel width depends on the width W, of the
`higher boron concentration region resulting from the side-
`wall implantation. To suppress the channel edge current,
`the boron concentration at the edge regions needs to be
`higher than that at the center region, and additionally the
`channel width should be roughly larger than twice WB.
`The channel edge current is affected by the shape of the
`top corner of the trench isolation, which depends on the
`planarization process. This means that the device char-
`acteristics are sensitive to variations in the fabrication
`process. Fig. 6(a)-(b) shows the comparison of sub-
`threshold characteristics and three-dimensional simula-
`tion results for devices with two kinds of comer shapes.
`The corner shapes used for simulation are schematically
`shown in Fig. 6(a). The planarization process mentioned
`in Section I1 forms the corner shape having rd > 0 be-
`
`Page 3 of 7
`
`

`

`OHE et u l . : NARROW-WIDTH EFFECTS O F SHALLOW TRENCH-ISOLATED CMOS
`
`1113
`
`0 A
`
`EXPERIMENTAL DATA
`SIMULATION With Qox 1 . 0 ~ 10"cm-2
`SIMULATION Without Qox
`_____________________ ---
`
`Without COUNTER DOPING
`
`- 1.1
`
`-1.0-
`
`+ 10-6
`5 10-7
`2 10-8
`a
`
`U
`
`EXPERIMENTAL DATA
`
`SIMULATION t d = - 2Onm
`
`BF2 DOSE 1 . 0 ~ 10'2cm-2
`
`BFz DOSE 1 . 7 ~ 10'2cm-2
`
`> -0.9 -
`UJ W $
`-0.8 -
`9
`3 -0.7 -
`0
`5
`F
`
`-0.6 -
`-0.5 - ~ = 0 . 8 8 p m
`-0.4 -
`
`VD = 0.1v
`
`-0.3 -
`-0.2 -
`
`-0.1,
`0.0
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`1
`
`5
`
`I
`I
`1 .o
`0.5
`CHANNEL WIDTH (pm)
`Fig. 7. V,,-Wcharacteristics of buried p-MOSFET's for the three kinds of
`threshold adjustmeentsSF, is implanted at 50 keV for the counter-dop-
`ing.
`
`V is applied, while for the 0.46-pm channel width device,
`as shown in Fig. 6(b), the dependence of the corner shape
`is enhanced by the backgate bias because the fringing field
`effect is enhanced as the backgate bias is reduced. This is
`consistent with the simulation results shown in Fig. 4
`where the edge current is enhanced in the 0.46-pm chan-
`nel width. Therefore, the devices that exhibit edge current
`are very sensitive to the top comer shape of the trench
`isolation. In trench-isolated MOSFET's, it is necessary to
`suppress this edge current. The present devices have been
`successfully fabricated down to channel widths of 0.65
`pm by PRORPS process technalogy, avoiding the nar-
`row-width effect.
`
`V. BURIED CHANNEL MOSFET
`The scaling of buried p-MOSFET's with trench isola-
`tion also requires study of the channel-width effect on
`threshold voltage. If the buried p-MOSFET's show the
`inverse narrow-width effect, it will be suppressed by
`n-type ions implanted into the sidewalls as well as the
`approach to the surface n-MOSFET's mentioned in Sec-
`tion IV. In the case of the narrow-width effect, p-type ions
`are needed. Unfortunately, the sidewall implantation with
`p-type ions cannot be applied to suppress the narrow-width
`effect because a parasitic p-channel field transistor is
`formed by such as-implant.
`
`'
`
`I
`1 5
`
`'
`
`2.0
`
`I
`
`I
`
`'
`
`'
`
`0.5
`
`/
`' 1
`
`10-11
`I '
`0 0
`
`I
`
`I
`
`I
`
`I
`
`' I
`
`I
`
`I
`
`1 .o
`GATE VOLTAGE (V)
`(b)
`Fig. 6. Subthreshold current characteristics of n-MOSFET's for two kinds
`of trench comer shapes. The deference of comer shapes is schematically
`shown in the cross sections. The t, is the distance from the surface of
`the gate oxide to the S O z surface of trench isolation. The solid lines
`show the drain current at t, = +20 nm and the dashed lines show at f,
`= -20 nm. These devices have a sidewall boron dose of 2.0 X lOI3
`cm-* and the backgate biases are Vsub = 0.0 and -2.0 V, respectively.
`The channel width is (a) 1.36 pm and (b) 0.46 pm.
`
`cause of the use of polysilicon as an etch stop. The ex-
`perimental data also show the drain current versus gate
`voltage characteristics of 1.36- and 0.46-pm channel
`width devices when the applied backgate biases are 0.0
`and -2.0 V, respective1 . These devices have a boron
`dose of 2.0 x lOI3 cm-'for
`the sidewall implantation.
`For the 1.36-pm channel width device, the n-MOSFET
`in Fig. 6(a) shows that the trench corner shape has little
`impact on the drain current when a backgate bias of -2.0
`
`Page 4 of 7
`
`

`

`1114
`
`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL 36. NO. 6 , JUNE 1989
`
`hl
`
`0 2 t
`
`/
`
`OXIDE BOTTOM
`
`- 0 6
`
`- 0 2
`
`0 0
`
`0 2
`
`0 4
`
`0 6
`
`0 8
`
`1 0
`
`-
`-0.1 -
`
`>
`
`OXIDE BOTTOM
`
`GATE OXIDE
`
`OXIDE,,’
`
`I
`
`I / ’
`
`I
`I
`I
`
`- 0.2
`
`1
`
`1
`
`1
`0.2
`
`1
`
`1
`
`l
`
`1
`0.8
`
`l
`
`
`
`1
`I
`0.4
`0.6
`DEPTH (pm)
`(b)
`Fig. 8. Two simulated possible situations of p-MOSFET’s at the threshold
`condition: (a) buried channel and (b) surface channel. The solid lines
`show the potential at the center of the channel and the dashed lines show
`the potential in the oxide.
`
`Fig. 7 demonstrates the experimental data and the three-
`dimensional simulation results of the threshold voltage
`versus channel width characteristics in the p-MOSFET’s.
`The drain bias is -0.1 V and the substrate bias is Vsub =
`0.0 V. These devices are simulated both with a Q,, of 1 .0
`x 10” cmP2 and without Q,, at the interface of the trench
`isolation, respectively. It is found that the buried p-MOS-
`FET’s show the narrow-width effect as the channel width
`is reduced. Although the simulation results give fairly
`good agreement with the experimental data, they under-
`estimate the narrow-width effect observed in the experi-
`mental data for channel widths less than 0.65 pm. This is
`because the narrow-width effect is enhanced by the slight
`“bird’s beak” at the edge of the channel width mentioned
`in Section 11. Moreover, at lower threshold voltages, the
`simulation results show a slight inverse-narrow-width ef-
`fect as shown in Fig. 7.
`To understand this phenomenon, we have analyzed two
`possible situations using the p-MOSFET’s with an n+-
`polysilicon gate and a Q,, of 1.0 x 10” cmp2 at thresh-
`
`- 0.7 1
`-0.8
`
`I
`-0.6
`
`II
`-0.4
`
`I W i
`rOUNTER
`_ -
`I
`0.4
`
`~
`
`t h o y
`DOPING
`
`I
`I
`I
`0.2
`0.0
`-0.2
`CHANNEL WIDTH (pm)
`Fig. 9. Potential distributions at the threshold conditions with Q,,, in the
`direction of the channel width for the four p-MOSFET’s used in Fig. 7.
`The potential at the channel position is along the A-B line in the sche-
`matic figure shown for the structure.
`
`I
`0.6
`
`_I
`0.8
`
`old. In Fig. 8(a) and (b), the solid lines indicate the po-
`tential at the center of the channel, and the dashed lines
`indicate the potential in the oxide region of the trench iso-
`lation. In this work, the potential is measured from the
`intrinsic Fermi level in the bulk silicon. The simulation
`result shown in Fig. 8(a) corresponds to the experimental
`data of the device with a threshold voltage of about -0.2
`V as used in Fig. 7. Fig. 8(b) shows the simulation result
`for the device without the counter-doping. As Shigyo and
`Dang [6] pointed out, the fringing field effect is estimated
`by the difference of the potential between the channel and
`the oxide regions. In the buried p-MOSFET’s shown in
`Fig. 8(a), the fringing field pulls up the potential at the
`channel edge region and the device shows the narrow-
`width effect. This is consistent with the experimental data
`shown in Fig. 7. On the other hand, the result in Fig. 8(b)
`shows that the device is in the surface-channel mode at
`the threshold condition of V,, < -1.16 V . This result
`illustrates that the surface p-MOSFET shows an inverse-
`narrow-width effect, as already pointed out in the pre-
`vious work [4]. This difference of the structural effects
`between buried and surface conduction mechanisms has
`not been considered in previous studies of trench-isolated
`p-MOSFET’s.
`The conduction mechanism of
`the p-MOSFET’s
`changes from the buried-channel mode to the surface-
`channel mode by reducing the BF2 dose use for the
`counter-doping. The transition between the surface- and
`buried-channel modes is approximately determined by the
`
`Page 5 of 7
`
`

`

`OHE ef al.: NARROW-WIDTH EFFECTS OF SHALLOW TRENCH-ISOLATED CMOS
`
`1 1 15
`
`threshold voltage, which does not lead to a voltage drop
`over the gate oxide. This can be written as
`
`where \E,,, is the minimum potential in the channel at the
`threshold condition, VFB is the flat-band voltage, and
`is the built-in potential of the n-well. \km = -0.42 V,
`VFB - @ E = 0.55 V, and then V,, = -0.97 V.
`Moreover, the results shown in Fig. 7 indicate that the
`narrow-width effect depends on the threshold voltage. As
`shown in Fig. 9, this is explained by the potential distri-
`butions in the channel at the threshold conditions for the
`four p-MOSFET’s used in Fig. 7. In Fig. 9, the lateral
`and vertical axes show the channel width and the potential
`in the channel along the A-B line. The fixed charge dens-
`ities at the interface of the trench isolation slightly pull
`up the potential at the interface. As the BF2 dose of the
`counter-doping is increased, the potential in the isolation
`oxide becomes high, which enhances the fringing field ef-
`fect. As a result, the narrow-width effect is enhanced with
`the increase of the threshold voltage. The somewhat low
`threshold voltage of -0.97 V can be used to avoid this
`narrow-width effect for trench isolation.
`VI. CONCLUSIONS
`The threshold behavior of the trench-isolated surface
`n- and buried p-MOSFET’s with n+-polysilicon gate has
`been characterized using the experimental data down to a
`channel width of 0.5 pm with the PRORPS process.
`Three-dimensional proceddevice integrated simulations
`have been used to model and explain the results. For
`n-MOSFET’s, it is found that the lateral diffusion of the
`boron implanted in the sidewalls induces an enhancement
`of the edge current although the devices show narrow-
`width effects. The n-MOSFET’s are successfully fabri-
`cated down to a channel width of 0.65 pm suppressing
`the edge current.
`The p-MOSFET’s show the narrow-width effect under
`buried-channel conditions and the inverse-narrow-width
`effect for the surface channel case, depending on the
`threshold conditions. Simulation has clarified that the nar-
`row-width effect of the buried p-MOSFET strongly de-
`pends on the threshold adjustment set by the counter-dop-
`ing. For submicrometer channel width devices, the
`somewhat low threshold voltage of -0.97 V can be
`adopted to avoid the narrow-width effect on threshold re-
`sulting from trench isolation without an additional side-
`wall implantation.
`
`ACKNOWLEDGMENT
`The authors wish to thank Dr. H. Mizuno, T. Ishihara,
`Dr. T. Takemoto, and H. Esaki for their encouragement.
`They also wish to thank Dr. T. Ohzone for his useful dis-
`cussions. Special thanks go to Prof. R. W. Dutton of
`Stanford University for critical reading of the manuscript.
`REFERENCES
`[I] N. Shigyo and R. Dang, “Analysis of inverse narrow-channel effect
`. .
`based on a three-dimensional simulation.” in Dip. Tech. Paaers Svma.
`‘
`VLSI Tech., Sept. 1982, pp. 54-55.
`
`M. Sugino and L. A. Akers, “Subthreshold current in oxide isolated
`structures,” IEEE Electron Device Lett., vol. EDL-4, pp. 114-1 15,
`Apr. 1983.
`M. Sugino, and L. A. Akers, and J. M. Ford, “Optimum p-channel
`isolation structure for CMOS,” IEEE Trans. Elerrron Devices, vol.
`ED-31, pp. 1823-1829, Dec. 1984.
`L. A. Akers, M. Sugino, and J . M. Ford, “Characterization of the
`inverse-narrow-width effect,” IEEE Trans. Electron Devices, vol.
`ED-34, pp. 2476-2484, Dec. 1987.
`T . Shibata et al., “A simplified BOX (buried-oxide) isolation tech-
`nology for megabit dynamic memories,” in IEDM Dig. Tech., 1983,
`pp. 27-30.
`N. Shigyo and R. Dang, “Analysis of an anomalous subthreshold
`current in a fully recessed oxide MOSFET using a three-dimensional
`device simulator,” IEEE Trans. Electron Devices, vol. ED-32, pp.
`441-445, Feb. 1985.
`G. Fuse et al., “A new isolation method with boron-implanted side-
`walls for controlling narrow-width effect,” IEEE Trans. Electron De-
`vices, vol. ED-34, pp. 356-360, Feb. 1987.
`S. Odanaka et al., “SMART: Three-dimensional process/device sim-
`ulator integrated on a super-computer.” in ISCAS Proc., vol. 2, 1987.
`pp. 534-531.
`S. Odanaka, H. Umimoto, M. Wakabayashi, and H. Esaki, “SMART-
`P: Rigorous three-dimensional process simulator on a supercompu-
`ter,” IEEE Trans. Computer-Aided Design, vol. 7 , pp. 675-683. June
`1988.
`G. Fuse et al., “A practical trench isolation technology with a novel
`planarization process,” in IEDM Tech. Dig., 1987, pp. 732-735.
`S. Odanaka et al., “A new half-micrometer p-channel MOSFET with
`efficient punchthrough stops,” IEEE Trans. Electron Devices, vol.
`ED-33, pp. 317-321, Mar. 1986.
`*
`
`Kikuyo Ohe was born in Osaka, Japan, on May
`14, 1963. She received the B.S. degree in physics
`from Nara Women’s University, Nara, Japan, in
`1986.
`In 1986, she joined the Semiconductor Re-
`search Center, Matsushita Electric Industrial Co.,
`Ltd., Osaka, Japan. She has been working on pro-
`ceddevice simulation.
`
`*
`
`Shinji Odanaka was born in Nagoya, Japan, on
`February 19, 1955. He received the B S. and M S
`degrees in applied mathematics and physics from
`Kyoto University, Kyoto, Japan, i n 1978 and
`1980, respectively.
`In 1980, he joined the Semiconductor Research
`Center, Matsushita Electric Industrial Co., Ltd.,
`Osaka, Japan. He has been working on CMOS de-
`vice modeling, simulation and design He has also
`developed a three-dimensional process device
`simulator on a supercomputer He is currently re-
`sponsible for submicrometer VLSI process/device modeling and simula-
`tion
`
`Kaori Moriyama was born in Nagoya, Japan, on
`August 17, 1963. She received the B.S. degree in
`mathematics from Osaka Women’s University,
`Osaka, Japan, in 1986.
`In 1986, she joined the Semiconductor Re-
`search Center, Matsushita Electric Industrial Co.,
`Ltd., Osaka, Japan. She has been working on pro-
`cess/device simulation.
`
`Page 6 of 7
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`IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 36, NO. 6. JUNE 1989
`
`Takashi Hori (M’87) was born in Japan on March
`13, 1956. He received the B.S. and M.S. degrees
`in metal science from Kyoto University, Kyoto,
`Japan, in 1979 and 1981, respectively. He is cur-
`rently working toward the Ph.D. degree in elec-
`trical engineering.
`In 1981, he joined the Basic Research Labo-
`ratory, Semiconductor Research Center, Matsush-
`ita Electric Industrial Co., Ltd., Osaka, Japan. In
`addition to his doctoral research, he is now en-
`gaged in research on the scaling and physics of
`submicrometer MOS devices and the development of ultrathin-gate insu-
`lator processing for ULSI’s. He is also responsible for the design and de-
`velopment of MOSFET’s for microprocessors and DRAM’S.
`
`Genshu Fuse received the B.E. and the M.E. de-
`grees in electrical engineering from Okayama
`University, Japan, in 1975 and 1977, respec-
`tively.
`In 1977, he joined the Semiconductor Research
`Center, Matsushita Electric Industrial Co., Ltd.,
`Osaka, Japan, where he has been working on ap-
`plications of ion implantation to semiconductor
`device development and on the development of
`MOS memory processing.
`
`Page 7 of 7
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