.
`
`United States Patent [191
`Ehrlich
`
`llllllllilllllIIIIllllllllllllllllllllll?lllllllllllllllllllllllllllllllll
`[11] Patent Number:
`5,310,624
`[45] Date of Patent: May 10, 1994
`
`US005310624A
`
`[54] INTEGRATED CIRCUIT
`MICRO-FABRICATION USING DRY
`LITHOGRAPHIC PROCESSES
`[75] Inventor: Daniel J. Ehrlich, Lexington, Mass.
`[73] Assignee: Massachusetts Institute of
`Technology, Cambridge, Mass.
`[21] Appl. No.: 924,374
`[22] Filed:
`Jul. 31, 1992
`
`[63]
`
`Related US. Application Data
`I
`Continuation of Ser. No. 517,394, Apr. 27, 1990, aban
`doned, which is a continuation of Ser. No. 149,426,
`Jan. 29, 1988, abandoned.
`
`[51] Int. Cl.5 .............................................. .. G03C 5/00
`[52] US. Cl. .................................. .. 430/322; 430/297;
`430/311; 430/945
`[58] Field of Search ............. .. 430/297, 311, 945, 322;
`427/450, 452, 455, 322
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`Re. 32,033 11/1985 Moreland ct al. ..
`3,959,105 6/1976 Feneberg et a1. ..
`4,170,662 10/ 1979 Weiss et a1. . . . . .
`
`430/311
`204/165
`. . . . . .. 427/38
`
`4,178,097 12/1979 Sara . . . . . . . . . . . . .
`
`. . . .. 355/110
`
`4,179,312 12/1979 Keller et a1. . . . .
`
`. . . . .. 148/1.5
`
`4,260,649 4/1981 Dension et al.
`
`427/531
`
`4,283,482 8/1981 l-lattori et al. . . . . . .
`
`. . . .. 430/296
`
`4,340,617 7/1982 Deutsch et a1.
`
`427/531
`
`. . . .. 430/296
`4,348,473 9/1982 Okumura et al. . . . . . .
`427/531
`4,359,485 11/1982 Donnelly et al. .... ..
`4,444,456 4/1984 Jain et al. ................... .. 350/3.7
`4,458,994 7/1984 Jain et a1.
`....... .. 354/4
`4,490,211 12/1984 Chen et a1. .
`156/643
`
`4,516,832 5/1985 Jain et a1. . . . . . . .
`
`. . . . . .. 350/96
`
`4,521,087 6/1985 Hayes et al.
`
`350/574
`
`4,549,064 10/1985 Del?no . . . . . . . . . .
`
`. . . .. 219/121
`
`4,560,641 12/1985 Kokaku et a1. . . . .
`
`. . . .. 430/312
`
`. . . .. 430/322
`4,568,632 2/1986 Blum et al. . . . . . . . . .
`. 156/610
`4,608,117 8/1986 Ehrlich et al.
`427/38
`4,615,904 10/1986 Ehrlich et a1.
`430/942
`4,619,894 10/1986 Bozler et a1. ..... ..
`156/635
`4,622,095 11/1986 Grobman ct a1. ..
`427/ 53.1
`4,626,449 12/ 1986 Hirai et a1. ....... ..
`355/53
`4,653,903 3/1987 Torigoe et a1.
`4,698,238 10/1987 Hayasaka et al. ................ .. 427/531
`
`FOREIGN PATENT DOCUMENTS
`
`0066053 8/1982 European Pat. Off. .
`0111655 3/1984 European Pat. Off. .
`0178654 4/ 1985 European Pat. Off. .
`2153543A 8/1985 United Kingdom .
`
`OTHER PUBLICATIONS
`Cali et al., (1976), Applied Optics, vol. 15, No.
`5:1327-1330.
`Ehrlich et al., (1981), Appl. Phys. Lett. 38(11), vol. 38,
`No. 11:946-948.
`Deutsch et al., (1979), Appl. Phys. Lett. 35(2) vol. 35,
`No. 2:175-177.
`Hanabusa etal., (1979), Appl. Phys. Lett. 35(8), v01. 35,
`No. 8:626-627.
`Andreatta et al., (1982), J. Vac. Sci. Technol, 20(3),
`740-742.
`Ehrlich et a1, (1985), J. Vac. Sci. Technol, vol. B 3(1),
`No. 1, pp. 1-8.
`Beatty, “Thin Films” in Handbook of Materials, Har
`per, ed., McGraw-Hill, Inc., 1970, pp. (11-1)-(11-19).
`Dr. Rothschild et al., “Attainment of 0.13 micron lines
`.
`.
`. ”, J. Vac. Sci. T echnolog vol. B(5) (1), pp. 389-390
`(1987).
`Rothschild, et al., “Excimer-laser etching of diamond
`and hard carbon ?lms by direct writing and optical
`projection”, vol. B4, No. l, J. Vac. Sci. Technol, pp.
`310-314 (1986).
`Primary Examiner-Thori Chea
`Attorney, Agent, or Firm-Thomas J. Engellenner; John
`V. Bianco
`[57]
`Dry, laser-based, lithographic techniques and systems
`for patterning a surface of a wafer or other substrate are
`disclosed. The techniques and systems are particularly
`adapted for automated micro-fabrication of integrated
`circuits on semiconductor wafers. The invention entails
`dry depositing a resist material on a surface of a sub
`strate, then generating a pattern in the resist material by
`selectively exposing the resist material to pulsed UV
`laser radiation, controlling the ambient exposure of the
`resist material between the resist-depositing and pat
`tern-generating steps, and, ?nally, transferring the pat
`tern from the resist to the substrate or otherwise em
`ploying the pattern to transform the substrate by deposi
`tion or implantation of materials.
`3 Claims, 4 Drawing Sheets
`
`Page 1 of 12
`
`IP Bridge Exhibit 2018
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`May 10, 1994
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`May 10, 1994
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`US. Patent
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`May 10, 1994
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`Page 5 of 12
`
`

`

`1
`
`INTEGRATED CIRCUIT MICRO-FABRICATION
`USING DRY LITHOGRAPHIC PROCESSES
`
`The United States Government has rights in this
`invention pursuant to the Department of Air Force
`Contract No. Fl9628-85-C-0002.
`This application is a continuation of application Ser.
`No. 07/514,394, ?led Apr. 27, 1990, now abandoned
`which is a continuation of application Ser. No.
`07/149,426, ?led Jan. 29, 1988, now abandoned.
`
`30
`
`20
`
`5,310,624
`2
`The use of conventional wet deposition and develop
`ing solutions is a major source of contamination and,
`consequently, defects in the fabrication of integrated
`circuits because such wet processing steps typically
`involve breaks in vacuum or controlled-ambient condi
`tions. Whenever this occurs, the surfaces of the wafer
`can begin to oxidize in the air or become exposed to
`airborne chemical and particulate contamination. As a
`result, the wafer surfaces often must be cleaned and
`dried before the next processing step can commence.
`The deposition, development, cleaning and drying op
`erations typically are time-consuming and reduce the
`through-put of the overall fabrication process. More
`over, the liquid solvents, themselves, can also be major
`sources of active corrosion or chemical contamination
`and thereby contribute further defects to the circuit or
`adversely affect dimensional control.
`Another major source of contamination during inte
`grated circuit fabrication is introduced by human opera
`tors working in the manufacturing clean room. Human
`operators are presently required in the clean room, for
`example, for process set-up and monitoring and transfer
`of wafers between process stations. It has been esti
`mated that an operator making only light hand and arm
`movements sheds approximately 6000 particles per min
`ute of a size equal to or larger than 0.3 microns. Success
`ful wafer fabrication can not allow even one such parti
`cle per square centimeter to accumulate on the wafer
`over the processing cycle which can last several weeks.
`At present, the problem of human contamination of
`wafers during processing is addressed largely by protec
`tive garments and air ?ltration technology.
`It is an object of the invention to provide improved
`processes and systems for pattern formation on inte
`grated circuit wafers.
`It is a further object of the invention to provide sim
`pler processes and systems for patterning such wafers
`while exposing the wafers to a reduced level of contam
`inants and while limiting the interaction of humans
`during processing.
`It is yet another object of the invention to provide
`more ?exible, economic and automated processes and
`systems for patterning wafers with high resolution.
`
`BACKGROUND OF THE INVENTION
`This invention generally relates to micro-fabrication
`of integrated circuits and, particularly, to an improved
`process and apparatus for pattern formation on semi
`conductor wafers to form such circuits.
`Within the semiconductor industry, production of
`electronic circuits by very large scale integration
`(“VLSI”) techniques is constrained by a variety of fac
`tors which limit yield and inhibit process ?exibility.
`These detrimental factors include, for example, the
`exposure of wafers to contaminants and/or oxidation
`during fabrication. Such processing constraints ad
`versely affect mass production of integrated circuits. In
`addition, conventional processes are slow and inordi
`nately expensive for the fabrication of low-volume
`products, thus posing an impediment to new device and
`circuit designs.
`Processes for micro-texturing and patterning semi
`conductor wafers typically rely on lithographic transfer
`of the desired image from a thin-?lm of radiation-sensi
`tive resist material. The process entails the formation of
`a sacri?cial layer, the “resist”, which is photo-litho
`35
`graphically patterned.
`The patterning of the resist involves several steps,
`including exposing the resist to a selected light source
`through a suitable mask to record a latent image of the
`mask and then developing‘and removing selected re
`gions of the resist. For a “positive” resist, the exposed
`regions are removed; while for a “negative” resist, the
`unexposed regions are removed.
`For example, in conventional processes using a de
`posited polymeric resist, the ?lm is exposed with visible
`or near UV light, electrons or x-rays to induce chain
`sission (in the case of a positive resist) or cross-linking
`(in a negative resist) of the polymeric resist material,
`followed by development in an organic solvent. The
`pattern can be transferred into surface texture in the
`wafer by etching with a reactive gas using the patterned
`resist as a protective masking layer. Alternatively, when
`a wafer is “masked” by the resist pattern, it can be pro
`cessed to form active electronic devices and circuits by
`deprsiting conductive or semiconductive materials or
`implanting dopants into etched wells and other surface
`structures.
`Conventional micro-fabrication processes require a
`number of wet processing steps. For example, there is a
`general trend towards the use of organic polymer mate
`rials as resists, such as Novolack resins, polyesters, or
`polyimides. These materials are typically spun cast onto
`the wafer as a thin film (e.g., about 0.1 to 3.0 microns
`thick) from a wet polymeric solution, such as mono
`ethyl ether or chlorobenzene. In addition, the develop
`ment steps (in which regions of the resist are removed)
`typically involve treating the exposed ?lm with another
`liquid solvent.
`
`45
`
`50
`
`55
`
`SUMMARY OF THE INVENTION
`The invention encompasses dry, laser-based, litho
`graphic exposure/development techniques and systems
`for patterning a surface of a wafer or other substrate.
`All-dry patterning processes are disclosed which avoid
`exposure of the substrate to liquid solvents and/or air,
`as well as reduce (or eliminate) human operators as a
`source of contaminants.
`The invention entails dry depositing a resist material
`on a surface of a substrate, then generating a pattern in
`the resist material by selectively exposing the resist
`material to pulsed UV laser radiation, controlling the
`ambient exposure of the resist material between the
`resist-depositing and pattern-generating steps, and, f1
`nally, transferring the pattern from the resist to the
`surface of the substrate or otherwise employing the
`pattern to transform the substrate by deposition or im
`plantation of materials.
`Preferably the above-described steps are accom
`plished in a single-enclosure, automated, integrated-cir
`cuit micro-fabricating apparatus having a plurality of
`processing stations or modules through which wafers
`are transported during processing and along which the
`wafers remain in a controlled ambient. For processing,
`
`65
`
`Page 6 of 12
`
`

`

`5,310,624
`
`4
`BRIEF DESCRIPTION OF THE DRAWINGS
`For a fuller understanding of the features, advantages
`and objects of the invention, reference should be made
`to the following detailed description and the accompa
`nying drawings, in which;
`FIG. 1 is a partial schematic representation of an
`integrated circuit, micro-fabricating machine showing
`photo-lithographic resist processing modules or stations
`in accordance with the invention;
`FIG. 2 is a schematic representation of one embodi
`ment of the photo-lithographic resist application mod
`ule of FIG. 1;
`FIG. 3 is a schematic representation of one embodi
`ment of the photo-lithographic resist exposure module
`of FIG. 1;
`FIG. 4 is a schematic representation of one embodi
`ment of the photo-lithographic resist developer module
`of FIG. 1;
`FIG. 5 is a schematic representation of one embodi
`ment of the photo-lithographic-resist etching module of
`FIG. 1;
`FIGS. 6A through 6E, inclusive, are schematic repre
`sentations in cross-section of a wafer during various
`processing steps in accordance with the invention;
`FIG. 7 is a diagrammatic representation of a process
`flow con?guration for micro-fabrication of a wafer in
`accordance with the invention.
`
`25
`
`35
`
`3
`the wafers are introduced preferably on a continuous
`feed basis into a main trunk or bus through an entry/ exit
`port constituting an air lock or vapor seal. The wafers
`are carried by a transport to one of many processing
`lines connected to the main bus to receive the wafers.
`The wafers enter the processing line through another
`air lock arrangement, utilizing, for example, a “smart”
`gate valve. The processing line preferably includes a
`series of chambers interlocked in airtight fashion to
`receive the wafers carried by the transport. The cham
`bers constitute modules or stations in which wafers are
`processed. For example, a ?rst chamber serves as a
`holding station for wafer queuing. In a second one, a
`resist material is applied by a dry deposition technique.
`The term “dry” as used herein is meant to denote the
`absence on exposure to, or use of, liquid solutions or
`solvents. In a third chamber, the resist is exposed to
`pulsed laser radiation, preferably from an excimer laser.
`The radiation exposure creates either a physical or la
`tent pattern in the resist. A physical pattern is one
`which entails a macro-structural change in the topogra
`phy or morphology of the resist. Where the exposure
`produces a physical pattern, it can be referred to as a
`self-developing resist process. A latent pattern is one
`which entails micro-structural or chemical modi?cation
`of regions of the resist. Subsequent processing of the
`wafer in yet another chamber can develop the latent
`pattern into a physical one.
`-
`Once the resist is patterned in the aforedescribed
`processing line, the wafer can be returned by the trans
`port to the main bus where it is routed to other process
`ing line in automated fashion pursuant to a predeter
`mined program and as directed by a controller.
`In a second processing line, for example, the resist
`pattern can be used to create a surface relief pattern on
`the wafer by dry etching or the like. Then the remaining
`resist is removed at a stripping station.
`Still other processing lines have stations for deposi
`tion, ion implantation, cleaning, etc. These other pro
`cesses are well known, and, in and of themselves, are
`not part of the present invention. However, impor
`tantly, these other processes can be Performed within
`the single-enclosure, controlled-ambient of the micro
`fabrication apparatus described herein.
`The invention embraces both the aforedescribed pro
`cess and apparatus for lithographically forming patterns
`in wafers and other substrates, as well as devices made
`thereby. The technique allows the elimination of expo
`sure to air, liquid solutions and solvents, and invasive
`human presence during Processing with a resulting
`reduction in contamination and, consequently, defect
`density in the wafer. Elimination of wet solutions and
`solvents also reduces the number of processing steps by
`rendering unnecessary such conventional processing
`steps as wet resist deposition, wet development, pre
`baking, and post-baking. Since the technique is auto
`mated, improved ?exibility is achieved. Furthermore,
`with the use of U.V. lasers during the exposure step,
`high-resolution and improved through-put can be
`achieved. With self-developing resists, a signi?cant
`reduction is realizable in the number of wafer-handling
`steps otherwise performed for resist development. The
`technique offers improved effective yield and, with in
`situ monitoring, improved quality control, while simpli
`fying and reducing the cost of micro-fabricating inte
`grated circuits.
`
`DETAILED DESCRIPTION
`The invention shall now be described with reference
`to the drawings in which like reference numbers desig
`nate similar features.
`FIG. 1 illustrates diagramatically a photolithographic
`system for use in the micro-fabrication of integrated
`circuits, and particularly in forming a pattern on a sur'
`face of a wafer or other substrate. In accordance with
`the present invention, FIG. 1 illustrates a single-enclo
`sure, automated, integrated circuit micro-fabricating
`apparatus 10 having a plurality of processing lines 12A,
`12B, 12C operationally interconnected by a main trunk
`or bus 18. Each of the processing lines 12A, 12B and
`12C includes at least one module or station at which one
`or more processing steps is carried out. The modules are
`generally designated by the numeral 14, followed by a
`letter to distinguish one from another. The illustrated
`apparatus 10 is but one exemplary con?guration for
`such a machine; other practical con?gurations will be
`apparent from the following description to one skilled
`in the art.
`The atmosphere within the main bus 18 is regulated
`by means of a gas source 20. In one preferred embodi~
`ment, the gas source 20 can operate to achieve a vac
`uum of 10"8 to 10-10 for gallium arsenide or 10-5 to
`10-7 Torr for silicon, or an inert gas with a water-free
`vapor such as nitrogen or argon at 100 to 1000 Torr.
`A transport 30 such as a track system or conveyor
`' belt arrangement extends along the main bus 18 in a
`loop fashion and branches into each of the processing
`lines, again in loop fashion. The transport is adapted to
`carry the wafers 16 at predetermined positions spaced
`from one another as directed by a controller 4-0.
`For processing, the wafers are introduced preferably
`on a continuous-feed basis into the main bus 18 through
`an entry/exit port 42 constituting a air lock or vapor
`seal such as a lip-seal arrangement. Once within the
`apparatus 10, the wafers are carried by the transport 30
`to one or more processing lines 12A, 12B, 12C in suc
`
`50
`
`55
`
`65
`
`Page 7 of 12
`
`

`

`.
`5
`cession or in any order programmed by the controller
`40. Additionally, the controller 40 can direct transport
`30 to carry speci?ed wafers to or from other Processing
`stations not shown in FIG. 1, such as for deposition,’ for
`implantation, for cleaning, etc.
`The illustrated processing lines 12A, 12B and 12C are
`used in photo-lithographically patterning the wafer.
`Each of the modules 14A through 14J inclusive in
`cludes an airtight chamber having at least one en
`try/exit port in the form of an air lock arrangement 50,
`utilizing, for example, a “sma ” gate valve. The
`“smart” gate can incorporate appropriate sensors and
`markers for keeping track of wafers during processing. _
`For example, bar codes or the like can be printed on the
`wafers and read by a detector at the “smart” gate to
`determine which wafers require processing at the mod
`ule to which the gate is attached. In the illustrated appa
`ratus 10, wafers can be directed to and from any of the
`modules 14A through 14] in any of the processing lines
`12A, 12B, 12C, passing by or through any intervening
`modules interposed between the main bus 18 and the
`desired module.
`The illustrated resist preparation line 12A includes
`several processing stations: The wafer queuing station
`14A is a holding station in which the transport 30 main
`tains the wafers on an endless or decoupled loop or
`other known arrangement until further processing is
`timely. The resist application module 14B applies the
`resist to the wafer. The resist exposure module 140
`laser patterns the resist. The optional resist developer
`module 14D converts latent patterns to physical pat
`terns when the resist exposure module 14C generates
`the former.
`~
`FIG. 2 is a more detailed, schematic representation of 35
`a resist application module such as module 14B of FIG.
`1 showing an exemplary embodiment—that of a ther
`mal/photo chemical vapor deposition (“CVD”) appara
`tus 100. CVD apparatus 100 is used to deposit resist ?lm
`from reactive vapor at room temperature with or with
`out illumination of actinic light.
`As shown, CVD apparatus 100 includes a vessel or
`chamber 102 having at each end an entry or exit port
`constituting a smart gate 104. The smart gate 104 has
`one or more sliding doors 106 for admitting or discharg
`ing the wafer carried on transport 30, and for closing
`and sealing off the chamber 102 so as to render it gas
`tight. Along one wall of the chamber is a window 108
`which is transparent to light emitted by an externally
`mounted lamp source 110. The lamp source 110 is, for
`example, a low-pressure mercury lamp operated at
`room temperature. Vaived gas inlet and outlet conduits
`112, 114 are connected with the chamber 102 to control
`the atmosphere therein. A pressure monitor or gauge
`116 is also provided.
`One typical application of the CVD apparatus 100 is
`for polymethyl methacrylate (PMMA) deposition. The
`wafer is carried into the chamber 102 by transport 30,
`and positioned by chuck 20 in alignment with heat con
`troller 22, the window 108 and lamp source 110. After
`60
`purging and flushing the atmosphere with the chamber
`102, methyl methacrylate vapor is introduced into the
`chamber 102 through inlet conduit 112 until it reaches 1
`to 10 Torr pressure, followed by Cd(CH3)2 vapor until
`the pressure gauge 112 reads 0.1 to 1.0 Torr. The latter
`gas serves as a catalyst. Flood illumination of the wafer
`by the lamp source 110 (approximately (W/cmZ, 254
`nm light) yields the PMMA deposition.
`
`5,310,624
`6
`In an analogous manner CVD apparatus 100 can be
`used to deposit other resist materials. For example,
`amorphous silicon can be deposited on a heated sub
`strate, with or without illumination when the chamber
`is ?lled with a silane or disilane gas.
`The resist application module 14B need not be a
`CVD apparatus since other suitable deposition tech
`niques are known in the art. Plasma deposition or elec
`tron-beam or ion-beam reactive depositions can be sub
`stituted, using known apparatus. In these techniques, a
`resist ?lm is deposited from a plasma or by similar elec
`tron-beam or ion-beam-induced reaction of a vapor.
`Also, “remote plasma” techniques, in which plasma and
`vapor are mixed in downstream flow, can be substi
`tuted. Using such techniques hard carbon resists can be
`formed by ion-beam or RF plasma-induced decomposi
`tions of butane or hydrocarbon vapors, and amorphous
`silicon resists can be deposited from silane by RF plas
`ma-induced decomposition.
`Still another alternative technique is to form the resist
`layer by sputter deposition/ evaporation. In these tech
`niques the physical deposition is achieved by transport
`of ions or molecules of the resist material from a sacri?
`cial target. In sputtering, an electron-beam or ion-beam
`is directed onto the target to bombard and eject mate
`rial. The resulting sputtering ions or molecules emitted
`from the material impinge upon the substrate or wafer,
`causing a ?lm to build up. In evaporation deposition,
`the target is heated to evaporate molecules; the evapo
`rant then strikes and builds up on the substrate. In one
`conventional practice of such methods, S102 is sputter
`deposited from a solid target or aluminum is deposited
`by “evaporation.” In the latter practice, the wafer is
`placed in an evacuated vessel, an electron beam is di
`rected toward a target of aluminum metal to heat it to
`its vaporization point. The aluminum vapor then con
`denses on the wafer.
`In FIG. 3, a representative embodiment of the resist
`exposure module 14C of FIG. 1 is illustrated. In accor
`dance with the invention, a pulsed UV laser apparatus
`150 is used. The apparatus 150 includes a vessel or
`chamber 152 generally similar to chamber 102 described
`above, having smart gates 154, window 156 and inlet
`and outlet valved conduits 158, 160.
`Additionally, the apparatus 150 includes a Pulsed UV
`laser 170 (e. g., commercially available ArF, KrF,
`XeClz or F2 excimer lasers) for emitting a laser beam
`through the window 156 and to the wafer carefully
`positioned thereunder. Because of their high resolution
`capability, excimer lasers, operating in the range of
`about 145 nanometers to about 350 nanometers, are
`preferred. While an excimer laser is preferred, a contin
`uous wave (CW) or solid state pulsed laser can also be
`used. The arrangement can be operated in a “projec
`tion” mode as illustrated, or in a scanned “direct write”
`mode which does not require an intermediate optical
`V mask to direct the laser beam. In most instances, the
`Projection mode is preferred since it produces a par
`tially coherent, non-gaussian beam characterized by
`reduced optical spreading and speckle noise. More spe
`ci?cally, in the illustrated arrangement, the laser beam
`emerging from the laser 170 passes through a mask
`element arrangement 172 preferably provided with an
`automatic mask loader/changer 173, a multi-elernent
`demagnifying lens arrangement 174 (e.g., Schwartz
`schild imaging system) preferably with automatic focus
`ing, through the window 156 and to a selected region of
`the wafer. The selected region of the wafer is micro
`
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`must be converted or transformed into physical pat
`positioned under the beam by a stepper stage 176, for
`terns. For positive resists, this is achieved in the resist
`example, an X-Y' table, which selectively moves the
`developer module 14D by any of a variety of tech
`wafer as it is held by means of chuck 178. A controller
`niques, including further laser-induced etching, Reac
`180 regulates the movement of the stepper stage 176 as
`tive Ion Etching (“RIE”), Remote Plasma Etching
`well as the operation of the laser 170, and preferably
`(“RPE”), Magnatron Etching, Electron-Cyclotron
`provides for automatic alignment and overlay control.
`Resonance Etching, Plasma Etching, or Ion-Beam
`The apparatus 150 can be used in a variety of different
`Assisted Etching. For negative resists, the process typi
`ways, including laser ablation, laser-assisted etching and
`cally involves chemical or thermal hardening of the
`solid state conversion, each of which can enable all dry
`exposed pattern regions, followed by etching of the
`patterning to be implemented.
`unexposed regions as described above.
`Laser ablation and laser-assisted etching essentially
`FIG. 4 shows a representative embodiment of the
`involve the vaporization or erosion of resist material. It
`resist developer module 14D employing an ion-beam
`is used for positive, physical patterning of the resist.
`assisted etching technique. The illustrated apparatus 200
`Suitable materials for laser ablation include, for exam
`ple, AZ 1350] polymer photo-resist (Shipley Mfg. 00.,
`includes a vessel or chamber 202 similar to chamber
`102, including smart gates 204, and valved gas inlet and
`Newton, Mass), polyirnides, PMMA, chromium, car
`outlet conduits 206, 208, water chuck 220, and a Kauf
`bon, diamond, pyrex and alumina cermets.
`man ion source 210 positioned over the wafer. The
`In the case of AZ polymer, the resist material can be
`Kaufman ion source produces a ?ood of moderately
`deposited onto the substrate by sputtering or the like,
`energized ions (on the order of about 0.3 to about 5
`and then ablated/etched by laser irradiation, preferra
`keV), such as Ar+ions, by passing an ionizable gas 214
`bly in a reactive atmosphere. For example, a polymer
`through an electrically charged grid 216 and directing
`coated wafer is placed in chamber 152, after purging
`the resulting ions onto the coated wafer. At the same
`and flushing the chamber 152, oxygen vapor is intro
`time C12 vapor is introduced by jet nozzle 212 of inlet
`duced via inlet conduit 158 to 100 Torr of pressure and
`conduit 206. The ion beam excites chlorine atoms ad
`a selected region of the wafer is then exposed to 20
`25
`sorbed on the surface of the resist and induced aniso
`ns-long pulses of 193 nm wavelength light from an ArF
`tropic etching of the previously exposed regions of the
`excimer laser at 170 mJ/cm2 density.
`resist (in the case of positive resists) or the unexposed
`Similarly, inorganic materials such as chromium can
`regions (in the case of negative resists). Such an ar
`be deposited by electron beam evaporation or sputter
`rangement ?nds particular utility with solid-transforma
`ing, and then laser-ablated or etched by laser irradiation
`tion resists.
`in a reactive atmosphere. For example, a chromium
`Alternatively, an RIE apparatus can be used to de
`coated wafer can be introduced into chamber 102 of
`velop the resist. For example, the irradiated polymer
`FIG. 3 and, after completion of chamber purging and
`resist ?lm can be exposed to a hexamethyl disilane
`flushing steps, the wafer is ?rst exposed to 100 Torr
`whereby silicon is reactively incorporated into the irra
`35
`HCl vapor and 20 Torr 02 vapor within the chamber.
`diated ?lm at selected regions. Subsequently, the ?lm is
`152. Then selected regions of the wafer are irradiated
`subjected to oxygen plasma. Since the silicon/polymer
`with 20 ns-long pulses of 193 nm wavelength light from
`regions etch slower than the regions having no incorpo
`an ArF excimer laser at a power density of approxi
`rated silicon, the patterns are developed.
`mately 300 mJ/cmz. This results in etching of the chro
`After the resist has been patterned, it is typically
`mium resist material so as to physically pattern the
`necessary in many applications to transfer the pattern to
`during the process, which is then pumped from the
`the underlying substrate. This is achieved, for example,
`chamber 152 through outlet conduit 160.
`by etching the resist-covered wafer, such as by Reactive
`A further example lies in laser-induced etching of
`Ion Etching (“RIE”). Returning to the overview of
`tungsten resists in chlorine gas. Again, a tungsten resist
`FIG. 1, this can be accomplished by the controller 40
`can be deposited upon a wafer by sputtering, evapora
`removing the wafer-in-process from module 14C or
`tion or other techniques as described above in connec
`14D, as appropriate, and returning it to main bus 18.
`tion with FIG. 2. The coated wafer can then be placed
`The controller then routes the wafer to processing line
`in the evacuated chamber 152, whereupon chlorine
`12B, as shown in FIG. 1. There, the wafer is queued up
`vapor is introduced to about 100 Torr pressure, and
`in another wafer queuing module 14E, similar to mod
`then the selected regions are irradiated at 40 mJ/cm2
`ule 14A. Then, in its turn, the wafer is directed into an
`energy density with 193 nm-wavelength pulses of 20 ns
`etching module 14F followed serially by the resist strip
`duration from an ArF excimer laser ir. order to remove
`ping module 14G.
`_
`the resist in the exposed regions.
`FIG. 5 is a representative embodiment of an etching
`Solid state conversion is the conversion of solid ?lm
`module 14F showing a RIE apparatus 250. The RIE
`from erodible to non-erodible (for negative resists) or
`55
`apparatus 250 includes a vessel or chamber 252 gener
`vice versa (for positive resists). An example of this tech
`ally similar in many ways to chamber 102 described
`nique