United States Patent [19]
`Ballard
`
`[11]
`[45]
`
`Patent Number:
`Date of Patent:
`
`4,529,621
`Jul. 16, 1985
`
`[54]
`
`[75]
`
`[73]
`
`PROCESS FOR DEPOSITING A THIN-FILM
`LAYER OF MAGNETIC MATERIAL ONTO
`AN INSULATIVE DIELECTRIC LAYER OF A
`SEMICONDUCTOR SUBSTRATE
`
`Inventor:
`
`Delbert L. Ballard, N orthridge, Calif.
`
`Assignee: Utah Computer Industries, Inc., Salt
`Lake City, Utah
`
`[21]
`
`Appl. No.: 539,729
`
`[22]
`
`Filed:
`
`Oct. 5, 1983
`
`[51]
`[52]
`
`[5 8]
`
`Int. Cl.3 .................. .. H01L 21/316; H01L 21/94
`US. Cl. ...................... .. 427/95; 204/192 M;
`365/171; 427/94; 427/96; 427/99; 427/131
`Field of Search ............. .. 204/ 192 M; 427/ 94-96,
`427/91, 99, 131; 365/171
`
`[56]
`
`Birkenbeil .................... .. 204/ 192 M
`
`References Cited
`U.S. PATENT DOCUMENTS
`3,161,946 12/1964
`3,573,485 4/1971
`3,702,991 11/1972
`3,800,193 3/1974
`4,149,301 4/1979
`
`Ballard . . . . . . . . .
`
`. . . . . . . . . . .. 307/406
`
`. 340/174 TF
`Bate et al.
`317/235 R
`Ashar et al. .
`Cook ............................ .. 29/25.42
`
`OTHER PUBLICATIONS
`Petersen, “Thin Film Magnetic Heads,” IBM TDB, vol.
`21, No. 12, May 1979, p. 5002.
`Ahn, “NiFe Films Mixed with $102 for Improved Ad
`hesion,” IBM TDB, vol. 18, No. 10, Mar. 1976, p. 3523.
`C. Morosanu et al., “Thin Film Preparation by Plasma
`and Low Pressure CVD in a Horizontal Reactor,” 31
`Vacuum, 309-313, No. 7 (1981).
`Primary Examiner—John D. Smith
`Attorney, Agent, or Firm-Workman, Nydegger &
`Jensen
`ABSTRACT
`[5?]
`The present invention is directed to a process for depos
`iting a thin-?lm layer of magnetic material onto an insu
`lative dielectric layer of a semiconductor substrate such
`that the layer of magnetic material completely and per
`manently adheres to the insulative dielectric layer. A
`product within the scope of the present invention is
`prepared by taking a semiconductor substrate, such as a
`silicon wafer, and through a chemical-vapor deposition
`process depositing a layer of an insulative dielectric
`(such as the silicon dioxide or silicon nitride) on the
`layer, and subsequently depositing a layer of a magnetic
`material (such as a nickel-iron alloy or a manganese-bis~
`muth alloy) through a sputtering process onto the insu
`lative dielectric layer. 1
`
`11 Claims, 5 Drawing Figures
`
`5|
`Substrate
`
`iOa
`
`Cimnicui Vapor Deposition
`of Si 02
`
`(d)
`
`200
`Ell-14+ 202mb Si (:12 0 ZHZO (Vapor)
`
`or
`
`Carrier
`
`BOO-IOOO‘C
`Hz Carrier
`
`12a
`
`'0‘
`
`Si Substrate
`
`Sputtering
`
`80-20 Ni Fe
`+
`i/"u
`N: F:
`
`i?n/ “ “F SI 02 {m
`SI Substrate
`/|oa
`
`Page 1 of 12
`
`IP Bridge Exhibit 2017
`TSMC v. IP Bridge
`IPR2016-01246
`
`

`

`"U.S. Patent Jul. 16,1985
`
`Sheetlof4
`
`4,529,621
`
`l0 /
`
`Semiconductor
`Substrate
`
`Chemical Vapor Deposition
`
`l2\- lnsulative Dielectric
`lo
`Semiconductor
`Substrate
`
`V
`
`Sputtering
`
`Magnetic Material
`mm.’
`IZL/ lnsulative Dielectric
`Semiconductor
`Substrate
`
`‘0V
`
`/'6
`
`Fig. l
`
`Page 2 of 12
`
`

`

`IU.S. Patent Jul. 16,1985
`
`Sheet20f4
`
`4,529,621
`
`100
`Si
`Substrate /
`
`Chemical Vapor Deposition
`of Si 02
`
`(a)
`
`(b)
`
`_
`
`'
`
`ZOO-500°C
`
`S|H4+ 202 N2 Currier
`
`_
`
`SI 02 + 2 H?O (Vapor)
`
`or
`
`>
`
`'
`
`SOC-900°C
`SI H4 4 CO2 N2 Comer SI 02 4 CO 2 H2O (Vapor)
`'
`+
`—-————> '
`+
`+
`
`'
`
`OI’
`
`(0)
`
`_
`
`SOC-900°C
`,
`%> +
`3| H4+2vco H2 Comer
`SI 02 c2 H4
`
`or
`
`(d)
`
`800-lOOO°C
`SI c|4+2 H2 + 2 co2 H2 Corrie-r
`
`'
`
`“p '
`
`SI 02 + 4 HCI 2 00
`
`+
`
`(e)
`
`Si H2C|2t2N2O—_> SiO2+2N2+2HC|
`
`or
`
`_
`
`Si 02
`Si Substrate
`
`/|2a
`/'°°
`
`Sputterihg
`80-20 Ni Fe
`+
`Ni Fe
`8| O2
`Si Substrate
`
`Fig. 2
`
`/'4°
`/|2a
`/|Oa
`
`leaf‘
`
`Page 3 of 12
`
`

`

`U.S. Patent Jul. 16,1985
`
`Sheet 3 of4
`
`4,529,621
`
`tOb
`3i
`Substrate / 7
`
`Chemical Vapor Deposition
`of
`N4
`
`(f)
`
`"SOD-"00°C
`3 Si H4 + 4 NH; H2 Comer
`
`Sig, N4 +12 H2 + 6 N2
`
`(g)
`
`(h)
`
`3
`
`H2 CIZ +
`
`NH3
`
`N4 + 6 NH4 +6 H2
`
`Si} N4
`Si Substrate
`
`flzb
`/I0b
`
`Sputtering
`80-20 Ni Fe
`L
`
`/|6b
`
`/—~|4b
`Fe
`/'\|2b
`Sig, N4
`SI Substrate /‘I0b
`
`Fig. 3
`
`Page 4 of 12
`
`

`

`US. Patent
`
`Jul. 16,1985
`
`Sheet4 of4
`
`4,529,621
`
`)24
`
`2|
`-
`I—
`
`28
`
`29
`
`‘
`
`
`
`32
`
`Fig. 4
`
`
`
` I356 MHZ
`RF GENERATOR
`
`1-2 KW
`
`
`Fig.5
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`Page 5 of 12
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`Page 5 of 12
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`

`

`1
`
`4,529,621
`
`PROCESS FOR DEPOSITING A THIN-FILM
`LAYER OF MAGNETIC MATERIAL ONTO AN
`INSULATIVE DIELECTRIC LAYER OF A
`SEMICONDUCTOR SUBSTRATE
`
`2
`means of storing information in digital computers. This
`type of storage cell has the inherent advantage of com
`pact construction and lack of power consumption. Even
`today, passive ferromagnetic-type storage cells are typi
`cally preferred in certain types of military applications
`because they are nonvolatile—that is to say, the infor
`mation stored in such a cell is not lost in the event of
`exposure to radiation or temporary loss of power. How
`ever, passive ferromagnetic-type storage cells also have
`a certain disadvantage in that readout of information is
`destructive since it is erased from the cell during the
`readout process. A further disadvantage is that the cell
`provides a very low output signal which must be ampli
`?ed for proper utilization.
`Some designs have been developed so that by using
`additional electronic circuitry, a “write-after-read”
`operation can be performed in which the information
`otherwise erased from the storage cell is immediately
`written back into the cell after the readout process.
`However, the use of such electronic circuits increases
`cost and creates further diminution of the output signal,
`thus increasing the ampli?cation problem which is al
`ready inherent by virtue of the low output signal pro
`vided by this type of storage cell.
`With the advent and improvement of low cost, high
`yield manufacturing processes for semiconductor inte
`grated circuits, the cost per bit of semiconductor com
`puter memories has steadily decreased over the last
`decade. Thus, increasingly the type of cell used to store
`digital information is derived from the use of active
`electronic elements arranged on semiconductor ICs in a
`conventional ?ip-?op (i.e., cross-coupled transistor)
`con?guration. Active electronic storage cells can be
`designed using either unipolar or bipolar transistors,
`which are typically manufactured at a relatively low
`cost on large or very large scale semiconductor inte
`grated circuits.
`These semiconductor or active ?ip-?op type storage
`cells have the advantage that readout is nondestructive
`and the output signal is higher than that of the passive,
`ferromagnetic-type storage cell. However, an inherent
`disadvantage is that power is continuously dissipated by
`the transistor elements, which creates undesirable heat
`ing effects. Furthermore, the stored digital information
`is lost if there is a power failure, even if the power loss
`is only momentary. The digital information stored in an
`active storage cell can also be destroyed by high density
`ionizing radiation and is thus not suitable for those types
`of applications which require nonvolatile storage.
`More recently, it has been proposed to combine the
`inherent advantages of both passive and active storage
`elements (i.e., low power consumption and non
`volatility of the ferromagnetic-type storage cell with
`the nondestructive readout and high signal output of an
`active flip flop configuration). See, e.g., US. Pat. No.
`3,573,485 issued Apr. 6, 1971 to Delbert L. Ballard. In
`this type of combination semiconductor/magnetic stor
`age cell, a circuit is formed using a pair of cross-coupled
`electronic switching elements such as bipolar or unipo
`lar transistors. Connected with at least one of these
`active switching elements as an impedance coupler is a
`passive (i.e., ferromagnetic) storage element. Digital
`information which is to be stored in the cell is electro
`magnetically written into the ferromagnetic storage
`element, thereby changing its effective impedance in
`the circuit. The readout signal is obtained from the
`electronic switching elements by providing power to
`
`BACKGROUND
`1. Field of the Invention
`This invention relates to integrated circuit fabrication
`process, and, more particularly, to a process for deposit
`in g a thin-?lm layer of magnetic material onto an insula
`tive dielectric layer of a semiconductor substrate.
`2. The Prior State of the Art, and Principal Objects of
`This Invention
`An integrated circuit (“IC”) consists of a series of
`discrete circuit elements which may either be active
`elements such as transistors or diodes, or passive ele
`ments such as resistors or capacitors, which are fabri
`cated in place as an integral part of a semiconductor
`substrate. Most often the substrate is a silicon “wafer”,
`although germanium and some other types of semicon
`ductive materials have also been used.
`Each wafer typically has numerous individual inte
`grated circuits formed on it. Transistors, which are the
`basic active integrated circuit elements, may be either
`bipolar, (that is, a transistor which depends on the prop
`erties of two types of charge carriers, namely, electrons
`or “n” type carries and holes or “p” type carriers, for its
`operation) or unipolar, (that is, one which depends on
`only one type of charge carrier). Bipolar transistors
`consist of base, collector and emitter regions formed on
`a selected layer of the substrate by doping the regions
`with certain chemical impurities which provide the
`desired type of charge carriers. Similarly, unipolar tran
`sistors consist of gate, source and drain regions formed
`on a selected layer of the substrate. Typical impurities
`which can be diffused in silicon to provide “n” or “p”
`type carrier regions include antimony (n type), arsenic
`(11 type), phosphorus (n type), boron (p type), gallium (p
`type) and aluminum (p type).
`As hereinafter more fully explained, the numerous
`individual circuit elements of each integrated circuit are
`formed on the semiconductor substrate using what is
`commonly called a planar process. Brie?y summarized,
`the planar process consists of forming a passivation
`layer of oxide or other suitable material on top of the
`silicon wafer, which is then photolithographically pat
`terned to permit selective introduction of “n” or “p”
`type impurities into the bulk of the silicon wafer at
`selected regions, thus altering the electrical properties
`of those regions. A series of three such selective intro
`ductions is required to form isolated bipolar transistors,
`whereas only one is required for unipolar transistors.
`Since the introduction of the concept of semiconduc
`tor integrated circuits by Jack Kilby in the late 1950’s,
`and with the development at about this same time of the
`planar process for making diffused transistors by Robert
`Noyce and Gordon Moore, semiconductor integrated
`circuit technology has played an increasingly important
`role in our society. One of the most fundamental and
`important applications of semiconductor integrated
`circuits has been their use in constructing computer
`memories, and one need only look at the growth of the
`computer industry to appreciate the degree to which
`our lives are now affected by this technology.
`Prior to the introduction in 1970 of the l-kilobit, fully
`decoded random access memory (“RAM”), passive,
`ferromagnetic storage cells were used as the basic
`
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`Page 6 of 12
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`

`

`4,529,621
`4
`FIG. 3 is a schematic diagram which illustrates sev
`eral alternative methods of producing a second pres
`ently preferred embodiment of the product manufac
`tured in accordance with the process of the present
`invention;
`FIG. 4 is a schematic diagram of an apparatus which
`may be used to accomplish heat-induced decomposition
`of selected gases in accordance with the process of the
`present invention; and
`FIG. 5 is a schematic diagram of an apparatus which
`may be used according to the process of the present
`invention to sputter the magnetic material onto the
`insulative dielectric layer.
`Reference is next made to a detailed description of
`the presently preferred embodiments of the invention as
`illustrated in the drawings.
`DETAILED DESCRIPTION OF THE
`PRESENTLY PREFERRED EMBODIMENTS
`The following detailed description begins with an
`overview of a manufacturing process for producing
`integrated circuits using a planar process. The discus
`sion then turns to a more detailed description of the way
`in which the process of the present invention is used in
`conjunction with such a planar process.
`
`20
`
`25
`
`3
`the switching elements in response to a readout address
`signal, with the electronic switching elements then as
`suming a conductive or nonconductive state which is
`determined by the effective circuit impedance provided
`by the ferromagnetic storage element.
`Notwithstanding the inherent advantages of a semi
`conductor/magnetic-type storage cell, it has been nec
`essary to overcome a number of very difficult practical
`problems in order to manufacture the passive ferromag
`netic element of this type of storage cell as an integrated
`component of a semiconductive integrated circuit. A
`principal problem which has been an impediment in this
`area has been the dif?culty in developing a workable
`process for permanently depositing a thin-?lm ferro
`magnetic or magnetic alloy layer into an insulative di
`electric layer of a semiconductor substrate.
`_
`It is therefore a primary object of the present inven
`tion to overcome the problems of the prior state of the
`art by providing a workable process for depositing a
`layer of ferromagnetic or magnetic alloy material onto
`an insulative dielectric layer such that the layer of mag
`netic material will completely and permanently adhere
`to the insulative dielectric layer.
`Another important object of the present invention is
`to provide a novel product which includes a thin-?lm
`layer of magnetic material deposited so as to completely
`and permanently adhere to a layer of insulative dielec
`tric material formed on a semiconductor substrate.
`The foregoing and other objects and features of the
`present invention will become more fully apparent from
`the following description and appended claims, taken in
`conjunction with the following drawings.
`BRIEF SUMMARY OF THE INVENTION
`In accordance with the foregoing principal objects,
`the present invention provides for a novel manufactur
`ing process which may be used, among other things, in
`producing a semiconductor/magnetic storage cell hav
`ing a thin-?lm layer of magnetic material formed as an
`integrated component of a semiconductor substrate.
`The process begins with preparation of a substrate such
`as a silicon wafer. The silicon wafer is processed so as to
`form the necessary circuit elements such as transistors,
`diodes, resistors, capacitors or the like which, when
`interconnected, form the individual integrated circuits
`45
`of the wafer. A layer of insulative dielectric material is
`deposited onto the wafer using a chemical-vapor depo
`sition process which consists of heat-induced decompo
`sition of selected gases. The insulative dielectric layer
`may typically consist of silicon dioxide or silicon ni
`tride, depending upon the particular gases and chemical
`reaction selected. A thin-?lm layer of magnetic material
`such as a nickel-iron or manganese-bismuth alloy is then
`deposited onto the layer of insulative dielectric material
`using a sputtering process. The resultant thin-?lm layer
`of magnetic material will completely and permanently
`adhere to the layer of insulative dielectric material.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`Reference is next made to the drawings, in which like
`parts are designated with like numerals throughout, and
`in which;
`FIG. 1 is a schematic diagram which generally illus
`trates the process of the present invention;
`FIG. 2 is a schematic diagram which illustrates sev
`eral alternative methods of producing one presently
`preferred embodiment of the product manufactured in
`accordance with the process of the present invention;
`
`65
`
`30
`
`40
`
`A. General Overview
`The manufacturing process begins with preparation
`of raw semiconductive material (usually silicon) into a
`suitable substrate which is formed as a small disc or
`wafer. The ?rst step in producing a silicon wafer is
`purifying raw silicon. This may be done by “zone refin
`ing” in which a molten zone is passed through a graph
`ite “boat” which contains the starting material. The
`result is separation and removal of impurities, leaving
`35
`' behind a chemically puri?ed polycrystalline silicon
`material. The puri?ed raw material is next converted
`into a single-crystal ingot. The ingot is grown by plac
`ing a single-crystal seed on the end of a shaft and rotat
`ing the shaft slowly through and away from the molten
`silicon. The melting and refreezing of the silicon at the
`seed interface allows crystal formation to take place.
`The cylindrical ingot is grown by slowly withdrawing
`the seed from the melt, with the critical parameters in '
`the single-crystal growth process being rotation and
`withdrawal rate of the seed, and purity and temperature
`uniformity of the melt.
`After the crystal growth is completed, the ingot is
`ground on one side to produce a “flat” that parallels the
`growth axis. The flat is used as a reference point for
`alignment of wafers during imaging and the like. After
`the flat is produced, the ingot is sliced using diamond
`saws into wafers which are typically twenty to forty
`mils thick, and approximately 7.6 cm in diameter. Sliced
`wafers are then lapped to remove damage or irregular
`ities caused by the slicing. Each wafer is then polished
`and chemically etched, leaving a highly polished, dam
`age-free surface.
`Once the silicon wafers are completed they are pro
`cessed in batches and are repetitively subjected to imag
`ing processes, to deposition and growth processes and
`to etching-masking processes. As described further
`below, each of these processes are complicated proce
`dures which can be combined and performed in an
`almost unlimited variety of ways.
`1. Imaging Processes
`Imaging processes are used to replicate patterned
`geometries on the wafer surface which represent the
`
`Page 7 of 12
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`

`

`6
`above) using diffusion or ion implantation techniques in
`order to generate p-n junctions which form active semi
`conductor devices such as diodes or transistors.
`Finally, various types of processes (called “metalliza
`tion”) can be used to produce the interconnecting wir
`ing pattern between the various circuit elements which
`form the integrated circuit. Wiring patterns can be
`formed on the wafer using flash evaporation, ?lament
`evaporation, electron-beam evaporation, planar and
`cylindrical sputtering, or induction evaporation meth
`ods.
`3. Etching-Masking Processes
`The etching-masking processes result in selective
`removal or addition of the deposited or grown layers of
`semiconductive or passivation materials in accordance
`with the patterned geometry which de?nes the inte
`grated circuit elements. The etching-masking steps can
`be accomplished in a variety of ways, depending upon
`the particular type of material that is to be masked or
`etched. Materials commonly used in the etching-mask
`ing steps are silicon dioxide, doped silicon dioxide,
`polysilicon, silicon nitride, metals and polyimide.
`The result of these highly complex imaging, deposi
`tion and growth, and etching-masking processes is the
`transformation of each substrate into a large number of
`integrated circuits which may contain literally tens or
`hundreds of thousands of individual circuit elements.
`Once these processes are completed, each wafer is
`scribed and diced so as to separate it into individual
`integrated circuits or chips, to which wire leads are then
`bonded prior to ?nal encapsulation and packaging.
`
`20
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`25
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`
`4,529,621
`5
`particular integrated circuit con?guration (i.e., inter
`connection of circuit elements) to be produced on each
`“chip" of the wafer. Imaging begins with either a chem
`ical or mechanical pretreatment of the wafers to remove
`dust and other forms of airborne or human contamina
`tion. Pretreatment of the wafers may also include appli
`cation of a resist adhesion promoter to enhance adhe
`sion of a photoresist which is applied to the wafers.
`Pretreatment is followed by coating the wafers with a
`photoresist, which is then subjected to infrared, con
`duction or microwave heating (call “softbaking”) in
`order to render the photoresist sensitive to exposure
`energy.
`Using a photomask, the wafers are exposed by either
`blanket exposure, step-and-repeat exposure, or scanning
`using a beam of exposing energy. This exposure pro
`duces a latent image closely matching the pattern of the
`photomask. Next, the wafers are sprayed with a devel
`oper solution for a predetermined time in order to per
`mit the solution to selectively attack and remove either
`exposed regions (in the case of a positive photoresist) or
`unexposed regions (in the case of a negative photore
`sist). The result is that a geometric pattern or “image” is
`left behind; this image serves as a mask for etching or
`for subsequent application of selected metals to be used
`as the interconnecting wiring pattern between circuit
`elements.
`The wafers may then be subjected to postbaking in
`order to insure that the photoresist is adequately
`bonded. Postbaking is accomplished in the same manner
`as softbaking. The wafers are then etched using either
`wet or dry etching techniques in order to completely
`remove selected regions of a deposited oxide layer
`which are left exposed after the developing process.
`Once etching is completed, the photoresist is re
`moved by immersing the wafers in a heated resist-strip
`ping solution or by placing them in a plasma-stripping
`chamber, where an oxygen plasma removes the resist.
`The surface of the wafers are then completely free of
`any photoresist material and the wafers are ready for
`40
`ion implantation or diffusion, after which another thin
`layer of oxide is generally deposited or grown over the
`wafer and the entire cycle is repeated.
`2. Deposition and Growth Processes
`Deposition and growth processes are used to apply
`various layers of semiconductive or passivation materi
`als to the wafer in order to selectively modify and/or
`insulate the electrical characteristics of various regions
`in the wafer for the purpose of forming the desired
`circuit components such as transistors, diodes, resistors,
`or capacitors.
`Like imaging processes, deposition and growth pro
`cesses can be performed in a wide variety of ways. For
`example, layers of iron oxide or other suitable passiv
`ation materials may be formed using certain oxidation
`or deposition processes. Such layers of passivation ma
`terials provide a base for photoresist adhesion and imag
`ing, and/or provide an insulating layer between various
`other layers which contain circuit elements or intercon
`necting wiring patterns. Deposition and growth pro
`cesses may include processes such as epitaxial growth,
`wherein a single-crystal material is applied to a silicon
`wafer of the same crystal orientation so as to grow a
`semiconductive layer which is used to provide the base
`and collector regions for bipolar transistors.
`.Regions of the various semiconductor layers may
`then be de?ned by masking and etching, and then dop
`ing the layers with chemical impurities (as described
`
`45
`
`B. The Preferred Processes and Products
`From the foregoing overview, it is readily apparent
`that an almost in?nite variety of combinations of steps
`can be used to accomplish the basic steps of imaging,
`deposition and growth, and etching-masking, which are
`used to manufacture a particular integrated circuit con
`?guration.
`The process of the present invention is intended to be
`used as a part of the type of overall planar process
`described above. However, while the process of the
`present invention is particularly useful in producing a
`special type of semiconductor/magnetic storage cell in
`which a thin-?lm ferromagnetic element is formed as an
`integrated component of the semiconductor substrate,
`those of skill in the art will readily appreciate that the
`process of the present invention can be used in conjunc
`tion with a very wide variety of integrated circuit fabri
`cation processes which could be used for producing
`> other types of integrated circuit con?gurations.
`In its simplest form, the process of the present inven
`tion may be generally described and illustrated with
`reference to FIG. 1. As shown in FIG. 1, a semiconduc
`tor substrate 10 is typically prepared in the form of a
`wafer from a suitable semiconductive material; silicon is
`the most commonly used material for the wafer.
`After the wafer 10 has been subjected to appropriate
`imaging, deposition and growth, and etching-masking
`processes so as to form the basic transistor elements for
`each integrated circuit of the wafer, the wafer is sub
`jected to a chemical-vapor deposition process so as to
`form an insulative dielectric layer 12 on the wafer 10 by
`means of heat-induced decomposition of selected gases.
`The insulative dielectric layer 12 may typically com
`prise. silicon dioxide, silicon nitride, or any other suit
`able insulative dielectric material which can be depos
`ited by chemical-vapor deposition.
`
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`8
`7
`According to the reaction of equation (b) of FIG. 2,
`One method for chemical-vapor deposition of insula
`silane is reacted with carbon dioxide, in the presence of
`tive layer 12a of silicon dioxide is to react silane (SiH4)
`nitrogen, at a temperature of between about 500° C. and
`and oxygen (02) according to the reaction set forth in
`about 900° C. Through this reaction mechanism, a layer
`equation (a) of FIG. 2. In order to obtain the most desir
`of silicon dioxide may be deposited onto a prepared
`able growth rate of silicon dioxide layer 12a which has
`silicon wafer.
`a sufficiently high quality and which is of a relatively
`According to the reaction of equation (0) of FIG. 2,
`uniform thickness, the wafers are preferably heated to a
`silane may be reacted with carbon monoxide in the
`temperature in the range of about 350° C. to about 500°
`presence of hydrogen gas at a temperature of between
`C. during the vapor-deposition reaction of equation (a).
`about 500° C. and 900° C. in order to produce the de
`While it will be appreciated that temperatures outside
`sired silicon dioxide layer, according to the reaction of
`the indicated range may be utilized, these temperatures
`equation (d) of FIG. 2. Alternatively, silicon chloride
`have been found to be the most effective under practical
`(SiCl4) may be reacted with carbon dioxide in the pres
`manufacturing conditions. This is because the growth
`ence of hydrogen gas at a temperature of between 800°
`rate of the deposited layer of silicon dioxide peaks at
`C. and about 1000° C. in order to produce the silicon
`about 400° C. and then falls off relatively rapidly as the
`dioxide layer, according to the reaction of equation (d)
`temperature gets signi?cantly hotter or colder. Hence,
`of FIG. 2. Finally, silicon dioxide layer 12a may be
`when the vapor deposition reaction of equation (a) is
`produced according to the reaction of equation (e) of
`used, the wafers are most preferably heated to a temper
`FIG. 2 in which dichlorosilane (SiHZClZ) is reacted in
`ature in the range of about 400° C. to about 410° C.
`the presFe-of nitrous oxide (N20).
`Within the temperature range of from about 400° C. to
`Various types of reaction chambers may be used to
`about 410° C., the growth rate of deposited silicon (1103(
`carry out the process for chemical vapor deposition of
`ide layer 12a is about one thousand angstroms (1000 A)
`the silicon dioxide layer. In typical reaction chambers, a
`per minute.
`susceptor (with silicon wafers placed on its surface) is
`As mentioned above, typical reaction rates can be
`rotated or otherwise moved in the gas environment to
`controlled to result in the deposition of silicon dioxide
`provide uniformity during the deposition process. The
`at a rate as high as a thousand angstroms a minute.
`reaction chamber can comprise a standard bell-jar type
`Maximizing this deposition rate is advantageous in a
`of chamber, where the gas is pumped up through the
`commercial manufacturing setting, provided that the
`susceptor; alternatively, the reaction chamber may
`necessary high quality and uniformity can be main
`comprise a horizontal system in which the gas is passed
`tained. Of course, under certain circumstances, it will be
`from one end of the chamber to the other. Barrel sys_
`appreciated that greater uniformity may be necessary;
`tems, in which wafers are placed on a rotating cylinder,
`hence, lower deposition rates may be desirable.
`have also been devised.
`The thickness of the silicon dioxide layer will vary
`The heat sources which provide the deposition tem
`depending upon the speci?c application. For space
`perature are generally one of two types, either cold
`considerations, it is usually desirable to have this silicon
`wall or hot-wall. A typical cold-wall system uses ultra
`dioxide layer as thin as possible; however, if the layer is
`violet or radio-frequency energy to heat the susceptor,
`too thin, it may crack or be unable to fully insulate the
`which in turn heats the wafers by conduction. In a
`adjacent layers. YVhen the silicon dioxide layer is less
`cold-wall system, the walls of the reaction chamber are
`than about 2000 A, cracking of the layer is not uncom
`at a lower temperature than those of hot-wall chambers,
`mon. Thus, it is contemplated that under most circum
`in which thermal-resistance heating is used.
`stances, the silicon dioxide layer will be allowed to
`In a hot wall machine, the entire reaction chamber is
`grow to a thickness of between about 2,000 and about
`heated; hence, the walls of the machines are equally hot.
`10,000 angstroms in thickness with the presently pre
`Hot wall machines have the advantage of providing
`ferred thickness being between about 8000 A and about
`greater uniformity in the thickness of the insulative
`10,000 A.
`layer which is produced; however, they are typically
`In order to obtain greater uniformity in the thickness
`more expensive and have a less throughput. Hence, it is
`of the silicon dioxide layer 120 which is produced ac
`typical, in the absence of a need for high uniformity of
`cording to reaction (a) of FIG. 2, the silane, which may
`the layer, to use a cold wall apparatus.
`be in a nitrogen carrier gas, is preferably not allowed to
`An example of such a cold-wall apparatus which can
`mix with oxygen until it is in the vicinity of the heated
`be used to accomplish low temperature chemical vapor
`wafers. Since the uniformity of layer 12a is controlled
`deposition of the silicon dioxide is schematically illus
`by the reaction temperature, it is desirable to have the
`trated in FIG. 4. The apparatus of FIG. 4 includes an
`reaction take place on the wafer when it has been com
`automatic load station generally designated at 18 in
`pletely heated to the desired temperature.
`which a “boat” 20 is loaded with the wafers 21. The end
`In addition, greater uniformity in the silicon dioxide
`of the automatic load station 18 is sealed with a sealing
`layer can be achieved and cracking can be minimized by
`plate 22, and the boat 20 containing the wafers 21 is then
`phosphorus doping of the silicon dioxide. By adding
`inserted into a long, horizontal quartz tube 34. The
`trace amounts of phosphorus according to procedures
`selected gases (for example, silane and oxygen in a nitro
`known in the art, the silicon dioxide layer can be thinner
`gen carrier gas) are then injected by means of a ?ow
`and yet provide satisfactory insulation.
`controlled gas system 26 into the reaction chamber
`The presently preferred reaction for depositing diox
`generally designated at 28, which includes a resistance
`ide layer 120 is set forth in equation (a) of FIG. 2. There
`heated furnace 29.
`are, however, other chemical reactions which could be
`Spike thermocouples schematically illustrated at
`utilized within the scope of the present invention in
`30-32 are used to monitor temperature, and a pressure
`order to provide for chemical-vapor deposition of a
`satisfactory silicon dioxide layer. Through this reaction
`sensor 24 is used to monitor pressure. An in-tube ther
`mocouple 36 is typically inserted in exhaust tube 50,
`mechanism, a layer of silicon dioxide may be deposited
`through which the undesired gaseous byproducts pass
`onto a prepared silicon wafer.
`
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