United States Patent [19]
`Yu et a1.
`
`[54] INTEGRATED CIRCUIT POLISHING
`METHOD
`[75] Inventors: Chris C. Yu; Gurtej S. Sandhu; Trung
`T. Doan, all of Boise, Id.
`[73] Assignee: Micron Technology, Inc., Boise, Id.
`[211 App]. No.: 858,670
`[22] Filed:
`Mar. 27, 1992
`
`[51] Int. Cl.5 ......................................... .. H01L 21/302
`[52] us. c1. .................................. .. 437/225; 437/974;
`156/636
`[58] Field of Search ....... .. 156/636; 51/281 R, 283 R;
`437/225, 228, 974
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,735,679 4/1988 Lasky ................................ .. 156/636
`4,839,311 6/1989 Riley et a].
`437/241
`4.847,]11 7/1989 Chow et al.
`437/41
`4.956.313 9/1990 Cote et a1. ..... ..
`156/636
`4.992.135 2/1991 Doan ............. ..
`156/636
`5.064.777 11/1991 Dhong et al.
`437/233
`5,169,491 12/1992 Doan ................................. .. 156/636
`
`FOREIGN PATENT DOCUMENTS
`
`253706 l/1988 Fed. Rep. of Germany .... .. 156/636
`
`OTHER PUBLICATIONS
`R. S. Bennett et al., “Selective Planarization Process
`and Structures,” IBM Tech. Disc. Bull., vol. 27, No. 4B,
`Sep. 1984, pp. 2560-2563.
`G. H. Schwuttke et al., “New Gettering Process Using
`Laser-Induced Damage . . . ,” IBM Technical Disclosure
`Bulletin. Vol. 26, No. 1, Jun. 1983, p. 245.
`W. L. C. M. Heyboer et al., "Chemomechanical Silicon
`
`l|||l|IllllllllllllllllllllIlllllllllllllllllllllllllllllIlllllllllllllllll
`
`USO05314843A
`5,314,843
`[11] Patent Number:
`[45] Date of Patent: May 24, 1994
`
`Polishing”, J. Electrochem. Society, vol. 138, No. 3, Mar.
`1991, Pp- 774-777.
`‘
`“Enhanced Metal Polish: Corrosion Control by Tem
`perature Friction .
`.
`. ” International Technology Disclo
`sures, vol. 9, No. 8, Aug. 25, 1991.
`G. S. Oehrlein et a1., “Competitive Reactions of Fluo
`rine and Oxygen with W, WSi, and Si Surfaces . . . ” J.
`Vac. Sci. Tech A, vol. 7, N0. 3, May/Jun. 1989, pp.
`1035-1041.
`
`Primary Examiner-Tom Thomas
`Assistant Examiner—Michael Trinh
`Attorney, Agent, or Firm—Dorr, Carson, Sloan &
`Peterson
`'
`
`ABSTRACT
`[57]
`A semiconductor wafer has a surface layer to be plana
`rized in a chemical mechanical polishing (CMP) pro
`cess. An area of the layer that is higher than another
`area is altered so that the removal rate is higher. For
`example, if the surface layer is TEOS oxide, the higher
`layer may be bombarded with boron and phosphorus to
`produce BPSG, which has a polishing rate 2-3 times
`that of the TEOS. Upon CMP planarization, the higher
`area erodes faster resulting in improved planarization.
`Alternatively, the lower area may be doped with nitro
`gen to produce a nitride which is more resistant to
`CMP. with the same result. Likewise areas, such as
`tungsten troughs, which tend to be dished by CMP,
`may be changed to WNx which is more resistant to the
`tungsten CMP than the adjacent tungsten, eliminating
`the dishing upon planarization.
`.
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`23 Claims, 4 Drawing Sheets
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`May 24, 1994
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`May 24, 1994
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`Fig. /0A
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`5000
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`D IMIN OVER
`POLISHING
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`400°
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`0 NO OVER
`POLISHING
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`1
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`2
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`3
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`4
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`5
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`=2
`0 3000
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`2000
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`1000
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`ZIU
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`? 5
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`I
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`DISHING(A)
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`0
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`100
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`120
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`METAL FEATURE SIZE (,LLm)
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`1
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`INTEGRATED CIRCUIT POLISHING METHOD
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`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The invention in general relates to the fabrication of
`integrated circuits, and more particularly to structures
`and methods for improving the polishing steps in the
`fabrication of integrated circuits.
`2. Statement of the Problem
`As is well-known, integrated circuits are generally
`mass produced by fabricating hundreds of identical
`circuit patterns on a single semiconducting wafer which
`is subsequently sawed into hundreds of identical dies or
`chips. While sometimes referred to as “semiconductor
`devices", integrated circuits are in fact fabricated from
`various materials which are either electrically conduc~
`tive, electrically non-conductive, or electrically semi~
`conductive. Silicon, the most commonly used semicon
`ductor material, can be used in either the single crystal
`or polycrystalline form. Both forms of silicon may be
`made conductive by adding impurities to it, which is
`commonly referred to as “doping". If the doping is with
`an element such as boron which has one less valence
`electron than silicon, electron “holes” become the dom
`inant charge carrier and the doped silicon is referred to
`as P-type silicon. If the doping is with an element such
`as phosphorus which has one more valence electron
`than silicon, additional electrons become the dominant
`charge carriers and the doped silicon is referred to as
`N-type silicon. Silicon dioxide is also commonly used in
`integrated circuits as an insulator or dielectric. Its use is
`so common that in the art is generally referred to as
`“oxide” without ambiguity.
`As indicated above, the properties of silicon are rou
`tinely adjusted in integrated circuit technology by add~
`ing dopants. Likewise it is common practice to modify
`other materials, such as conductors or insulators, by
`adding other components. Or, one material, such as
`silicon, may be removed or replaced by another. Pro
`cesses that commonly are used to modify, remove, or
`deposit a material are ion implantation, sputtering, etch
`ing, chemical vapor deposition (CVD) and variations
`thereof, such as plasma enhanced chemical vapor depo
`sition (PECVD).
`The above-discussed processes are often selectively
`applied to an integrated circuit through the use of a
`masking process. In a masking process, a photo mask
`containing the pattern of the structure to be fabricated is
`created, the wafer is coated with a light-sensitive mate
`rial called photoresist or resist, the resist-coated wafer is
`exposed to ultraviolet light through the mask to soften
`or harden parts of the resist depending on whether
`positive or negative resist is used, the softened parts of
`the resist are removed, the wafer is treated by one of the
`processes discussed above to modify, remove, or re
`place the part unprotected by the resist, and then the
`remaining resist is stripped. This masking process per
`mits specific areas of the integrated circuit to be modi
`tied, removed or replaced.
`Another process commonly used in fabrication of
`integrated circuits is chemical mechanical polishing
`(CMP). This process involves chemically etching of a
`surface while also mechanically grinding or polishing it.
`The combined action of surface chemical reaction and
`mechanical polishing allows for a controlled, layer by
`layer removal of a desired material from the wafer sur
`face, resulting in a preferential removal of protruding
`
`5,314,843
`2
`surface topography and a planarized wafer surface.
`CMP is generally accomplished by polishing the wafer
`front surface against a polishing pad wetted with a
`slurry comprised of three ingredients: an acidic or basic
`solvent; an abrasive; and a suspension ?uid. The CMP
`process is generally used to remove undesirable residues
`remaining from other processes, particularly when it
`also desirable to create a smooth, planar surface for a
`subsequent process. In the past few years, CMP has
`become one of the most effective techniques for plana
`rizing all or a portion of a semiconductor wafer. How
`ever, while a good local planarization can be readily
`achieved in a CMP process, obtaining a complete pla
`narization with good uniformity on the scale of a wafer,
`or even a die, is not easy. On the wafer scale, the polish
`ing rate often is not uniform from wafer center to edge
`due to a difference in relative speed between the polish
`ing platen and the wafer carrier at wafer center and
`edge. On the die scale, planarization is also not easy due
`to height differences in the oxide layer between differ
`ent regions on the die, for example between a memory
`array and the periphery area in a die. On a smaller scale,
`planarization is difficult because of differences in the
`height of the oxide layer between, for example, N-well
`regions and P-well regions. As another example, the
`material removal rate will vary from place to place on
`the wafer, depending on the wafer structure and com
`position. For example, the polishing rate at a wafer
`trough often differs from that at the other parts of the
`wafer due to the different slurry distribution and ?ow at
`the different areas. These differences are particularly
`acute in stacked capacitor DRAMs. This lack of homo
`geneous planarization can result in some material not
`being removed to a desired ?nal thickness that was
`intended, i.e under polishing, in some material being
`removed that it was not intended to remove, i.e. over
`polishing, or both. Further, since the subsequent pro
`cesses assume or even require a planar wafer surface,
`this lack of planarization can alter the properties and
`parameters of the device. All of these results contribute
`to defective devices, loss of device yield, and lack of
`device reliability. Thus there is a need for apparatus and
`methods to improve the uniformity of planarization in
`the CMP process.
`Since semiconductor devices are becoming more
`complex in structure and materials, and since the CMP
`planarization process is dependent on structure and
`materials, apparatus and techniques that permit the
`fabrication engineer to control and design the CMP
`process would be highly desirable.
`Generally, a change in one phase of the integrated
`fabrication process usually impacts other phases. Since
`integrated circuit fabrication processes are highly com
`plex and require sophisticated equipment, developments
`of entirely new processes and materials can be quite
`costly. Thus new apparatus and methods for control of
`the CMP process that can be incorporated into current
`fabrication technology would be highly desirable be
`cause expensive modi?cation of equipment and pro
`cesses can be avoided.
`3. Solution to the problem
`The present invention solves the above problems by
`providing an integrated fabrication method in which,
`prior to the CMP process, a portion of the wafer surface
`is modi?ed in selected areas so that the polishing rate in
`these areas is altered. For example, areas that tend to be
`dished after the conventional CMP process, may be
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`3
`modi?ed in a plasma nitridation process to create a
`material more resistant to polishing, thereby decreasing
`the polishing rate, with the net result that after the CMP
`process the dishing is eliminated. Or an area where
`there are large height differences in a surface to be
`planarized, the higher area is modi?ed in an ion implan
`tation process to create a material less resistant to pol
`ishing, thereby increasing the polishing rate, with the
`net result that after the CMP process, the overall sur
`face is flat with the height differences eliminated.
`
`5,314,843
`4
`mechanical polishing process until all of the second
`material is removed and the ?rst material is planarized.
`The invention not only provides a solution to the
`planarization problems in CMP, but offers a way to do
`so with standard semiconductor and CMP technology.
`Numerous other features, objects and advantages of the
`invention will be apparent from the following descrip
`tion when read together with the accompanying draw
`ings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a cross-sectional view of a portion of a prior
`art semiconductor device wafer to which CMP has
`been applied;
`FIG. 2 is a cross-sectional view of the portion of the
`semiconductor device wafer according to the invention
`after a portion of the surface layer has been altered to
`make it more resistant to CMP;
`FIG. 3 is a cross-sectional view of the portion of the
`semiconductor device wafer of FIG. 2 after planariza
`tion;
`~
`FIG. 4 is a cross-sectional view of a semiconductor
`wafer according to an alternative preferred embodi
`ment of the invention in which a reverse mask has been
`used to alter a portion of the wafer surface to make it
`less resistant to CMP;
`FIG. 5 is a cross-sectional view of a semiconductor
`wafer according to another alternative preferred em
`bodiment of the invention in which a portion of the
`oxide layer overlying the periphery of a memory array
`has been altered to make it less resistant to CMP;
`FIG. 6 is a cross-sectional view of the semiconductor
`wafer of FIG. 5 after planarization;
`FIG. 7 is a cross-sectional view of a semiconductor
`wafer according to a further alternative preferred em
`bodiment of the invention in which a portion of the
`surface of an oxide layer overlying the semiconducting
`substrate adjacent the periphery of a memory array has
`been altered to make it more resistant to CMP;
`FIG. 8 is a cross-sectional view of a semiconductor
`wafer according to an additional preferred embodiment
`of the invention in which a BPSG layer over a N-well
`region has been altered to yield a slower polishing rate;
`FIG. 9 is a cross-sectional view of the semiconductor
`wafer of FIG. 8 after planarization.
`FIG. 10A is a graph of the experimentally determined
`dishing as a function of feature size for several different
`polishing conditions; and
`FIG. 10B is a graph of the experimentally determined
`dishing as a function of feature size for two different
`?lms.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`
`1. Overview
`Turning now to FIG. 1, there is shown a cross-sec
`tional view of a portion of a semiconductor wafer 2
`according to the prior art. It should be understood that
`the ?gures are not meant to be actual cross-sectional
`views of any particular portion of an actual semicon
`ducting device, but are merely idealized representations
`which are employed to more clearly and fully depict
`the process of the invention than would otherwise be
`possible. Wafer 2 comprises a semiconducting substrate
`3 and an oxide layer 4, that has been patterned to form
`a relatively wide trough 5 and an irregular area 6 with
`multiple narrow troughs, such as 7. A conducting layer
`8 has been deposited on the wafer 2 ?lling in the troughs
`
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`
`SUMMARY OF THE INVENTION
`The invention provides a method of fabrication of an
`integrated circuit, the method comprising the steps of:
`providing a semiconductor wafer having a surface layer
`of a material to be planarized in a chemical mechanical
`polishing process; altering a ?rst portion of the surface
`layer of material to respond differently to the chemical
`mechanical polishing process than a second portion of
`the surface layer; and polishing the surface layer in a
`20
`chemical mechanical polishing process. Preferably, the
`step of altering comprises adding an impurity to the
`material. Alternatively, the step of altering comprises
`chemically altering the ?rst portion of material. Both
`above approaches are intended to modify the wafer
`surface in the selected areas so that the polishing rate in
`these areas can be altered.
`In another aspect the invention provides a method of
`fabrication of an integrated circuit. the method compris
`ing the steps of: providing a semiconductor wafer hav‘
`ing a surface layer of a ?rst material to be planarized in
`a chemical mechanical polishing process; altering a
`portion of the surface layer of material to create a sec
`ond material which responds differently to the chemical
`mechanical polishing process than the ?rst material; and
`polishing the surface layer in a chemical mechanical
`polishing process. Preferably, the step of polishing com
`prises removing all of the second material. Preferably,
`the step of altering comprises doping selected portions
`of the ?rst material. In one embodiment, the ?rst mate
`rial is silicon dioxide, the step of doping comprises dop
`ing with boron or phosphorous and the second material
`is doped silicon oxide. Alternatively, the step of doping
`comprises doping with nitrogen. In another embodi
`ment, the ?rst material is tungsten, the modi?cation
`process comprises nitridation in a nitrogen (N) or am
`monia (NH3) plasma, and the second material is tung
`sten nitride.
`In a further aspect, the invention provides a method
`of fabrication of an integrated circuit, the method com
`prising the steps of: providing a semiconductor wafer
`having a surface layer of a ?rst material to be planarized
`in a chemical mechanical polishing process; altering a
`portion of the surface layer of material above a wafer
`trough to create a second material more resistant to the
`chemical mechanical polishing process than the ?rst
`material; and polishing the surface layer in a chemical
`mechanical polishing process until all of the second
`material is removed and the ?rst material is planarized.
`In yet another aspect, the invention provides a
`method of fabrication of an integrated circuit compris
`ing the steps of: providing a semiconductor wafer hav
`ing a surface layer of a ?rst material to be planarized in
`a chemical mechanical polishing process; altering a
`portion of the surface layer of material at either side of
`a trough to create a second material less resistant to the
`chemical mechanical polishing process than the ?rst
`material; and polishing the surface layer in a chemical
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`5 and 7. Chemical mechanical polishing (CMP), a well
`known planarizing process in the semiconductor fabri
`cation art, has been applied to the surface of conducting
`layer 8. If the CMP is continued when the interface
`between metal 8 and substrate oxide 4 is reached, the
`metal surface above the area 5 will continue to be pol
`ished due to the elasticity of the pad. This results in
`dishing of the surface 9 above the trough area 5. The
`dishing is far less in areas such as the area above the
`small trough area 6 because the pad is relatively ?at
`above the small metal features and the applied pad pres
`sure is mainly concentrated on the oxide 4. Turning
`now to FIG. 2, there is shown a cross-sectional view of
`a portion of a semiconductor wafer 10 according to the
`preferred embodiment of the invention. Wafer 10 com
`prises a semiconducting substrate rate 12 and an oxide
`layer 13, that has been patterned to form a relatively
`wide trough 16 and an irregular area 18 with multiple
`narrow troughs, such as 19. A conducting layer 14 has
`been deposited on the wafer 10 ?lling in the troughs 16
`and 19. In the method according to the invention, a
`portion 24 of the layer 14 is altered to form a material
`which is more resistant to CMP than the material of the
`adjacent portions of layer 14. The form and type of
`alteration is selected to just balance the effect of the
`dishing, so that when the surface 20 is polished, the
`removal rate of the material 24 above the trough 16 is
`slower than the removal rate of the material of layer 14
`in the area above the area 18 adjacent the trough 16.
`The depth of alteration 24 is controlled so that all of the
`altered material 24 is removed when the desired planari
`zation (FIG. 3) has been achieved.
`2. Detailed Description of the Fabrication
`Returning now to FIG. 2, semiconductor wafer 10
`includes a substrate 12 which is preferably lightly doped
`P-type single crystal silicon, but may also be polysili
`con, N~type silicon, or any other type of conducting or
`semiconducting material that may be used in a semicon
`ductor device. A conventional pad silicon oxide layer
`13 has been formed on the substrate 12. By well-known
`fabrication processes, the oxide 13 has been patterned to
`form a relatively wide trough l6 and a series of narrow
`troughs, such as 19, in the area 18 adjacent trough 16.
`The structure of the substrate 12 and oxide layer 13 in
`an actual semiconductor device may be considerably
`more complex and include various dopings of the sub
`strate 12 which are omitted for clarity. A tungsten layer
`14 has been formed on wafer 10 by any conventional
`process such as chemical vapor deposition. The desired
`end result of this deposition process is that the troughs
`l6 and 19 be ?lled with tungsten 14 up to and no further
`than the surface 30 of oxide layer 13. However, to be
`sure that all the troughs 16 and 19 are ?lled with tung
`sten 14, the layer 14 includes an excess of tungsten. In
`the conventional processes of fabrication, after forma
`tion of the layer 14 the surface 20 is removed by a chem
`ical mechanical polishing process (CMP) which, for
`removal of tungsten, comprises mechanically polishing
`the tungsten in a slurry comprising the combination of
`two or three ingredients including: 1) a chemical base
`such as hydrogen peroxide (H202) dissolved in water;
`2) an abrasive, such as alumina, silica, or titanium oxide
`(TiOX where x equals 1 to 2) ; and 3) an optional ?uid,
`such as ethylene glycol in which the abrasive is sus
`pended. The CMP process tends to continue to polish
`tungsten when the tungsten and oxide substrate inter
`face is reached in the region over the trough 16 due to
`the dishing effect discussed in the last section.
`
`6
`In the process according the invention, a portion 24
`of the layer 14 is altered to make it more resistant to the
`tungsten CMP process, resulting in a slower removal
`rate in portion 24. Preferably, portion 24 is altered by
`masking and immersion of the wafer in a nitrogen or
`ammonia plasma to form tungsten nitride (WNx) or by
`nitrogen implantation. The masking and nitridation
`processes are well-known in the semiconductor art, and
`thus will not be described in detail. The wafer 10 is then
`planarized by CMP and the result is shown in FIG. 3.
`The removal rate in the tungsten nitride area 24 has
`been decreased just enough to result in a thicker tung
`sten ?lm in the region above trough 16 than that in
`region above area 18 when the tungsten and oxide inter
`face is reached. So during the continued CMP process
`to clear metal residue above the oxide 13, the tungsten
`?lm in area above trough 16 will become ?ush with the
`oxide 13, with no dishing.
`FIG. 4 shows an alternative preferred embodiment of
`the invention to reach the result shown in FIG. 3. In
`FIG. 4 the wafer of FIG. 1 has been subjected to a
`masking step and oxidation in a plasma to create tung
`sten oxide (WOx) regions 34 and 36 adjacent the trough
`16. The tungsten oxide regions 34 and 36 are less resis
`tant to tungsten CMP than the undoped tungsten 14.
`The masking and oxidation is designed so that the re
`moval rate of the portions 34 and 36 of tungsten layer 14
`is increased to produce a protruding tungsten pro?le
`above area 16 when the tungsten and oxide interface is
`reached, again with the result that the wafer surface 30
`(FIG. 3) is smooth and flat with no dishing. The areas
`masked to produced the pattern of FIG. 4 is the reverse
`of the areas masked to produce the doping pattern of
`FIG. 2, and thus the process of FIG. 4 is called a reverse
`mask process.
`FIG. 5 illustrates another preferred embodiment of
`the method of the invention. The ?gure is an idealized
`depiction of the periphery area 38 adjacent a memory
`array 40. The array 40 typically comprises a semicon
`ducting substrate 41, multiple layers of semiconducting,
`conducting, and insulating materials in the area 42, and
`a boro-phospho-silicate glass (BPSG) silicon oxide layer
`44. Both the substrate 41 and the area 42 are generally
`complex structures involving many different doped
`areas, the details of which do not play a role in the
`present invention, and thus are omitted for clarity. The
`multiple layers in the area 42 raise the memory array 40
`signi?cantly above the level of the substrate 41 and thus
`there is a large height difference between the array 40
`and the periphery 38. In the prior art, as one of the ?nal
`steps of fabrication, the entire wafer is over-laid with
`the BPSG layer and planarized by a CMP process in
`which the etch solvent is preferably potassium hydrox
`ide (KOH) diluted in water, the abrasive is silica, and
`the suspension fluid is ethylene glycol. The large height
`difference will generally make it dif?cult to create a
`smooth, flat surface at the boundary of array 40. In the
`preferred embodiment of the invention, rather than
`overlay the entire wafer with BPSG, the entire wafer is
`overlaid with an undoped silicon dioxide, such as tetra
`ethooxysilane (TEOS) layer 46, the wafer is masked
`(not shown), and a portion 44 is implanted with boron
`and phosphorus in an ion implantation process to create
`the BPSG layer 44. Both the masking and ion implanta
`tion are well-known processes in the semiconductor
`device fabrication art and thus will not be described in
`detail. The polishing rate of BPSG 44 is much higher
`that the polishing rate of the undoped oxide 46, thus it
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`8
`icant for one minute of over polishing particularly for
`feature sizes of width greater than about 1 pm. FIG.
`10B shows dishing as a function of feature size for a
`chemical vapor deposited tungsten metal ?lm and for an
`AlSiCu ?lm. The dishing is negligible for narrow fea
`tures, but rises rapidly as the feature size approaches
`about 1 pm, and then appears to level off at a relatively
`high value of about 5000A. Generally, we have found
`that for features less than 1 pm in width, dishing is
`negligible, and for features of 4 pm or larger, dishing is
`signi?cant.
`Turning to the embodiments of FIGS. 5-7, for a
`difference of about 0.5 pm to 1.5 pm in heights between
`the memory array 40 and the periphery 38, the thickness
`of implanted BPSG layer 44 in the embodiment of FIG.
`5 may range from about 2000A thick to about 7000A
`thick, and nominally is about 5000A thick. The relative
`dimensions for an application of the invention that in
`volves the silicon oxides, such as the embodiment of
`FIGS. 5 and 6, may be found from table I, which gives
`the polishing rates of the undoped and doped oxides.
`TABLE I
`POLISHING RATES OF UNDOPED AND DOPED OXIDES
`Type of Oxide
`Polishing Rate (KA/min)
`Undoped Oxide (TEOS)
`1-2
`Doped Oxide
`3-4
`(B: 2.6%; P: 5.7%)
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`0
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`5,314,843
`7
`will be polished faster and a smooth ?at surface 48
`(FIG. 6) is easier to obtain in the CMP process. Alterna
`tively, the entire wafer may be overlaid with BPSG as
`in the prior art, a reverse mask may be used, and nitro
`gen implanted by ion bombardment in a portion 52
`(FIG. 7) of the BPSG layer 50, driving out the boron
`and phosphorus and replacing them with nitrogen. The
`resulting silicon nitride 52 has a much slower removal
`rate in the standard oxide CMP process, and thus a
`smooth, ?at surface similar to that in FIG. 6 may be
`obtained. It is noted that in this embodiment the nitro
`gen implantation is designed so that the entire nitride
`area 52 is removed in the CMP process.
`FIG. 8 shows another preferred embodiment of the
`invention. The ?gure depicts a cross-section of a por
`tion of a DRAM in the area where a P-well 60 and an
`N-well 62 are adjacent. The parts or the DRAM struc
`ture shown include a preferably lightly p-doped silicon
`substrate 61, P-well 60, N-well 62, interlayer dielectric
`(ILD) TEOS layer 64, and BPSG layer 66. The struc
`ture of the DRAM in the P-well region 68 is much more
`complex than that in the N-well region 69. Again the
`structure in the area 67 and the actual structure of the
`doped areas in the substrate 61 is quite complex and not
`shown since the speci?c details of the structure are not
`relevant to the invention. The complexity of area 67
`results in a signi?cant height difference between the
`P-well region 68 and the N-well region 69. Again, this
`height difference has made producing a smooth, flat
`surface by the standard oxide CMP process, discussed
`in detail above, dif?cult. In the process according to the
`invention, a portion 70 of the BPSG layer 66 is con
`verted to nitride by masking and nitrogen ion bombard
`ment. This makes the removal rate in the area 70 much
`less than in the unaltered BPSG layer 66 during the
`standard oxide CMP process. The result is an smooth,
`?at surface 72 as shown in FIG. 9. Again, it is noted that
`the nitrogen implantation is designed so that the entire
`nitride area 70\is removed in the CMP process.
`The dimensions of the various layers in the embodi
`ments of the invention described above will depend on
`a wide variety of factors, including the details of the
`particular semiconductor device designs, the particular
`fabrication processes used, the choice of CMP ingredi
`ents, and the desired degree of ?atness desired in the
`?nal result. In the embodiment of FIGS. 2-3, the thick
`ness of layer 14 may range from about 0.5 pm thick (the
`vertical direction in the ?gures) to about 1.5 pm thick,
`and nominally is about 1 pm thick. For a trough 16 that
`is greater than 2 pm wide (the horizontal direction in
`the ?gures) by 0.5 pm deep, the tungsten nitride portion
`24 may range from 50% of the length of trough 16 to
`100% of trough 16, and nominally is about 80% of the
`length of trough 16, and may range from about 100A
`thick to about 2000A thick, and nominally is about
`1000A thick. For the reverse mask embodiment of FIG.
`4, the tungsten oxide portions 34 and 36 may range from
`about 1000A thick to about 5000A thick, and nominally
`is about 3000A thick. Since the preferred dimensions of
`the altered portions depend on so many variables which
`60
`cannot be anticipated in a document of this length, the
`actual dimensions chosen should be adjusted depending
`on the application and the experience of the user of the
`process. For the embodiments of FIGS. 2-4, experimen
`tal dishing curves shown in FIGS. 10A and 10B, give
`some guidance. FIG. 10A shows the effect of over
`polishing on dishing. As can be seen from the ?gure,
`dishing is negligible with no over polishing. but is signif
`
`For a difference of about 0.5 um to 1.5 pm in heights
`between the P-well region 68 and the N-well region 69
`in the embodiment of FIGS. 8 and 9, the thickness of the
`nitrogen implanted layer 79 may range from about
`500A thick° to about 3000 A thick, and nominally is
`about 1000A thick.
`The dimensions of the other parts of the invention,
`such as the silicon substrate 12, the oxide 13, area 42 in
`FIGS. 5-7, the doped area 60 and 61 (FIGS. 8 and 9),
`area 67, and TEOS layer 64 are generally known by
`those skilled in the art.
`A feature of the invention is that by using technolo
`gies readily available in the semiconductor fabrication
`art, the CMP process can be controlled to a signi?cant
`degree to produce excellent planarization in many situa
`tions where obtaining good planarization was dif?cult
`in the prior art.
`Another feature of the invention is that much of the
`data concerning the standard CMP processes is applica
`' ble to _the present invention. That is, CMP processes
`50
`have been studied for several years with the view
`towards optimizing the processes. For example there is
`much data on the relative removal rates of variations of
`the oxide CMP process, and their effect on materials
`that may be adjacent the oxide, such as nitrides. This
`information can now be applied to further optimizing
`the process of the invention.
`There has been described a novel method of design
`ing and controlling the CMP process that results in
`much better planarization and which has many other
`advantages. It should be understood that the particular
`embodiments shown in the drawings and described
`within this speci?cation are for purposes of example and
`should not be construed to limit the invention which
`will be described in the claims below. Now that a num
`ber of examples of the method of the invention have
`been given, numerous other applications are evident.
`Nearly any prior art CMP process may be improved by
`the method of the invention. Further, it is evident that
`
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`Page 9 of 11
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`those skilled in the art may now make numerous uses
`and modi?cations of the speci?c embodiment described,
`without departing from the inventive concepts. Or the
`various parts described may be made with a wide vari
`ety of dimensions and materials. A greater or lesser
`number of parts may be used. Consequently, the inven
`tion is to be construed as embracing each and every
`novel feature and n