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`Filed on behalf of Godo Kaisha IP Bridge 1
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`IPR2016-1246; IPR2016-01247
`U.S. Patent No. 7,126,174
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`____________
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`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Case IPR2016-012461
`U.S. Patent No. 7,126,174
`____________
`
`DECLARATION OF DR. E. FRED SCHUBERT, PH.D.
`IN SUPPORT OF PATENT OWNER’S RESPONSE
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`
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`1 Case IPR2016-01247 has been consolidated with this proceeding.
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`IP Bridge Exhibit 2012
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`IPR2016-1246; IPR2016-01247
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`Table of Contents
`Introduction ........................................................................................................... 1
`
`Summary Of Opinions ........................................................................................... 1
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`Background And Qualifications ............................................................................. 3
`
`Previous Expert Witness Experience .................................................................. 3
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`Compensation ..................................................................................................... 3
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`Background ........................................................................................................ 4
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`Materials Reviewed ..............................................................................................10
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`Understanding Of Claim Terms ............................................................................10
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`Legal Standards ....................................................................................................11
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`Dr. Banerjee’s Declaration ....................................................................................13
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`Technological Background ...................................................................................19
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`Acronyms ..........................................................................................................19
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`Silicon Integrated Circuit (IC) Processing .........................................................20
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`Electrical Isolation In Silicon Integrated Circuit Wafers ....................................29
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`Differences Between LOCOS Isolation And Trench Isolation ...........................35
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`LOCOS Isolation And Trench Isolation Are Not Functionally Equivalent .........37
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`Difficulties Of Employing STI On Wafers Having A Non-Planar Topology .....42
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`Benefits Of The Claimed Features Of The ‘174 Patent And Their Synergies .....50
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`Applied Prior Art ..................................................................................................60
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`U.S. Patent No. 5,153,145 (“Lee”) .....................................................................60
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`U.S. Patent No. 5,021,353 (“Lowrey”) ...............................................................66
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`U.S. Patent No. 5,539,229 (“Noble”) .................................................................75
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`U.S. Patent No. 4,506,434 (“Ogawa”) ...............................................................80
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`Overview Of Why The References Are Not Combinable ......................................86
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`Combination: Lee & Noble ...................................................................................91
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`The Initial Processing Sequence Of Noble Is Opposite From Lee ......................91
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`Lee And Noble Processes Are Not Compatible ..................................................97
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`No L-Shaped Second Sidewalls ....................................................................... 103
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`Summary ......................................................................................................... 109
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`Lee-Noble Rejection Fails On Further Grounds ............................................... 111
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`Silicidation Of Lee ....................................................................................... 111
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`Conclusions regarding the Lee-Noble combination .......................................... 113
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`Petitioner Fails To Meet Its Burden To Establish That Lee In Combination With
`Noble Renders At Least Claim 1 Unpatentable ................................................... 114
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`Combination: Lee & Ogawa ............................................................................... 115
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`Initial Processing Sequence of Ogawa Is Opposite From Lee .......................... 115
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`Lee And Ogawa Processes Are Not Compatible .............................................. 123
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`No L-Shaped Second Sidewalls ....................................................................... 127
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`Petitioner’s Proposed Silicide “Layer” Is Portrayed To Be A Small Diameter
`Circular Element (Wire or Cylinder) That Runs Along the Gate Width Of The
`Device ............................................................................................................. 130
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`Conclusions Regarding The Lee-Ogawa Combination .................................... 132
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`Petitioner Fails To Meet Its Burden To Establish That Lee In Combination With
`Ogawa Renders At Least Claim 1 Unpatentable ................................................. 133
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`Conclusions Regarding Claim 1 ...................................................................... 134
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`Dependent Claims ........................................................................................... 135
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`Lee In Combination With Noble/Ogawa Would Not Render Claim 2 And 6
`Obvious ........................................................................................................ 135
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`Lee In Combination With Noble/Ogawa Would Not Render Claim 3 And 15
`Obvious ........................................................................................................ 135
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`Lee In Combination With Noble/Ogawa Would Not Render Either Claim 5
`And 16 Obvious ........................................................................................... 135
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`Lee In Combination With Noble/Ogawa Would Not Render Claim 7, 17, And
`18 Obvious ................................................................................................... 136
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`Lee In Combination With Noble/Ogawa Would Not Render Claim 9 Obvious
` ..................................................................................................................... 137
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`Lee In Combination With Noble/Ogawa Would Not Render Claim 10 Obvious
` ..................................................................................................................... 138
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`Lee In Combination With Noble/Ogawa Would Not Render Claim 11 and 12
`Obvious ........................................................................................................ 139
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`Lee In Combination With Noble/Ogawa Would Not Render Claim 14 Obvious
` ..................................................................................................................... 141
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`Summary Of Argument ................................................................................... 141
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`Combination: Lowrey & Noble ........................................................................... 144
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`Lowrey Is Not Compatible With Trench Isolation............................................ 144
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`The Initial Processing Sequence Of Lowrey .................................................... 147
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`Trench Isolation Is Incompatible With Lowrey ................................................ 152
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`Lowrey Cannot Be Combined With Noble ....................................................... 157
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`No Second L-Shaped Sidewalls ....................................................................... 169
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`Conclusions Regarding The Lowrey-Noble Combination ................................ 176
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`Petitioner Fails To Meet Its Burden To Establish That Lowrey In Combination
`With Noble Renders At Least Claim 1 Unpatentable ....................................... 177
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`Combination: Lowrey And Ogawa ...................................................................... 178
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`Initial Processing Sequence Of Ogawa ............................................................ 179
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`The Petition Fails To Describe How Lowrey Could Be Combined With Ogawa
`To Render The Challenged Claims Unpatentable ............................................ 181
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`Lowrey And Ogawa Do Not Suggest L-Shaped Sidewalls ............................... 186
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`Summary ......................................................................................................... 188
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`Petitioner Fails To Meets Its Burden To Establish That A POSITA Would
`Combine Lowrey with Ogawa ......................................................................... 189
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`Conclusions Regarding The Lowrey-Ogawa Combination .............................. 193
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`Petitioner Fails To Meet Its Burden To Establish That Lowrey In Combination
`With Ogawa Renders At Least Claim 1 Unpatentable ........................................ 194
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`Nothing Suggests That L-Shaped Sidewalls Would Form On The
`Interconnection ................................................................................................ 195
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`Conclusions Regarding Claim 1 ...................................................................... 197
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`Dependent Claims ........................................................................................... 200
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`Lowrey In Combination With Noble/Ogawa Would Not Render Claims 4, 5, 8,
`And 16 Obvious ........................................................................................... 200
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`Lowrey In Combination With Noble/Ogawa Would Not Render Claims 9 And
`10 Obvious ................................................................................................... 200
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`Lowrey In Combination With Noble/Ogawa Would Not Render Claims 11
`And 12 Obvious ........................................................................................... 200
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`Lowrey In Combination With Noble/Ogawa Would Not Render Claim 14
`Obvious ........................................................................................................ 202
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`Summary Of Argument ................................................................................... 203
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`I, E. Fred Schubert, declare as follows:
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`Introduction
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`IPR2016-1246; IPR2016-01247
`U.S. Patent No. 7,126,174
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`1.
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` My name is Dr. E. Fred Schubert. I have been asked to submit this
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`declaration on behalf of Godo Kaisha IP Bridge 1 (“IP Bridge” or “Patent Owner”)
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`in connection with a Petition for Inter Partes Review of U.S. Patent No. 7,126,174
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`(“the ’174 patent”), which I understand was submitted to the Patent Trial and
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`Appeal Board of the United States Patent and Trademark Office by petitioner
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`Taiwan Semiconductor Manufacturing Company Ltd. (“TSMC”).
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`2.
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`I have been retained as a technical expert by IP Bridge to study and
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`provide my opinions on the technology claimed in, and the patentability or non-
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`patentability of, claims 1-3, 5-7, 9-12, and 14-18 in the ’174 patent (“the
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`Challenged Claims”).
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`3.
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`I understand the ’174 patent is related to U.S. Patent Nos. 6,967,409
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`(the ’409 patent), 6,709,950 (the ’950 patent), and 6,281,562 (the ’562 patent) and
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`also claims the benefit of priority to two Japanese applications, JP 7-192181,
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`which was filed on July 27, 1995, and JP 7-330112, which was filed on December
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`19, 1995.
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`Summary Of Opinions
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`4.
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`I have reviewed the ’174 patent, associated prior art, the TSMC
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`Petition, the Declaration of Dr. Banerjee, as well as references cited therein. I
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`understand that the Petitioner and its expert, Dr. Banerjee, express the following
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`contentions:
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`5.
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`First, Petitioner and its expert contend that LOCOS isolation and
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`trench isolation are interchangeable and one could simply substitute LOCOS
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`isolation with trench isolation.
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`6.
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`Second, Petitioner and its expert offer four combinations, (1) Lee and
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`Noble, (2) Lee and Ogawa, (3) Lowrey and Noble, (4) Lowrey and Ogawa, and
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`contend that the substitution of Lee’s LOCOS isolation or Lowrey’s LOCOS
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`isolation, with either Noble’s or Ogawa’s trench isolation would result in the
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`claimed invention of the ’174 patent.
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`7.
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`Based on my experience and knowledge in the field and based on my
`
`review of the documents, I express my opinions as follows:
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`8.
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`First, it is my opinion that LOCOS isolation and trench isolation are
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`substantially different structures thereby requiring that their fabrication processes
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`as well as the processes that they are integrated into must be modified substantially
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`when transitioning from LOCOS isolation to trench isolation.
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`9.
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`Second, it is my opinion that a simple substitution of LOCOS isolation
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`with trench isolation, without a detailed re-engineering of a fabrication process, is
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`generally not obvious, not possible, and if done nonetheless, would result in a non-
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`working Si IC device.
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`10. Accordingly, it is my opinion that the ’174 patent is not obvious based
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`on the prior art asserted by Petitioner and its expert. That is, the ’174 patent is not
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`obviated by the Lee and Noble, Lee and Ogawa, Lowrey and Noble, or Lowrey and
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`Ogawa combinations.
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`Background And Qualifications
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`Previous Expert Witness Experience
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`11.
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`I have served as a technical expert witness since the late 1990s. My
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`expert activity included semiconductor materials, processing, devices, packaging,
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`and systems. I have worked on behalf of Plaintiffs and Defendants, on behalf of
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`domestic companies and foreign companies, and in proceedings at the USPTO
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`(including inter partes reviews), District Court, and the International Trade
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`Commission (ITC). My work included mostly utility patent cases, but also
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`included design patent cases, a case of alleged misappropriation of a trade secret,
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`and a case of alleged mishandling of a patent application.
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`Compensation
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`12.
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`I am compensated at my customary rate of $500 per hour worked on
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`the case plus reasonable and customary expenses. My compensation does not
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`depend on the outcome of the inter partes review.
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`Background
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`13.
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`I am currently a Professor in the Department for Electrical, Computer,
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`and Systems Engineering at the Rensselaer Polytechnic Institute (RPI) located in
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`Troy, New York.
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`14.
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`I received a Master’s Degree in Electrical Engineering from the
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`University of Stuttgart, Germany, in 1981. While working towards my Master’s
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`Degree in Electrical Engineering, I had hands-on experience working in a silicon
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`IC fabrication facility, working on silicon integrated piezo-resistive sensors. I
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`received a Ph.D. degree in Electrical Engineering from the University of Stuttgart,
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`Germany, in 1986. While working towards my Ph.D., in 1982, I worked as a
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`summer intern at IBM’s silicon integrated circuit fabrication facility in Böblingen,
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`Germany. In this capacity, my work specifically focused on photolithography and
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`mask design. My dissertation was titled “Modern Schottky Gate Field Effect
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`Transistor Devices Made of III-V Semiconductors.” Subsequent to my education,
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`starting in 1985, I worked in industry, at AT&T Bell Laboratories in Holmdel and
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`Murray Hill, New Jersey, for ten years. The transistor was invented at Bell Labs (in
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`1949) and the Labs were subsequently recognized as one of the world’s premier
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`industrial research laboratories. From 1990-1995, while at AT&T Bell Labs, I
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`worked in the silicon integrated circuit fabrication facility. This facility was
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`nicknamed “Blue Zoo” fabrication facility and was located in Murray Hill, New
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`Jersey. While working in this facility, my work focused on the doping of silicon,
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`on the demonstration of shallow junctions, and on the design and fabrication of
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`silicon MOSFETs, including LDD MOSFETs that employ gate sidewall spacers
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`for a better control of the dopant distribution.
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`15.
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`In 1995, I joined academia. My first position was at Boston University
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`(Boston MA) where I worked as a full professor for seven years. In 2002, I joined
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`RPI as a distinguished professor, the Wellfleet Senior Constellation Professor, with
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`appointments
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`in
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`the Department for Electrical, Computer, and Systems
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`Engineering and the Department for Physics, Applied Physics, and Astronomy. I
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`served as Head of the Future Chips Constellation from 2002 to 2015. Furthermore,
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`I am the founding Director of the Smart Lighting Engineering Research Center,
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`which is funded by the US National Science Foundation at $40 million over 10
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`years.
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`16.
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`I am co-inventor of more than 30 U.S. patents and have co-authored
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`more
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`than 300 publications.
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`I authored
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`the books “Doping
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`in
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`III–V
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`Semiconductors” (1993), “Delta Doping of Semiconductors” (1996), and the first
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`and second editions of “Light-Emitting Diodes” (2003 and 2006). My publications
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`have been well recognized by the technical community as illustrated by the more
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`than 25,000 citations that my publications have received. The high number of
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`citations shows the recognition of my research accomplishments and puts me in the
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`top 1% of researchers in the field of semiconductors.
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`17.
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`I have received several awards for my technical contributions. They
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`include: Senior Member IEEE (1993); Literature Prize of Verein Deutscher
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`Elektrotechniker for book “Doping in III–V semiconductors” (1994); Fellow SPIE
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`(1999); Alexander von Humboldt Senior Research Award (1999); Fellow IEEE
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`(1999); Fellow OSA (2000); Boston University Provost Innovation Award (2000);
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`Discover Magazine Award for Technological Innovation (2000); R&D 100 Award
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`for RCLED (2001); Fellow APS (2001); RPI Trustees Award for Faculty
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`Achievement (2002 and 2008); Honorary membership in Eta Kappa Nu (2004); 25
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`Most Innovative Micro- and Nano-Products of the Year Award of R&D Magazine
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`(2007); and the Scientific American 50 Award (2007).
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`18. My general expertise is in the field of electrical engineering and
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`applied physics with a particular emphasis on semiconductor devices,
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`semiconductor materials, semiconductor processing, and semiconductor device
`
`packaging. I have worked in semiconductor processing facilities, including
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`facilities dedicated to silicon integrated circuit (IC) processing, for many years
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`starting in 1980. I have numerous documented contributions to the field of
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`semiconductor doping including the fabrication and analysis of ultra-shallow
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`junctions in silicon, namely delta-function-like doping profiles that are deposited
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`with near-atomic precision. These doping profiles are more precise than what is
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`currently attainable with ion implantation. At the present time, doping by ion
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`implantation is the dominant doping technique in the silicon IC industry. I have
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`also taught courses on silicon integrated circuit technology. This includes teachings
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`at RPI and Boston University. My teachings concern the theory of silicon
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`integrated circuits as well as the fabrication of silicon integrated circuits, including
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`silicon MOSFETs, LDD MOSFETs, HKMG MOSFETs, LDMOS FETs,
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`FINFETs, and GAAFETs2. The courses that I taught include practical hands-on
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`laboratory sections.
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`19. Furthermore, I have made pioneering contributions to the field of
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`porous silica thin films (porous SiO2 thin films) deposited by oblique-angle
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`deposition. These highly porous silica films, whose porosity can be as high as
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`90%, are highly desirable for high-speed interconnects in silicon ICs due to the low
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`dielectric constant (“low k”) of these materials and the resulting low capacitance of
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`interconnect wires using interlayer dielectrics made of porous silica. My research
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`also included the theoretical study, experimental verification, and the application
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`
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`2 LDD = Low-doped drain; HKMG = High k metal gate; LDMOS = Laterally
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`diffused metal oxide semiconductor; FINFET = Fin-shaped FET; GAAFET = Gate
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`all around FET
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`of the piezo-resistive coefficients of thin silicon membranes that are subjected to a
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`mechanical stress and strain. My research contributions also include the use of
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`delta-doped silicon for MOSFET applications for ultra-shallow junctions. Delta-
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`doped silicon MOSFETs possess ultra-shallow junctions. Indeed, these junctions
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`are the shallowest junctions attainable (delta-doped junctions are shallower than
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`ion-implanted junctions). That is, I (along with my collaborators) demonstrated the
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`shallowest junctions in silicon.
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`20. At my home institution, Rensselaer Polytechnic Institute (RPI), I
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`teach on the subject of silicon microelectronics on a regular basis. The teaching
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`includes undergraduate and graduate courses. The subject matter includes silicon
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`metal-oxide-semiconductor field effect transistors (MOSFETs), complementary
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`metal-oxide-semiconductor (CMOS) technology, constant-electric-field scaling,
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`the theory of transistors and integrated circuits, and the fabrication of integrated
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`circuits. I am well versed in the theory and the physics of semiconductor devices
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`and associated electrical circuits. In addition, I regularly work with students and
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`staff of a silicon microfabrication clean room facility at my home institution (RPI).
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`Several of my former Ph.D. and Master students have worked or are currently
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`working in the silicon integrated circuit industry including the following
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`companies: IBM Company in Fishkill NY, Global Foundry Company in Malta NY,
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`Albany Nanotech in Albany NY, Micron Company in Boise Idaho, and Intel
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`Company in Boise Idaho.
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`21. My experience includes the operation, modeling, driving, design,
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`fabrication, and analysis of solid-state devices and integrated electrical circuits. I
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`am the inventor on patents that concern silicon semiconductor devices, including
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`the doping of silicon. My experience includes the employment and operation of
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`various analysis techniques including SEM (scanning electron microscopy), TEM
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`(transmission electron microscopy), EDXS (energy dispersive x-ray spectroscopy
`
`also called EDS or EDX), EELS (electron energy loss spectroscopy), and SIMS
`
`(secondary ion mass spectrometry).
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`22.
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`I have consulted for companies in the semiconductor industry,
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`including the semiconductor processing industry. Specifically, I have consulted for
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`Varian Company in Gloucester, Massachusetts (now part of Applied Materials
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`Company) and for Micron Technologies in Boise, Idaho. In my capacity as a
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`consultant, I visited these companies multiple times and on a regular basis. My
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`consulting has allowed the companies to enhance their understanding of
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`semiconductor devices and take advantage of the technological advancements
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`made in academia including my research laboratory and the microfabrication
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`facility at RPI.
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`23. More details about my experience and background are included in my
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`curriculum vitae, attached as Appendix A to my report.
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`Materials Reviewed
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`24.
`
`I have reviewed the following documents:
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`• The ’174 patent and its file history
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`• US patent 6,281,562 and its file history
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`• US patent 6,709,950 and its file history
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`• US patent 6,967,409 and its file history
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`• The TSMC Petition and references cited therein
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`• Dr. Banerjee’s expert declaration and references cited therein
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`• Various technical articles and patents cited herein and in Patent
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`Owner’s Response
`
`Understanding Of Claim Terms
`
`25.
`
` I understand that in a pending litigation involving the ’174 patent
`
`(Case No. 2:16-cv-00134-JRG-RSP (E.D. Tex Feb 14, 2016)), the Court has
`
`construed certain terms in the claims of the ’174 patent. In forming the opinions
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`stated in this report, I have assumed the constructions of those terms as provided
`
`by the Court’s Order (the “Order”). Dkt. No. 105. Exhibit 3001. In the claim
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`construction order, the following terms of the ’174 patent were given the following
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`constructions:
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`Claim Term
`“a trench isolation region surrounding
`
`Construction
`Plain meaning
`
`an active area of a semiconductor
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`substrate” (claim 1)
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`“first silicide layers formed on regions
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`“first silicide layers formed on regions
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`located on the sides of the first L-
`
`that are within the active area and
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`shaped sidewalls within the active area”
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`located on the sides of the first L-
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`(Claim 1)
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`shaped sidewalls”
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`“L-shaped sidewalls” (Claims 1, 14)
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`“sidewalls that substantially resemble a
`
`capital letter ‘L’ or its mirror image”
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`“surface of the active area” (Claims 9,
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`“top of the active area”
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`10)
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`“a lower portion of the interconnection
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`“a
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`bottom
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`surface
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`of
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`the
`
`provided on the upper surface of the
`
`interconnection provided on the upper
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`trench isolation is located higher than
`
`surface of the trench isolation is located
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`the surface of the active area” (Claim
`
`higher than the surface of the active
`
`10)
`
`area”
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`“composed of
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`the same material”
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`Plain and ordinary meaning
`
`(Claim 11)
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`“made of the same insulating film”
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`“made of the same insulating material”
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`
`See Exhibit 3001, Appendix A.
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`Legal Standards
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`26.
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`I am not a lawyer. Counsel for IP Bridge has advised me regarding the
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`legal principles governing patent
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`understanding is as follows below.
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`IPR2016-1246; IPR2016-01247
`U.S. Patent No. 7,126,174
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`law. Based on counsel’s advice, my
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`27.
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`In an IPR proceeding, the Petitioner has the initial burden of
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`persuasion to establish a reasonable likelihood that at least one claim of an issued
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`patent are unpatentable, and this burden remains throughout the entire proceeding
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`28. Petitioner must provide an analysis of how or why an element from a
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`prior art teaching could be combined with the teaching of another reference
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`29. A person of ordinary skill in the art (POSITA) at the time the
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`application leading to the ’174 patent was filed would have at least a Bachelor’s
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`degree in Electrical, Materials, Mechanical, or Chemical Engineering, or a related
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`degree, and at least two years of experience working in semiconductor processing
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`and fabrication, semiconductor equipment manufacturing, or semiconductor
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`materials. Integrated circuit (IC) design is different from IC processing and
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`fabrication. It is one thing to have a theoretical understanding of circuit design, but
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`quite another to be familiar with the problems associated with the IC fabrication
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`process. Without any direction by Petitioner how or why a feature is to be
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`combined, a naked assertion that such would be within the skill of a POSITA is
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`not enough to establish a reasonable likelihood that at least one claim of an issued
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`patent is unpatentable in an IPR proceeding.
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`30. Although the POSITA is entitled to use “common sense” to arrive at
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`the conclusion that the claimed invention is obvious, the POSITA must provide a
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`IPR2016-1246; IPR2016-01247
`U.S. Patent No. 7,126,174
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`reasoned explanation that avoids conclusory generalizations.
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`31. An assertion of invalidity cannot be based merely on conclusory
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`statements when dealing with prior art, but must set forth the rationale on which it
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`relies.
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`32. For an invention to be obvious it is not enough that there be a reason
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`to combine individual elements from different prior art references; the POSITA
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`must also be in possession of sufficient knowledge to know how to incorporate
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`features from one reference into the other reference.
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`33. Petitioner’s expert relies on the following Legal Standard:
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`A person of ordinary skill often will be able to fit the teachings of
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`multiple references together like a puzzle;
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`Exhibit 1004, ¶37(f).
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`34.
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`I understand this to not be a generalized starting point in every
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`analysis because it entirely fails to take into account the specific technology, the
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`complexity of the technology, certain constraints associated with the technology,
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`and the specific documents being relied upon and which are being combined.
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`Dr. Banerjee’s Declaration
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`35.
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`I have reviewed Dr. Banerjee’s Declaration to see how he addresses
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`the issue if it would be possible to fabricate the combinations of elements that he
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`proposes would be obvious to combine. I note that he stated the following:
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`IPR2016-1246; IPR2016-01247
`U.S. Patent No. 7,126,174
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`a.
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`Ogawa also discusses how to implement this trench
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`isolation with “a series of ordinary steps available in the prior
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`art” that “are employed for production of sources and drains 58,
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`an inter-layer insulating layer 59 and an upper layer wiring 60
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`for the ultimate purpose of producing a MOS IC.” (Ogawa at
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`8:3–7.)
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`Exhibit 1004, ¶79.
`b. Moreover, a person of ordinary skill in the art would
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`have understood that replacing Lee’s LOCOS with Noble’s STI
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`would have been entirely compatible and had no impact on the
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`processes used for gate formation, source/drain formation, L-
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`shaped sidewall formation, silicide formation, or any other
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`aspect of the claims. LOCOS and STI are both methods for
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`forming insulating materials in the same locations of the
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`substrate to perform the same function. They are both
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`performed near the very beginning in device processing, and
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`how the isolation regions are formed would not affect Lee’s
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`processes or the resultant device structures. It is therefore my
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`opinion that the combined teachings of Lee and Noble render
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`the Challenged Claims obvious. (emphasis applied)
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`Exhibit 1004, ¶82.
`c. Moreover, a person of ordinary skill in the art would
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`have understood that replacing Lee’s LOCOS with Ogawa’s
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`trench isolation would have been entirely compatible and had
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`no
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`impact on
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`the processes used for gate formation,
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`IPR2016-1246; IPR2016-01247
`U.S. Patent No. 7,126,174
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`source/drain formation, L-shaped sidewall formation, silicide
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`formation, or any other aspect of the claims. LOCOS and trench
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`isolation are both methods for forming insulating materials in
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`the same locations of the substrate to perform the same
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`function. They are both performed near the very beginning in
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`device processing, and how the isolation regions are formed
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`would not affect Lee’s processes or the resultant device
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`structures. (emphasis applied)
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`Exhibit 1004, ¶198.
`d.
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`Other references further demonstrate that replacing Lee’s
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`LOCOS with Ogawa’s trench isolation would have constituted
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`a simple substitution of one known element for another
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`according to known methods to achieve predictable results.
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`Exhibit 1004, ¶201
`e.
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`Ogawa also discusses how to implement this trench
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`isolation with “a series of ordinary steps available in the prior
`
`art” that “are employed for production of sources and drains 58,
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`an inter-layer insulating layer 59 and an upper layer wiring 60
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`for the ultimate purpose of producing a MOS IC. (Ogawa at
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`8:3–7.)
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`Exhibit 1024, ¶78.
`f. Moreover, a person of ordinary skill in the art would
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`have understood that replacing Lowrey’s LOCOS with Noble’s
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`STI would have been entirely compatible and had no impact on
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`the processes used for gate formation, source/drain formation,
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`L-shaped sidewall formation, s