`U.S. Patent No. 7,126,174
`
`Filed on behalf of Godo Kaisha IP Bridge 1
`By: Neil F. Greenblum (ngreenblum@gbpatent.com)
`
`Greenblum & Bernstein, P.L.C.
`
`1950 Roland Clarke Place
`
`Reston, VA 20191
`
`Tel: 703-716-1191
`
`Fax: 703-716-1180
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
`and GLOBALFOUNDRIES U.S. INC.,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Case IPR2016-012461
`U.S. Patent No. 7,126,174
`____________
`
`PATENT OWNER’S CURRENT EXHIBIT LIST
`(As of February 1, 2018)
`
`
`Mail Stop PATENT BOARD, PTAB
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`1 Case IPR2016-01247 has been consolidated with this proceeding.
`GlobalFoundries U.S. Inc.’s motions for joinder in Cases IPR2017-00925 and
`IPR2017-00926 were granted.
`
`
`
`
`
`PATENT OWNER’S CURRENT EXHIBIT LIST
`(As of February 1, 2018)
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`
`Exhibit
`No.
`
`Description
`
`2001
`
`2002
`
`2003
`
`2004
`
`Substitute Declaration of Dr. E. Fred Schubert,
`Ph.D. in support of Patent Owner’s Preliminary
`Response filed in IPR2016-01246 on October 5,
`2016.
`
`Schematic illustration of the Chemical Mechanical
`Polishing process from Steigerwald, Murarka, and
`Gutmann, Chemical Mechanical Planarization of
`Microelectronic Materials (1997).
`
`Schematic illustration of the Chemical Mechanical
`Polishing process from the Motorola Company.
`SCSolutions.com. Accessed September 30, 2016.
`http://www.scsolutions.com/chemical-mechanical-
`planarization-cmp-controllers-0.
`
`Photograph of a Chemical Mechanical Polishing
`Tool from the Applied Materials Company.
`BusinessWire.com. Accessed October 5, 2016.
`http://www.businesswire.com/news/home/20040711
`005007/en/Applied-Materials-Revolutionizes-
`Planarization-Technology-Breakthrough-Reflexion.
`
`2005
`
`Troxel, Boning, McIlrath “Semiconductor Process
`Representation.” Wiley Encyclopedia of Electrical
`and Electronics, pp.139 –147 (1999).
`
`2006
`
`U.S. Patent No. 6,052,319 to Jacobs.
`
`2007
`
`U.S. Patent No. 6,952,656 to Cordova et al.
`
`Newly
`Submitted
`
`Served on
`January 27,
`2017
`
`
`
`
`
`
`
`
`
`
`
`
`
`1
`
`
`
`Description
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`
`Newly
`Submitted
`
`Hunt, “Low Budget Undergraduate
`Microelectronics Laboratory.” University
`Government Industry Microelectronics Symposium,
`pp.81-87 (2006).
`
`
`
`Exhibit
`No.
`
`2008
`
`2009
`
`U.S. Patent No. 7,074,709 to Young.
`
`Burckel, “3D-ICs created using oblique processing.”
`Advanced in Patterning Materials and Processes
`XXXIII, pp. 1–12 (2016).
`
`Substitute Declaration of Dr. E. Fred Schubert,
`Ph.D. in support of Patent Owner’s Preliminary
`Response filed in IPR2016-01247 on October 7,
`2016.
`
`Served on
`January 27,
`2017
`
`Corrected Declaration of Dr. E. Fred Schubert,
`Ph.D. in support of Patent Owner’s Response filed
`in IPR2016-01246 on March 24, 2017.
`
`Thompson, L. F. “An Introduction to Lithography.”
`Introduction to Microlithography, ACS Symposium
`Ser., American Chemical Society, pp. 1-13 (1983).
`
`2010
`
`2011
`
`2012
`
`2013
`
`2014
`
`CA1275846 C to Roland et al.
`
`2015
`
`U.S. Patent No. 5,314,843 to Yu et al.
`
`2016
`
`U.S. Patent No. 5,231,306 to Meikle et al.
`
`2017
`
`U.S. Patent No. 4,529,621 to Ballard.
`
`2018
`
`U.S. Patent No. 5,310,624 to Ehrlich.
`
`2019
`
`U.S. Patent No. 5,097,422 to Corbin, II et al.
`
`2020
`
`Declaration of Amanda Dove.
`
`2021
`
`U.S. Patent No. 4,952,524 to Lee et al.
`
`2
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Description
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`
`Newly
`Submitted
`
`
`
`
`
`
`
`
`
`
`
`
`
`Exhibit
`No.
`
`2022
`
`2023
`
`2024
`
`2025
`
`2026
`
`Bryant, A.; Haensch, W.; Geissler, S; Mandelman,
`Jack; Poindexter, D.; and Steger, M. “The Current-
`Carrying Corner Inherent to Trench Isolation.”
`IEEE Electron Device Letters, Vol. 14, No. 8, pp.
`412-414 (1993).
`
`Ohe, Kikuyo; Odanaka, Shinji; Moriyama, Kaori;
`Hori, Takashi; and Fuse, Genshu. “Narrow-Width
`Effects of Shallow Trench-Isolated CMOS with n+-
`Polysilicon Gate.” IEEE Transactions on Electron
`Devices, Vol. 36, No. 6, pp. 1110-1116 (1989).
`
`Shigyo, N.; Wada, T.; Fukuda, S.; Hieda, K.,
`Hamamoto, T.; Watanabe, H.; Sunouchi, K.; and
`Tango, H. “Steep Subthreshold Characteristic and
`Enhanced Transconductance of Fully-Recessed
`Oxide (Trench) Isolated 1/4 µm Width MOSFETs.”
`1987 International Electron Devices Meeting, pp.
`636-639 (1987).
`
`Furukawa, T., and Mandelman, J.A. “Process and
`Device Simulation of Trench Isolation Corner
`Parasitic Device.” Journal Of The Electrochemical
`Society, Vol. 135, No. 8, p. 358C, Item 236 (1988).
`
`“Structural Analysis Sample Report” downloaded
`from
`https://www.chipworks.com/TOC/Structural_Analy
`sis_Sample_Report.pdf (2013).2
`
`2027
`
`U.S. Patent No. 4,776,922 to Bhattacharyya et al.
`
`
`
`2 Date corrected from 2008 to 2013.
`
`3
`
`
`
`Exhibit
`No.
`
`Description
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`
`Newly
`Submitted
`
`Subbanna, S.; Ganin, E.; Crabbé, E.; Comfort, J.;
`Wu, S.; Agnello, P.; Martin, B.; McCord, M.;
`Newman, H. Ng. T.; McFarland, P.; Sun, J.; Snare,
`J.; Acovic, A.; Ray, A.; Gehres, R.; Schulz, R.;
`Greco, S.; Beyer, K.; Liebmann, L.; DellaGuardia,
`R.; Lamberti, A. “200 mm Process Integration for a
`0.15 µm Channel-Length CMOS Technology Using
`Mixed X-Ray / Optical Lithography.” Proceedings
`of 1994 IEEE International Electron Devices
`Meeting, pp. 695-698 (1994).
`
`Chung, J.; Jeng, M.-C.; Moon, J.E.; Wu, A.T.;
`Chan, T.Y.; Ko, P.K.; Hu, Chenming. “Deep-
`Submicrometer MOS Device Fabrication Using a
`Photoresist-Ashing Technique.” IEEE Electron
`Device Letters, Vol. 9. No. 4, pp. 186-188 (1988).
`
`Tanaka, Tetsu; Suzuki, Kunihiro; Horie, Hiroshi;
`Sugii, Toshihiro. “Ultrafast Low-Power Operation
`of p+-n+ Double-Gate SOI MOSFETS.” 1994
`Symposium on VLSI Technology Digest of Technical
`Papers, pp. 11-12 (1994).
`
`2028
`
`2029
`
`2030
`
`2031
`
`WIPO Publication No. WO 90/05377 to Lowrey.
`
`2032
`
`Kaufman, F. B.; Thompson, D. B.; Broadie, R. E.;
`Jaso, M. A.; Guthrie, W. L.; Pearson, D. J.; and
`Small, M. B. “Chemical‐Mechanical Polishing for
`Fabricating Patterned W Metal Features as Chip
`Interconnects.” Journal of The Electrochemical
`Society, Vol. 138, No. 11, pp. 3460-3465 (1991).
`
`
`
`
`
`
`
`
`
`
`
`4
`
`
`
`Exhibit
`No.
`
`Description
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`
`Newly
`Submitted
`
`2033
`
`2034
`
`2035
`
`2036
`
`2037
`
`2038
`
`2039
`
`2040
`
`2041
`
`Landis, H.; Burke, P.; Cote, W.; Hill, W.; Hoffman,
`C.; Kaanta, C.; Koburger, C.; Lange, W.; Leach, M.;
`and Luce, S. “Integration of chemical-mechanical
`polishing into CMOS integrated circuit
`manufacturing.” Thin Solid Films, Vol. 220, No. 1-
`2, pp.1-7 (1992).
`
`Library of Congress Catalog Record of
`Steigerwald, Murarka, and Gutmann, Chemical
`Mechanical Planarization of Microelectronic
`Materials (1997).
`
`Library of Congress Catalog Record of Introduction
`to Microlithography, ACS Symposium Ser.,
`American Chemical Society (1983).
`
`Library of Congress Catalog Record of IEEE
`Electron Device Letters, Vol. 14, No. 8 (1993).
`
`Library of Congress Catalog Record of IEEE
`Transactions on Electron Devices, Vol. 36, No. 6
`(1989).
`
`Front cover and table of contents of 1987
`International Electron Devices Meeting (1987).
`
`Front cover of Proceedings of 1994 IEEE
`International Electron Devices Meeting (1994).
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Amended version of Exhibit 2026 - “Structural
`Analysis Sample Report” downloaded from
`https://www.chipworks.com/TOC/Structural_Analy
`sis_Sample_Report.pdf (2013).
`
`Served on
`April 14,
`2017
`
`Russell, Phillip E. “SEM-Based Characterization
`Techniques.” Mat. Res. Soc. Symp. Proc., Vol. 69,
`pp.15-22 (1986).
`
`Served on
`April 14,
`2017
`
`5
`
`
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`
`Exhibit
`No.
`
`Description
`
`2042
`
`Front cover and table of contents of Mat. Res. Soc.
`Symp. Proc., Vol. 69 (1986).
`
`Russell, Phillip E. “SEM Based Characterization
`Techniques for Semiconductor Technology.”
`Spectroscopic Characterization Techniques for
`Semiconductor Technology, Vol. 452, pp.183-189
`(1983).
`
`Front cover and table of contents of Spectroscopic
`Characterization Techniques for Semiconductor
`Technology, Vol. 452 (1983).
`
`Served on
`April 14,
`2017
`
`Thorton, P.R.; Davies, I.G.; Shaw, D.A.; Sulway,
`D.V.; Wayte, R.C. “Device Failure Analysis By
`Scanning Electron Microscopy.” Microelectronics
`and Reliability, Vol. 8, pp. 33-53 (1969).
`
`2046
`
`Front cover and table of contents of
`Microelectronics and Reliability, Vol. 8 (1969).
`
`Newly
`Submitted
`
`Served on
`April 14,
`2017
`
`Served on
`April 14,
`2017
`
`Served on
`April 14,
`2017
`
`Served on
`April 14,
`2017
`
`Served on
`April 14,
`2017
`
`2043
`
`2044
`
`2045
`
`2047
`
`2048
`
`Pabbisetty, S.V.; Gavisetty, Kumar; Vaughan,
`Steve; Wills, Kendall Scott. “Electron beam testing
`and its application to VLSI technology.”
`Characterization of Very High Speed
`Semiconductor Devices & Integrated Circuits, Vol.
`795, pp.166-177 (1987).
`
`Front cover and table of contents of
`Characterization of Very High Speed
`Semiconductor Devices & Integrated Circuits, Vol.
`795, (1987).
`
`Served on
`April 14,
`2017
`
`6
`
`
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`
`Exhibit
`No.
`
`2049
`
`2050
`
`Description
`
`Wolfgang, Eckhard; Lindner, Rudolf; Fazekas,
`Peter; Feuerbaum, Hans-Peter. “Electron-Beam
`Testing of VLSI Circuits.” IEEE Journal of Solid-
`State Circuits, Vol. SC-41. No. 2, pp. 471-
`481(1979).
`
`Newly
`Submitted
`
`Served on
`April 14,
`2017
`
`Front cover and table of contents of IEEE Journal of
`Solid-State Circuits, Vol. SC-41. No. 2, pp. 471-
`481(1979).
`
`Served on
`April 14,
`2017
`
`2051
`
`Front cover and table of contents of IEEE Electron
`Device Letters, Vol. 9. No. 4 (1988).
`
`Served on
`April 14,
`2017
`
`Front cover and table of contents of 1994
`Symposium on VLSI Technology Digest of Technical
`Papers (1994).
`
`Served on
`April 14,
`2017
`
`Front cover and table of contents of Journal of The
`Electrochemical Society, Vol. 138, No. 11, pp.
`3460-3465 (1991).
`
`Served on
`April 14,
`2017
`
`Served on
`April 14,
`2017
`
`Served on
`April 14,
`2017
`
`Served on
`April 14,
`2017
`
`2052
`
`2053
`
`2055
`
`2056
`
`2057
`
`2054
`
`Front cover and table of contents of Thin Solid
`Films, Vol. 220, No. 1-2, pp.1-7 (1992).
`
`Exhibit 2012 - Declaration of Dr. E. Fred Schubert,
`Ph.D. in support of Patent Owner’s Response filed
`in IPR2016-01246 on March 24, 2017 with
`amended CV.
`
`Amended Exhibit 2020 - Declaration of Amanda
`Dove.
`
`Transcript of Conference Call conducted on June
`20, 2017
`
`
`
`7
`
`
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`
`Exhibit
`No.
`
`Description
`
`2058
`
`Drawing by Dr. Sanjay Kumar Banerjee
`
`2059
`
`U.S. Patent No. 5,945,715 to Kuriyama
`
`2060
`
`European Patent Application No. EP 0 739 032 to
`Park et al.
`
`2061
`
`U.S. Patent No. 6,281,562 to Segawa et al.
`
`2062
`
`First and Last Pages of JP H9-172063
`
`2063
`
`Verified English Translation of First and Last Pages
`of JP H9-172063
`
`2064
`
`First and Last Pages of JP H9-97838
`
`2065
`
`Verified English Translation of First and Last
`Pages of JP H9-97838
`
`2066
`
`First and Last Pages of JP H9-120964
`
`2067
`
`Verified English Translation of First and Last Pages
`of JP H9-120964
`
`2068
`
`Patent Assignment Abstract of Title for 08-571,131
`
`2069
`
`Recorded Assignment assigning the 08-571,131
`application
`
`2070
`
`Recorded Assignment assigning 08-685,726
`
`2071
`
`Recorded Assignment assigning the 08-685,726
`application
`
`8
`
`Newly
`Submitted
`
`Provided
`on June 27,
`2017
`
`Provided
`on June 27,
`2017
`
`Provided
`on June 27,
`2017
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Exhibit
`No.
`
`Description
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`
`Newly
`Submitted
`
`2072
`
`Patent Assignment Abstract of Title for 08-340,341
`
`2073
`
`Recorded Assignment assigning the 08-340,341
`application
`
`2074
`
`Executed Declaration of Mr. Hajime Ogawa
`
`2075
`
`U.S. Patent No. 6,709,950 to Segawa et al.
`
`2076
`
`U.S. Patent No. 6,967,409 to Segawa et al.
`
`2077
`
`2078
`
`Order Granting Joint Motion To Dismiss All Claims
`And Counterclaims With Prejudice, Godo Kaisha IP
`Bridge 1 v. Broadcom Limited et al., USDC EDTEX
`2:16-cv-00134-JRG-RSP, Document 337, July 5,
`2017.
`
`Deposition Transcript of Dr. Sanjay K. Banerjee
`dated June 27, 2017 and Errata Sheet (dated June
`28, 2017) from the Deposition of Dr. Sanjay K.
`Banerjee
`
`2079
`
`Patent Owner’s Demonstrative Exhibit
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`2080
`
`Email dated August 14, 2017 from Neil Greenblum
`to PTAB regarding submission of decision in
`IPR2016-00394.
`
`X
`
`
`
`9
`
`
`
`Dated: February 1, 2018
`
`Respectfully submitted,
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`/Neil F. Greenblum /
`Neil F. Greenblum
`Registration No. 28,394
`Greenblum & Bernstein, P.L.C.
`1950 Roland Clarke Place
`Reston, Virginia 20191
`Tel: 703-716-1191
`Fax: 703-716-1180
`Email: ngreenblum@gbpatent.com
`
`Attorney for Patent Owner,
`GODO KAISHA IP Bridge 1
`
`10
`
`
`
`IPR2016-01246
`U.S. Patent No. 7,126,174
`CERTIFICATE OF SERVICE
`
`
`
`The undersigned hereby certifies that a true copy of the foregoing:
`
`PATENT OWNER’S CURRENT EXHIBIT LIST
`(As of February 1, 2018)
`
`and Exhibit 2080 was served by electronic mail on this 1st day of February, 2018,
`
`upon Counsel for Petitioner, as follows:
`
`Darren M. Jiron (darren.jiron@finnegan.com);
`J.P. Long (jp.long@finnegan.com);
`E. Robert Yoches (bob.yoches@finnegan.com);
`Joshua L. Goldberg (joshua.goldberg@finnegan.com);
`TSMC-IPB-PTAB@finnegan.com;
`Kent J. Cooper (kent.cooper@kjcooperlaw.com); and
`Adam Floyd (floyd.adam@dorsey.com)
`
`/Neil F. Greenblum /
`Neil F. Greenblum
`Registration No. 28,394
`Greenblum & Bernstein, P.L.C.
`1950 Roland Clarke Place
`Reston, Virginia 20191
`Tel: 703-716-1191
`Fax: 703-716-1180
` Email: ngreenblum@gbpatent.com
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`