UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`Taiwan Semiconductor Manufacturing Company, Ltd.
`
`Petitioner
`
`v.
`
`Godo Kaisha IP Bridge 1
`
`Patent Owner
`
`
`
`
`
`Patent No. 7,126,174
`Filing Date: November 24, 2004
`Issue Date: October 24, 2006
`
`Title: SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING
`THE SAME
`
`
`
`Inter Partes Review No. IPR2016-01247
`
`
`
`CORRECTED DECLARATION OF DR. SANJAY KUMAR BANERJEE,
`PH.D. IN SUPPORT OF PETITION FOR INTER PARTES REVIEW OF
`UNITED STATES PATENT NO. 7,126,174
`
`
`
`
`Page 1 of 191
`
`
`
`TSMC Exhibit 1024
`TSMC v. IP Bridge
`IPR2016-01246
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`Taiwan Semiconductor Manufacturing Company, Ltd.
`
`Petitioner
`
`v.
`
`Godo Kaisha IP Bridge 1
`
`Patent Owner
`
`
`
`
`
`Patent No. 7,126,174
`Filing Date: November 24, 2004
`Issue Date: October 24, 2006
`
`Title: SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING
`THE SAME
`
`
`
`Inter Partes Review No. IPR2016-01247
`
`
`
`CORRECTED DECLARATION OF DR. SANJAY KUMAR BANERJEE,
`PH.D. IN SUPPORT OF PETITION FOR INTER PARTES REVIEW OF
`UNITED STATES PATENT NO. 7,126,174
`
`
`
`
`Page 1 of 191
`
`
`
`TSMC Exhibit 1024
`TSMC v. IP Bridge
`IPR2016-01246
`
`
`
`TABLE OF CONTENTS
`
`I.
`
`INTRODUCTION ..................................................................................... 1
`
`II.
`
`SUMMARY OF OPINIONS ..................................................................... 2
`
`III. BACKGROUND AND QUALIFICATIONS ........................................... 2
`
`A.
`
`Background........................................................................................ 2
`
`B.
`
`C.
`
`Previous Expert Witness Experience .................................................. 6
`
`Compensation .................................................................................... 6
`
`IV. MATERIALS REVIEWED ...................................................................... 7
`
`V.
`
`LEGAL STANDARDS .............................................................................. 9
`
`A. Anticipation ......................................................................................10
`
`B.
`
`Obviousness ......................................................................................11
`
`VI. TECHNOLOGICAL BACKGROUND ...................................................15
`
`A.
`
`B.
`
`Integrated Circuits ............................................................................15
`
`Isolation Structures ...........................................................................18
`
`1. LOCOS ......................................................................................19
`
`2. Shallow Trench Isolation ...........................................................20
`
`C.
`
`Insulating Sidewalls ..........................................................................22
`
`VII. THE ’174 PATENT ...................................................................................25
`
`A. Disclosed “Conventional” Devices ...................................................25
`
`B.
`
`Representative Embodiment .............................................................27
`
`
`
`i
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`Page 2 of 191
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`Japanese Application No. 7-192181 Does not Disclose All the
`C.
`Features of the Challenged Claims ..............................................................27
`
`VIII.
`
`LEVEL OF ORDINARY SKILL ...................................................30
`
`IX. ANALYSIS ................................................................................................31
`
`A.
`
`B.
`
`C.
`
`D.
`
`Lowrey (U.S. Patent No. 5,021,353) .................................................31
`
`Noble (U.S. Patent No. 5,539,229) ....................................................32
`
`Ogawa (U.S. Patent No. 4,506,434) ..................................................33
`
`The combined teachings of Lowrey and Noble ..................................35
`
`1. Claim 1 is obvious over Lowrey and Noble ................................43
`
`2. Claim 4 is obvious over Lowrey and Noble ................................57
`
`3. Claim 5 is obvious over Lowrey and Noble ................................59
`
`4. Claim 8 is obvious over Lowrey and Noble ................................61
`
`5. Claim 9 is obvious over Lowrey and Noble ................................63
`
`6. Claim 10 is obvious over Lowrey and Noble ..............................66
`
`7. Claim 11 is obvious over Lowrey and Noble ..............................69
`
`8. Claim 12 is obvious over Lowrey and Noble ..............................70
`
`9. Claim 14 is obvious over Lowrey and Noble ..............................72
`
`10. Claim 16 is obvious over Lowrey and Noble .............................73
`
`E.
`
`The combined teachings of Lowrey and Ogawa ................................76
`
`1. Claim 1 is obvious over Lowrey and Ogawa ..............................82
`
`2. Claim 4 is obvious over Lowrey and Ogawa ..............................85
`
`3. Claim 5 is obvious over Lowrey and Ogawa ..............................86
`
`4. Claim 8 is obvious over Lowrey and Ogawa ..............................87
`
`
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`ii
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`5. Claim 9 is obvious over Lowrey and Ogawa ..............................87
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`6. Claim 10 is obvious over Lowrey and Ogawa ............................88
`
`7. Claim 11 is obvious over Lowrey and Ogawa ............................89
`
`8. Claim 12 is obvious over Lowrey and Ogawa ............................90
`
`9. Claim 14 is obvious over Lowrey and Ogawa ............................91
`
`10. Claim 16 is obvious over Lowrey and Ogawa ...........................91
`
`X. CONCLUSION .........................................................................................92
`
`
`
`
`
`iii
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`I, Dr. Sanjay Kumar Banerjee, Ph.D., declare as follows:
`
`I.
`
`Introduction
`
`1. My name is Dr. Sanjay Kumar Banerjee. I have been asked to submit
`
`this declaration on behalf of Taiwan Semiconductor Manufacturing Company, Ltd.
`
`(“TSMC” or “Petitioner”) in connection with a petition for inter partes review of
`
`U.S. Patent No. 7,126,174 (“the ’174 patent”), which I have been told is being
`
`submitted to the Patent Trial and Appeal Board of the United States Patent and
`
`Trademark Office by TSMC.
`
`2.
`
`I have been retained as a technical expert by TSMC to study and
`
`provide my opinions on the technology claimed in, and the patentability or non-
`
`patentability of, claims 1, 4, 5, 8–12, 14, and 16 in the ’174 patent (“the
`
`Challenged Claims”).
`
`3.
`
`I understand the ’174 patent is related to U.S. Patent Nos. 6,967,409
`
`(the ’409 patent), 6,709,950 (the ’950 patent), and 6,281,562 (the ’562 patent) and
`
`also claims the benefit of priority to two Japanese applications, JP 7-192181,
`
`which was filed on July 27, 1995, and JP 7-330112, which was filed on December
`
`19, 1995.
`
`
`
`
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`II.
`
`Summary of Opinions
`
`4.
`
`This declaration is directed to the Challenged Claims of the ’174
`
`patent, and sets forth certain opinions I have formed, the conclusions I have
`
`reached, and the bases for each.
`
`5.
`
`Based on my experience, knowledge of the art at the relevant time,
`
`analysis of prior art references, and the understanding a person of ordinary skill in
`
`the art would have of the claim terms in light of the specification, it is my opinion
`
`that all of the Challenged Claims of the ’174 patent are unpatentable as being
`
`obvious over the prior art references discussed below.
`
`6.
`
`Based on my experience, knowledge of the art at the relevant time,
`
`and the plain and ordinary meaning of the claims as they would have been
`
`understood by a person of ordinary skill in the art, it is further my opinion that the
`
`Challenged Claim features that do not appear in Japanese Patent Application No.
`
`7-192181.
`
`III. Background and Qualifications
`
`A. Background
`
`7.
`
`I am currently the Cockrell Family Chair Professor of Electrical and
`
`Computer Engineering at the University of Texas at Austin. At UT Austin, I am
`
`also the director of the Microelectronics Research Center. I have been a faculty
`
`member at UT Austin since 1987.
`
`
`
`2
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`8.
`
`I have also been active in industries related to the relevant field of art.
`
`As a Member of the Technical Staff, Corporate Research, Development and
`
`Engineering of Texas Instruments Incorporated from 1983–1987, I worked on
`
`polysilicon transistors and dynamic random access trench memory cells used by
`
`Texas Instruments in the world’s first 4-Megabit DRAM, for which I was co-
`
`recipient of the Best Paper Award, IEEE International Solid State Circuits
`
`Conference, 1986.
`
`9.
`
`I received a B.Tech from the Indian Institute of Technology,
`
`Kharagpur, an M.S. and Ph.D. from the University of Illinois at Urbana-
`
`Champaign, all in Electrical Engineering.
`
`10.
`
`I am a leading researcher and educator in various areas of transistor
`
`device fabrication technology, including the fabrication, characterization and
`
`applications of memory devices, transistors, and nanotechnology. My research has
`
`been funded by the Texas Advanced Technology Program (ATP), the Texas
`
`Higher Education Coordinating Board, the National Science Foundation, the
`
`SEMATECH (Semiconductor Manufacturing Technology) consortium, the SRC
`
`(Semiconductor Research Corporation) consortium, DARPA, and the Department
`
`of Energy, among others.
`
`11. At the University of Texas, I am the director of the Microelectronics
`
`Research Center, comprised of faculty colleagues, graduate, and undergraduate
`
`
`
`3
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`students. I also serve as the director of the South West Academy of
`
`Nanoelectronics, one of three centers in the United States to develop a replacement
`
`for MOSFETs.
`
`12.
`
`I have published over 1,000 technical articles, many related to
`
`semiconductor fabrication technology, most at highly competitive refereed
`
`conferences and rigorously reviewed journals. I have also published 8 books or
`
`chapters on transistor device physics and fabrication, and have supervised over 50
`
`Ph.D. and 60 MS students.
`
`13.
`
`I have been a member of scientific organizations and committees,
`
`including the IEEE Dan Noble Award Committee from 2010–2013, serving as
`
`Chair from 2012–2013, the International Technology Roadmap for
`
`Semiconductors, the International Conference on MEMS (Microelectromechanical
`
`Systems) and Nanotechnology, the IEEE International Conference on
`
`Communications, Computers, Devices, the International Electron Devices
`
`Meeting, the International Conference on Simulation of Semiconductor Processes
`
`and Devices, and the IEEE Symposium on VLSI (Very-Large-Scale Integration)
`
`Technology.
`
`14.
`
`I have served as the Session Chair for the “Device Technology”
`
`Session conducted at the IEEE International Electron Devices Meeting in 1989–
`
`1990. I have also served as the General Chairman for the IEEE University
`
`
`
`4
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`
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`Government Industry Microelectronics Symposium in 1994–1995, and Chair of the
`
`IEEE Device Research Conference.
`
`15.
`
`I have served on the Technical Advisory Boards of AstroWatt, DSM
`
`Semiconductors, Cambrios, Nanocoolers Inc., BeSang Memories, Organic ID and
`
`ITU Ventures; Gerson Lehmann Group, NY; Austin Community College; Asia
`
`Pacific IIT; Rochester Institute of Technology, and HSMC Foundry.
`
`16.
`
`I received the Engineering Foundation Advisory Council Halliburton
`
`Award (1991), the Texas Atomic Energy Fellowship (1990–1997), Cullen
`
`Professorship (1997–2001) and the Hocott Research Award from UT Austin
`
`(2007). I also received the IEEE Grove Award (2014), Distinguished Alumnus
`
`Award, IIT (2005), Industrial R&D 100 Award (2004), ECS Callinan Award,
`
`2003, IEEE Millennium Medal, 2000, NSF Presidential Young Investigator Award
`
`in 1988, and several SRC Inventor Recognition and Best Paper Awards.
`
`17.
`
`I was a Distinguished Lecturer for IEEE Electron Devices Society,
`
`and am a Fellow of the Institute of the Electrical and Electronics Engineers (IEEE),
`
`the American Physical Society (APS) and the American Association for the
`
`Advancement of Science (AAAS).
`
`18.
`
`I am the inventor or co-inventor of over 30 United States patents in
`
`various areas of transistor device fabrication technology.
`
`
`
`5
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`19. Additional details about my employment history, fields of expertise,
`
`and publications are further included in my curriculum vitae (attached as Appendix
`
`A).
`
`B.
`
`20.
`
`Previous Expert Witness Experience
`
`I have served as an expert witness since the mid 1990’s. In the last ten
`
`years or so, I have testified at the International Trade Commission three times, and
`
`the Northern District of California once. In addition, I have been deposed six
`
`times on patents related to CMOS and semiconductor memories such as flash and
`
`DRAMs. Several of these have been IPR cases.
`
`C. Compensation
`
`21.
`
`I am being compensated for services provided in this matter at my
`
`usual and customary rate of $500 per hour plus travel expenses. My compensation
`
`is not conditioned on the conclusions I reach as a result of my analysis or on the
`
`outcome of this matter. Similarly, my compensation is not dependent upon and in
`
`no way affects the substance of my statements in this declaration.
`
`22.
`
`I have no financial interest in Petitioner or any of its subsidiaries. I
`
`also do not have any financial interest in Patent Owner Godo Kaisha IP Bridge 1. I
`
`do not have any financial interest in the ’174 patent and have not had any contact
`
`with any of the named inventors of the ’174 patent (Mizuki Segawa, Isao
`
`
`
`6
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`Page 10 of 191
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`
`
`Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita,
`
`Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, and Michikazu Matsumoto).
`
`IV. Materials Reviewed
`
`23.
`
`In forming my opinions, I have reviewed the following references:
`
`• The ’174 patent (which I have been told is Exhibit 1001 to TSMC’s
`
`petition);
`
`• U.S. Patent No. 5,153,145 to Lee et al. (“Lee,” which I have been told
`
`is Exhibit 1002 to TSMC’s petition);
`
`• U.S. Patent No. 3,617,824 to Shinoda et al. (“Shinoda,” which I have
`
`been told is Exhibit 1003 to TSMC’s petition);
`
`• J.A. Appels et al., Some Problems of MOS Technology, Philips Tech.
`
`Rev. vol. 31 nos. 7–9, pp. 225–36 (1970) (“Appels,” which I have been
`
`told is Exhibit 1005 to TSMC’s petition);
`
`• U.S. Patent No. 4,110,899 to Nagasawa et al. (“Nagasawa,” which I
`
`have been told is Exhibit 1006 to TSMC’s petition);
`
`• U.S. Patent No. 3,787,251 to Brand et al. (“Brand,” which I have been
`
`told is Exhibit 1007 to TSMC’s petition);
`
`• B.B.M. Brandt et al., “LOCMOS, a New Technology for
`
`Complementary MOS Circuits,” Philips Tech. Rev. vol. 34 no. 1, pp.
`
`
`
`7
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`19–23 (1974) (“Brandt,” which I have been told is Exhibit 1008 to
`
`TSMC’s petition);
`
`• U.S. Patent No. 5,702,976 to Schuegraf et al. (“Schuegraf,” which I
`
`have been told is Exhibit 1009 to TSMC’s petition);
`
`• U.S. Patent No. 4,506,434 to Ogawa et al. (“Ogawa,” which I have
`
`been told is Exhibit 1010 to TSMC’s petition);
`
`• U.S. Patent No. 4,957,590 to Douglas (“Douglas,” which I have been
`
`told is Exhibit 1011 to TSMC’s petition);
`
`• U.S. Patent No. 5,976,939 to Thompson et al. (“Thompson,” which I
`
`have been told is Exhibit 1012 to TSMC’s petition);
`
`• U.S. Patent No. 6,165,826 to Chau et al. (“Chau,” which I have been
`
`told is Exhibit 1013 to TSMC’s petition);
`
`• U.S. Patent No. 5,733,812 to Ueda et al. (“Ueda,” which I have been
`
`told is Exhibit 1014 to TSMC’s petition);
`
`• U.S. Patent No. 5,539,229 to Noble, Jr. et al. (“Noble,” which I have
`
`been told is Exhibit 1015 to TSMC’s petition);
`
`• U.S. Patent No. 5,521,422 to Mandelman et al. (“Mandelman” which I
`
`have been told is Exhibit 1016 to TSMC’s petition);
`
`• U.S. Patent No. 5,021,353 to Lowrey et al. (“Lowrey,” which I have
`
`been told is Exhibit 1017 to TSMC’s petition);
`
`
`
`8
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`• U.S. Patent No. 4,638,347 to Iyer (“Iyer,” which I have been told is
`
`Exhibit 1018 to TSMC’s petition);
`
`• Japanese Patent Application No. 7-192181 to Segawa et al. (which I
`
`have been told is Exhibit 1019 to TSMC’s petition);
`
`• Certified Translation of Japanese Patent Application No. 7-192181 to
`
`Segawa et al. (which I have been told is Exhibit 1020 to TSMC’s
`
`petition);
`
`• File History of U.S. Patent No. 7,126,174 to Segawa et al. (which I
`
`have been told is Exhibit 1021 to TSMC’s petition); and
`
`• File History of Japanese Patent Application No. 7-330112 to Segawa et
`
`al. (which I have been told is Exhibit 1022 to TSMC’s petition).
`
`• Certified Translation of the File History of Japanese Patent Application
`
`No. 7-330112 to Segawa et al. (which I have been told is Exhibit 1023
`
`to TSMC’s petition).
`
`V. Legal Standards
`
`24.
`
`I am not an attorney and have not been asked to offer my opinion on
`
`the law. However, as an expert offering an opinion on whether the claims in the
`
`’174 patent are patentable, I have been told that I am obliged to follow existing
`
`law. I have been told the following legal principles apply to analysis of
`
`patentability pursuant to 35 U.S.C. §§ 102 and 103.
`
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`25.
`
`I also understand that, in an inter partes review proceeding, patent
`
`claims may be deemed unpatentable if it is shown by preponderance of the
`
`evidence that they were anticipated and/or rendered obvious by one or more prior
`
`art patents or publications.
`
`26. Further, I have been told that, in an inter partes review proceeding,
`
`patent claims cannot claim the benefit of priority to a domestic or a foreign
`
`application, if the domestic or the foreign application does not adequately describe
`
`or enable those claims.
`
`A. Anticipation
`
`27.
`
`I have been told that for a claim to be anticipated under § 102, every
`
`limitation of the claimed invention must be found in a single prior art reference.
`
`28.
`
`I have been told that a claim is unpatentable as anticipated under
`
`§ 102(a) if the claimed invention was “known or used by others in this country, or
`
`patented or described in a printed publication in this or another country, before the
`
`invention thereof by the applicant for patent.”
`
`29.
`
`I have been told that a claim is unpatentable as anticipated under
`
`§ 102(b) if the claimed invention was “patented or described in a printed
`
`publication in this or a foreign country or in public use or on sale in this country,
`
`more than one year prior to the date of the application for patent in the United
`
`States.”
`
`
`
`10
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`30.
`
`I have been told that a claim is unpatentable as anticipated under
`
`§ 102(e) if “the invention was described in (1) an application for patent, published
`
`under section 122(b), by another filed in the United States before the invention by
`
`the applicant for patent or (2) a patent granted on an application for patent by
`
`another filed in the United States before the invention by the applicant for patent,
`
`except that an international application filed under the treaty defined in section
`
`351(a) shall have the effects for the purposes of this subsection of an application
`
`filed in the United States only if the international application designated the United
`
`States and was published under Article 21(2) of such treaty in the English
`
`language.”
`
`B. Obviousness
`
`31.
`
`I have been told that under 35 U.S.C. § 103(a), “[a] patent may not be
`
`obtained although the invention is not identically disclosed or described as set forth
`
`in section 102, if the differences between the subject matter sought to be patented
`
`and the prior art are such that the subject matter would have been obvious at the
`
`time the invention was made to a person having ordinary skill in the art to which
`
`said subject matter pertains.”
`
`32. When considering the issues of obviousness, I have been told that I
`
`am to do the following:
`
`a.
`
`Determine the scope and content of the prior art;
`
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`b.
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`Ascertain the differences between the prior art and the claims at
`
`issue;
`
`c.
`
`d.
`
`Resolve the level of ordinary skill in the pertinent art; and
`
`Consider evidence of secondary indicia of non-obviousness (if
`
`available).
`
`33.
`
`I have been told that the relevant time for considering whether a claim
`
`would have been obvious to a person of ordinary skill in the art is the time of
`
`alleged invention, which I have assumed is shortly before the ’174 patent was filed.
`
`34.
`
`I have been told that obviousness is a determination of law based on
`
`underlying determinations of fact. I have been told that these factual
`
`determinations include the scope and content of the prior art, the level of ordinary
`
`skill in the art, the differences between the claimed invention and the prior art, and
`
`secondary considerations of non-obviousness.
`
`35.
`
`I have been told that any assertion of secondary indicia must be
`
`accompanied by a nexus between the merits of the invention and the evidence
`
`offered.
`
`36.
`
`I have been told that a reference may be combined with other
`
`references to disclose each element of the invention under § 103. I have been told
`
`that a reference may also be combined with the knowledge of a person of ordinary
`
`skill in the art and that this knowledge may be used to combine multiple
`
`
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`references. I have also been told that a person of ordinary skill in the art is
`
`presumed to know the relevant prior art. I have been told that the obviousness
`
`analysis may take into account the inferences and creative steps that a person of
`
`ordinary skill in the art would employ.
`
`37.
`
`In determining whether a prior art reference could have been
`
`combined with another prior art reference or other information known to a person
`
`having ordinary skill in the art, I have been told that the following principles may
`
`be considered:
`
`a. A combination of familiar elements according to known methods is
`
`likely to be obvious if it yields predictable results;
`
`b. The substitution of one known element for another is likely to be
`
`obvious if it yields predictable results;
`
`c. The use of a known technique to improve similar items or methods in
`
`the same way is likely to be obvious if it yields predictable results;
`
`d. The application of a known technique to a prior art reference that is
`
`ready for improvement, to yield predictable results;
`
`e. Any need or problem known in the field and addressed by the
`
`reference can provide a reason for combining the elements in the
`
`manner claimed;
`
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`f. A person of ordinary skill often will be able to fit the teachings of
`
`multiple references together like a puzzle; and
`
`g. The proper analysis of obviousness requires a determination of
`
`whether a person of ordinary skill in the art would have a “reasonable
`
`expectation of success”—not “absolute predictability” of success—in
`
`achieving the claimed invention by combining prior art references.
`
`38.
`
`I have been told that whether a prior art reference renders a patent
`
`claim unpatentable as obvious is determined from the perspective of a person of
`
`ordinary skill in the art. I have been told that there is no requirement that the prior
`
`art contain an express suggestion to combine known elements to achieve the
`
`claimed invention, but a suggestion to combine known elements to achieve the
`
`claimed invention may come from the prior art, as filtered through the knowledge
`
`of one skilled in the art. In addition, I have been told that the inferences and
`
`creative steps a person of ordinary skill in the art would employ are also relevant to
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`the determination of obviousness.
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`39.
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`I have been told that, when a work is available in one field, design
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`alternatives and other market forces can prompt variations of it, either in the same
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`field or in another. I have been told that if a person of ordinary skill in the art can
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`implement a predictable variation and would see the benefit of doing so, that
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`variation is likely to be obvious. I have been told that, in many fields, there may
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`14
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`Page 18 of 191
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`be little discussion of obvious combinations, and in these fields market demand—
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`not scientific literature—may drive design trends. I have been told that, when
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`there is a design need or market pressure and there are a finite number of
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`predictable solutions, a person of ordinary skill in the art has good reason to pursue
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`those known options.
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`40.
`
`I have been told that there is no rigid rule that a reference or
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`combination of references must contain a “teaching, suggestion, or motivation” to
`
`combine references. But I also understand that the “teaching, suggestion, or
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`motivation” test can be a useful guide in establishing a rationale for combining
`
`elements of the prior art. I have been told that this test poses the question as to
`
`whether there is an express or implied teaching, suggestion, or motivation to
`
`combine prior art elements in a way that realizes the claimed invention, and that it
`
`seeks to counter impermissible hindsight analysis.
`
`VI. Technological Background
`
`A.
`
`Integrated Circuits
`
`41. A transistor functions like a valve for controlling electric current
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`through it according to a control signal. In a digital circuit, the valve is either open
`
`or closed, so the transistor acts more like a switch. One type of transistor is a
`
`MOSFET, which stands for metal-oxide-semiconductor (MOS) field-effect
`
`transistor (FET).
`
`
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`15
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`Page 19 of 191
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`42. As the name suggests, the MOS structure is a layered stack, the
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`bottom of which is a semiconductor, the middle of which is a gate oxide, and the
`
`top of which is a conductive gate. Often, when the gate insulator is not an oxide,
`
`this will be abbreviated MIS, rather than MOS, but they are effectively the same
`
`structures. In addition, the “metal” may be polysilicon or a metal silicide, rather
`
`than a true metal.
`
`43. A field-effect transistor (FET) is named after its principle of
`
`operation. In particular, the MOS gate structure modulates an electric field near
`
`the semiconductor-gate insulator interface. This electric field adjusts a “channel”
`
`through which the current can traverse the transistor.
`
`44. A MOSFET includes several basic elements: a source (an inlet for
`
`current), a drain (an outlet for current), and a gate (for controlling current flow
`
`through the channel beneath the gate from the source to the drain). Electrodes on
`
`top of the source and drain allow current to flow into and out of the transistor.
`
`45. The gate of a MOSFET comprises two basic parts: a gate insulator
`
`(“gate oxide” or “gate dielectric”) and a gate electrode (“gate electrode” or “gate”).
`
`The gate electrode allows the MOSFET to switch on and off. The gate electrode
`
`receives a control voltage to switch the MOSFET on and off, and the gate insulator
`
`generates an associated electric field that controls the channel. The “ON” and
`
`
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`16
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`“OFF” states of a MOSFET are depicted below with annotations. (Shinoda at Fig.
`
`5.)
`
`
`
`
`
` ON
`
`
`
`
`
`
`
`
`
`
`
` OFF
`
`46. MOSFETs are connected together by interconnections to form
`
`circuits. The interconnections are typically electrical conductors that provide
`
`pathways for electrical signals. Interconnections can be made from a variety of
`
`conducting materials, including metals, metal alloys, metal compounds,
`
`polycrystalline silicon (polysilicon), and combinations of the above (e.g., metal-
`
`silicon compounds, generally called “silicides”).
`
`47.
`
`Integrated circuits comprising multiple MOSFETs and
`
`interconnections have existed for more than 50 years. For example, the
`
`specification of Shinoda, filed in 1965, discloses multilevel interconnections
`
`formed between MOSFETS in an integrated circuit. (Shinoda at 4:30–73). Figures
`
`6–7 of Shinoda are reproduced below with annotations.
`
`
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`17
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`Page 21 of 191
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`Page 21 of 191
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`
`
`B.
`
`Isolation Structures
`
`48. The semiconductor industry has always moved towards packing more
`
`MOSFETS onto each chip—a trend called “scaling.” Scaling has been so
`
`predictable that it has been quantified. Moore’s Law predicts that the transistor
`
`density will double about every two years.
`
`49. As device densities increase, the distance between devices shrinks.
`
`By the early 1970s, scaling had caused undesirable interactions between circuit
`
`
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`18
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`Page 22 of 191
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`Page 22 of 191
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`
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`elements. (Appels at 234–36; Nagasawa at 1:40–2:26; Brand at 1:6–2:32.) The
`
`industry’s solution to this problem was to include “isolation” regions between the
`
`devices. (Appels at 234–36; Nagasawa at 1:7–2:66; Brand at 1:6–2:32; Brandt at
`
`20–23.) Isolation has been a fundamental aspect of semiconductor technology ever
`
`since.
`
`1.
`
`LOCOS
`
`50. LOCOS (LOCal Oxidation of Silicon) was one of the first isolation
`
`techniques. It was reported in 1970 by a research group at Philips. (Appels, 226,
`
`276; Brandt at 20 & n.4; Nagasawa at 1:8–14, 1:63–68.) In LOCOS, selected
`
`areas of a Si substrate are exposed to O2 at a high temperature to form SiO2
`
`insulating regions. (Appels, 228, 230, 234; Nagasawa at 3:18–20, 4:18–34; Brandt
`
`at 20–21.) During this process, the SiO2 consumes (i.e., “sinks into”) the substrate
`
`as the Si is converted to SiO2. (Brandt at 20.)
`
`51. LOCOS, although simple, has drawbacks. SiO2 grows laterally as the
`
`substrate is oxidized, resulting in unintentional SiO2 projections into MOSFET
`
`regions. These projections are commonly called “overhang” or “bird’s beaks” (due
`
`to their shape). (Nagasawa at 6:1:10; Schuegraf at 1:47–59; Brandt at Fig. 2a;
`
`Ogawa at 1:33–42, Fig. 1(shown below with annotation).) By the 1990s, the bird’s
`
`beak “pose[d] a limitation to device density” that was addressed by other isolation
`
`
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`19
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`Page 23 of 191
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`
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`techniques. (Schuegraf at 1:47–59; ’174 patent at 1:29–43 (which I have been told
`
`is admitted prior art).)
`
`2.
`
`Shallow Trench Isolation
`
`
`
`52. Trench isolation techniques, such as shallow trench isolation (STI),
`
`replaced LOCOS to avoid the scaling problem of the latter. (’174 patent at 1:29–
`
`34; Schuegraf at 2:20–24.) In STI, selected areas of a substrate are etched to form
`
`trenches, which are filled with insulating material. Although marginally more
`
`expensive and complex than LOCOS, STI does not encroach laterally into
`
`neighboring regions, thus resolving the problems of LOCOS. (Schuegraf at 2:20–
`
`24; Ogawa at 1:60–68.)
`
`53. Because the two processes are so similar otherwise, STI and LOCOS
`
`are interchangeable and functionally equivalent. (Schuegraf at 1:31–2:24;
`
`Thompson at 4:8–16; Chau at 3:1–10; Ueda at 5:56–67; Noble at 22:49–52.) In the
`
`1990s, when transitioning from the 0.5 µm to 0.25 µm process node, the industry
`
`faced a design choice: increase device density and add expense (trench isolation),
`
`
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`20
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`Page 24 of 191
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`
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`or maintain device density and costs (LOCOS). The industry has always decided
`
`in favor of scaling, and the choice was no different then. (Lee at 1:10–14.)
`
`54.
`
`In some STI processes, the top of the isolation structure is level with
`
`the substrate surface. The industry recognized that this can interfere with the
`
`operation of adjacent MOSFETs if packed too closely. For example, sharp corners
`
`of the STI structure enhance the electric field and create parasitic effects if the
`
`MOSFETs are too close. (Mandelman at 1:16–37, Abstract, 1:6–35, Figs. 6a, 6b.)
`
`Problems are exacerbated if the isolation trench is recessed below the substrate
`
`surface during subsequent etches, often allowing the gate to “wrap around” the
`
`trench corner. (Mandelman at 1:30–37, 3:27–48, 4:58–62, Fig. 2.)
`
`55. Raised STI structures wherein the STI region extends above the
`
`surface of a substrate help to avoid these problems. (Noble at 5:49–55, 6:32–50,
`
`Fig. 12; Mandelman at Abstract, 3:33–34, Fig. 5.) Raised STI also localizes
`
`source/drain regions by providing a barrier during their ion implantation or
`
`diffusion processes. (Noble at Abstract, 4:62–65, 5:5–8.) Raised STI structures
`
`from the prior art are shown below as examples. (Ogawa at Fig. 5(b); Noble at
`
`Fig. 11; Mandelman at Fig. 5.)
`
`
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`21
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`Page 25 of 191
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`
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`C.
`
`Insulating Sidewalls
`
`56. MOSFETs, interconnections, and STI regions with sidewalls
`
`
`
`(including L-shaped sidewalls) were all known in the art well before the
`
`application for the ’174 patent was filed. In my opinion, the ’174 patent discloses
`
`that a “conventional semiconductor device” included MOSFETs, interconnections,
`
`and STI regions with sidewalls. (’174 patent at 1:52–2:21, Figs. 17, 20(e).)
`
`57. Sidewalls provide several benefits in this context. For example, they
`
`prevent damage during etching to the structure o
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