throbber
Trials@uspto.gov
`571-272-7822
`
`
`Paper 11
`Entered: December 15, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`CANON INC., CANON U.S.A., INC.,
`CANON FINANCIAL SERVICES, INC., FUJIFILM CORPORATION,
`FUJIFILM HOLDINGS AMERICA CORPORATION,
`FUJIFILM NORTH AMERICA CORPORATION, JVC KENWOOD
`CORPORATION, JVCKENWOOD USA CORPORATION,
`NIKON CORPORATION, NIKON INC., OLYMPUS CORPORATION,
`OLYMPUS AMERICA INC., PANASONIC CORPORATION,
`PANASONIC CORPORATION OF NORTH AMERICA,
`SAMSUNG ELECTRONICS CO., LTD., and
`SAMSUNG ELECTRONICS AMERICA, INC.,
`Petitioner,
`
`v.
`
`PAPST LICENSING GMBH & CO., KG,
`Patent Owner.
`____________
`
`Case IPR2016-01211
`Patent 8,504,746 B2
`
`____________
`
`Before JONI Y. CHANG, JENNIFER S. BISK, and MIRIAM L. QUINN,
`Administrative Patent Judges.
`
`QUINN, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`

`
`IPR2016-01211
`Patent 8,504,746 B2
`
`
`
`Petitioner, as listed in the caption above, filed a Petition to institute
`
`inter partes review of claims 112, 14, 15, 1721, 2331, 34, and 35 of U.S.
`
`Patent No. 8,504,746 B2 (“the ’746 patent”) pursuant to 35 U.S.C.
`
`§ 311319. Paper 1 (“Pet.”). Papst Licensing GMBH & Co. KG (“Patent
`
`Owner”) timely filed a Preliminary Response. Paper 10 (“Prelim. Resp.”).
`
`We have jurisdiction under 35 U.S.C. § 314.
`
`For the reasons that follow, we grant the Petition as to claims 112,
`
`15, 1721, 2331, 34, and 35 (“the challenged claims”) of the ’746 patent.
`
`We deny the Petition as to claim 14.
`
`I.
`
`BACKGROUND
`
`A. RELATED MATTERS
`
`Petitioner identifies the patent-at-issue as the subject matter of many
`
`district court cases filed in the Northern District of California, Eastern
`
`District of Texas, District of D.C. and District of Delaware. Pet 6466; PO
`
`Notice Paper 5 at 14.
`
`The ’746 patent also has been the subject of multiple petitions for
`
`inter partes review filed by various Petitioners. Paper 5 at 4. The following
`
`proceedings have been identified: IPR2016-01200, -01206, -01211, -01213,
`
`-01223, and -01224. Paper 5, 1.
`
`B. REAL PARTIES-IN-INTEREST
`
`
`
`Petitioner asserts that the following parties are real parties-in-interest:
`
`Canon Inc.; Canon U.S.A., Inc.; Canon Financial Services, Inc.; Fujifilm
`
`Corporation; Fujifilm Holdings America Corporation; Fujifilm North
`
`America Corporation; JVC Kenwood Corporation; JVC Kenwood USA
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`Patent 8,504,746 B2
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`Corporation; Nikon Corporation, Nikon Inc.; Olympus Corporation;
`
`Olympus America Inc.; Panasonic Corporation; Panasonic Corporation of
`
`North America; Samsung Electronics Co., Ltd; and Samsung Electronics
`
`America, Inc. Pet. 63.
`
`C. THE ’746 PATENT (EX. 1201)
`
`
`
`The ’746 patent is titled, “Analog Data Generating and Processing
`
`Device for use With a Personal Computer.” It relates generally to the
`
`transfer of data, and, in particular, to interface devices for communication
`
`between a computer or host device and a data transmit/receive device from
`
`which data is to be acquired or with which two-way communications is to
`
`take place. Ex. 1201, 1:20–24. Figure 1, reproduced below, illustrates a
`
`general block diagram of an interface device 10. Id. at 4:5960.
`
`
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`IPR2016-01211
`Patent 8,504,746 B2
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`
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`According to Figure 1, first connecting device 12 is attached to a host
`
`device (not shown), to digital signal processor (DSP) 13 and memory means
`
`14. Id. at 4:6065. DSP 13 and memory means 14 are also connected to
`
`second connecting device 15. Id. at 4:6467. The interface device
`
`“simulates a hard disk with a root directory whose entries are ‘virtual’ files
`
`which can be created for the most varied functions.” Id. at 5:1114.
`
`“Regardless of which data transmit/receive device at the output line 16 is
`
`attached to the second connecting device, the digital signal processor 13
`
`informs the host device that it is communicating with a hard disk drive. Id.
`
`at 5:3134. In one embodiment, the interface device is automatically
`
`detected when the host system is “booted,” resulting in the user “no longer
`
`[being] responsible for installing the interface device 10 on the host device
`
`by means of specific drivers which must also be loaded.” Id. at 7:1320.
`
`D. REPRESENTATIVE CLAIM
`
`There are three independent claims in the set of challenged claims (1,
`
`31, 34). Claim 1 is reproduced below, and is illustrative of the subject
`
`matter claimed.
`
`1. An analog data acquisition device operatively connect
`able to a computer through a multipurpose interface of the
`computer, the computer having an operating system
`programmed so that, when the computer receives a signal
`from the device through said multipurpose interface of the
`computer indicative of a class of devices, the computer
`automatically activates a device driver corresponding to the
`class of devices for allowing the transfer of data between the
`device and the operating system of the computer, the analog
`data acquisition device comprising:
`
`a) a program memory;
`
`b) an analog signal acquisition channel for receiving a
`signal from an analog source;
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`Patent 8,504,746 B2
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`c) a processor operatively interfaced with the
`
`multipurpose interface of the computer, the program
`memory, and a data storage memory when the analog data
`acquisition device is operational;
`
`d) wherein the processor is configured and programmed
`to implement a data generation process by which analog data
`is acquired from the analog signal acquisition channel, the
`analog data is processed and digitized, and the processed
`and digitized analog data is stored in a file system of the
`data storage memory as at least one file of digitized analog
`data;
`
`e) wherein when the analog acquisition device is
`operatively interfaced with the multipurpose interface of the
`computer, the processor executes at least one instruction set
`stored in the program memory and thereby automatically
`causes at least one parameter indicative of the class of
`devices to be sent to the computer through the multipurpose
`interface of the computer, independent of the analog source,
`wherein the analog data acquisition device is not within the
`class of devices; and
`
`f) wherein the processor is further configured and
`programmed to execute at least one other instruction set
`stored in the program memory to thereby allow the at least
`one file of digitized analog data acquired from the analog
`signal acquisition channel to be transferred to the computer
`using the device driver corresponding to said class of
`devices so that the analog data acquisition device appears to
`the computer as if it were a device of the class of devices;
`
`whereby there is no requirement for any user-loaded
`file transfer enabling software to be loaded on or installed in
`the computer in addition to the operating system.
`
`E. ASSERTED GROUNDS OF UNPATENTABILITY
`
`Petitioner asserts unpatentability of claims 112, 14, 15, 1721,
`
`2331, 34, and 35 (Pet. 7):
`
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`IPR2016-01211
`Patent 8,504,746 B2
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`Reference(s)
`
`Kawaguchi1
`
`Basis
`
`§ 102
`
`Kawaguchi, and Matsumoto2
`
`§ 103
`
`Kawaguchi, Matsumoto, and
`Takahashi3
`Kawaguchi, Matsumoto, and
`DASM-AD144
`Kawaguchi, Matsumoto, and
`Saito5
`Kawaguchi, Matsumoto, Saito,
`and Muramatsu,6
`
`Claim(s)
`
`112, 14, 15, 1719, 26,
`2931, 34, and 35
`112, 14, 15, 1719, 26,
`2931, 34, and 35
`14
`
`§ 103
`
`§ 103
`
`21, 24, 25, 27, and 28
`
`§ 103
`
`§ 103
`
`20
`
`23
`
`In addition to the supporting argument for these grounds in the
`
`Petition, Petitioner also presents expert testimony. Ex. 1204, Declaration of
`
`Paul F. Reynolds, Ph.D. (“Reynolds Declaration”).
`
`II. ANALYSIS
`
`A. CLAIM INTERPRETATION
`
`
`
`In an inter partes review, claim terms in an unexpired patent are given
`
`their broadest reasonable construction in light of the specification of the
`
`
`1 JP H4-15853, Jan. 21, 1992 (Ex. 1206) (Ex. 1207, English translation,
`“Kawaguchi”). All further citations to Kawaguchi are to the English
`translation (Ex. 1207).
`2 US Patent No. 5,684,607, Nov. 4, 1997 (Ex. 1208) (“Matsumoto”).
`3 JP H05-344283, Dec. 24, 1993 (Ex. 1210) (Ex. 1211, English translation,
`“Takahashi”). All further citations to Takahashi are to the English
`translation (Ex. 1211).
`4 Analogic, DASM-AD14, 14-Bits, 2 MHz A-to-D SCSI Substation for the
`Most Demanding Data Acquisition Applications (1992) (Ex. 1209, “DASM-
`AD14”).
`5 US Patent No. 5,724,155, Mar. 3, 1998 (Ex. 1213, “Saito”).
`6 US Patent No. 5,592,256, Jan. 7, 1997 (Ex. 1212, “Muramatsu”).
`
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`patent in which they appear. 37 C.F.R. § 42.100(b). Under the broadest
`
`reasonable interpretation standard, claim terms generally are given their
`
`ordinary and customary meaning, as would be understood by one of ordinary
`
`skill in the art in the context of the entire disclosure. See In re Translogic
`
`Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`
`
`
`We note that only those claim terms which are in controversy need to
`
`be construed, and only to the extent necessary to resolve the controversy.
`
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir.
`
`1999). The parties propose constructions for several claim terms. Pet. 7–9;
`
`Prelim. Resp. 16, 17, 20–28. For purposes of this Decision, we find it
`
`necessary to address only the claim terms identified below.
`
`“analog signal acquisition channel”
`
`
`
`Independent claim 1 recites that the “analog data acquisition device”
`
`comprises “an analog signal 1acquisition channel for receiving a signal from
`
`an analog source.” Ex. 1201, 11:5960. Claim 1 further recites that the
`
`processor is configured and programmed to implement a data generation
`
`process by which analog data is acquired from the analog signal acquisition
`
`channel.” Id. at 11:6512:1 (emphasis added). In contrast, claims 31 and 34
`
`do not recite an “analog signal acquisition channel.” Instead, claims 31 and
`
`34 require acquiring analog data from an analog source. In claim 31, the
`
`analog source is operatively interfaced with the processor, whereas in claim
`
`34, there is no recited relationship between the processor and the analog
`
`source. Notably, although analog data is received from the analog source,
`
`none of the independent claims (1, 31 and 34), require that the claimed
`
`analog (data) acquisition device and interface comprise an analog source.
`
`Petitioner does not identify any meaningful difference between the claims
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`with regard to the acquisition of analog data. At this juncture, neither party
`
`proffers a construction for “analog signal acquisition channel.” We find,
`
`however, that the claim language differences between these independent
`
`claims warrant that we clarify the scope of the “analog signal acquisition
`
`channel” in claim 1.
`
`
`
`First, claim 1 expressly requires that the “analog signal acquisition
`
`channel” receive a signal from an analog source which, by the plain reading
`
`of the claim, must be an analog signal. Second, the Specification supports
`
`this interpretation. In particular, we note that Figure 2, which describes in
`
`more detail interface device 10 shown in Figure 1, depicts 8-channel
`
`multiplexer 1520, described as having multiple inputs, each connected to a
`
`sample/hold circuit. Id. at 8:6165. The 8-channel multiplexer (1520),
`
`feeds its output signal 1525 into an analog/digital converter 1530 and to the
`
`DSP 1300. Id. That is, the Specification describes that multiplexer 1520
`
`receives an analog signal, which is then sent to other parts of interface 10 for
`
`digitization. This understanding is enforced by further description of Figure
`
`2 in the Specification.
`
`
`
`For example, the Specification refers to interface device 10
`
`connecting (shown as line 16) to “any data transmit/receive device.” Id. at
`
`9:3437. Interface device 10 also implements an analog input, by “means
`
`of the blocks 15051535,” which include 8-channel multiplexer 1520. Id. at
`
`9:3437. The Specification goes on to describe the input having 8 channels,
`
`“independently programmable, and with a sampling rate of 1.25 MHz and
`
`quantization of 12 bits.” Id. at 9:3742. Taken together, this description of
`
`the 8 channels and the analog input to interface device 10 informs us that the
`
`recited “analog signal acquisition channel” of claim 1, which is claimed as
`
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`IPR2016-01211
`Patent 8,504,746 B2
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`part of the analog data acquisition device, receives an analog signal from an
`
`analog source. See Ex. 1201, 11:5660 (“analog data acquisition device
`
`comprising: . . . b) an analog signal acquisition channel”).
`
`
`
`The analog signal acquisition channel, however, is separate and
`
`distinct from the analog source. For instance, claim 1 requires that the
`
`analog signal acquisition channel receive the analog signal from the analog
`
`source. Furthermore, claim 1 requires that the processor “is configured and
`
`programmed to implement a data generation process by which analog data is
`
`acquired from the analog signal acquisition channel.” Id. at 11:65121.
`
`This claim language requires that the data generation process, which
`
`acquires data from the analog signal acquisition channel, must involve the
`
`claimed processor. This understanding is consistent with the Specification,
`
`which describes that the “programmable amplifier 1525 and the 8-channel
`
`multiplexer 1520 are controlled via an amplifier channel selection circuit
`
`1540 which is in turn controlled by the DSP 1300.” Id. at 8:679:3.
`
`
`
`Accordingly, we determine that, for purposes of this Decision, the
`
`“analog signal acquisition channel” is part of the analog acquisition device,
`
`and its processor implements the process by which analog data is received
`
`through the analog signal acquisition channel from the claimed analog
`
`source.
`
`B. OBVIOUSNESS GROUNDS BASED, AT LEAST IN PART, ON
`KAWAGUCHI
`
`
`
`Petitioner asserts that the challenged claims would have been obvious
`
`over the combination of Kawaguchi and Matsumoto. See supra, Section I.E.
`
`A patent claim is unpatentable as obvious under 35 U.S.C. § 103(a) if the
`
`differences between the claimed subject matter and the prior art are such that
`
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`the subject matter, as a whole, would have been obvious at the time the
`
`invention was made to a person having ordinary skill in the art to which said
`
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`
`(2007). The question of obviousness is resolved on the basis of underlying
`
`factual determinations including: (1) the scope and content of the prior art;
`
`(2) any differences between the claimed subject matter and the prior art;
`
`(3) the level of ordinary skill in the art; and (4) objective evidence of
`
`nonobviousness. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`
`
`
`First, we evaluate the level of ordinary skill in the art for purposes of
`
`this decision. Dr. Reynolds testifies that a person having ordinary skill in
`
`the art at the time of the invention “would have had at least a four-year
`
`degree in electrical engineering, computer science, or related field of study,
`
`or equivalent experience, and at least two [years of] experience in studying
`
`or developing computer interfaces or peripherals.” Ex. 1204 ¶ 39.
`
`Dr. Reynolds further testifies that such an artisan also would “be familiar
`
`with operating systems (e.g., MS-DOS, Windows, Unix) and their associated
`
`file systems (e.g., a FAT file system), device drivers for computer
`
`components and peripherals (e.g., mass storage device drivers), and
`
`communication interfaces (e.g., SCSI and PCMCIA interfaces).” Id. Patent
`
`Owner confirms that Petitioner’s statements regarding the level of ordinary
`
`skill in the art are mostly consistent with Patent Owner’s view, but
`
`nonetheless contends that an ordinarily skilled artisan would have one more
`
`year of experience, or, alternatively, five or more years of experience
`
`without a bachelor’s degree. Prelim. Resp. 2122. Notwithstanding the
`
`apparent differing opinions, at this juncture, the variance between the
`
`proffered levels of ordinary skill in the art does not have meaningful impact
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`in our determination of whether to institute inter partes review. Our analysis
`
`in this Decision is supported by either level of skill.
`
`
`
`We now turn to address the scope of the prior art. A short overview
`
`of Kawaguchi, and Matsumoto follow.
`
`1. Overview of Kawaguchi (Ex. 1207)
`
`Kawaguchi discloses a SCSI device converter for connecting a
`
`plurality of peripheral devices to an engineering workstation. Ex. 1207, 2.
`
`Figure 1 of Kawaguchi is reproduced below.
`
`As shown in Figure 1 of Kawaguchi, SCSI device converter 3
`
`includes: SCSI interface 7 for connecting to engineering workstation 1;
`
`personal computer input/output bus interfaces 8, 9 for connecting to output
`
`device (plotter) 4 and input device (CD-ROM) 5, respectively; bi-directional
`
`
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`parallel bus interface 10 for connecting to interrupt control device
`
`(sequencer) 6. SCSI device converter 3 can be adapted to accommodate any
`
`other type of device interface, including analog-to-digital converter 19 to
`
`receive analog data from an analog sensor 18. Id. at 5. SCSI device
`
`converter 3 also implements data writing unit 11, data reading unit 12,
`
`control data writing 13, interrupt data reading unit 14, code converting unit
`
`15, control unit 16, and interrupt control unit 17, by using a microcomputer,
`
`ROM, and RAM. Id.
`
`
`
`The engineering workstation has a SCSI interface “as standard
`
`equipment for connecting with the hard disk.” Id. at 5. According to
`
`Kawaguchi, “the SCSI device converter is able to input and output data to a
`
`SCSI interface of an [engineering workstation] using the same standards as
`
`SCSI interface for a hard disk.” Id. at 4. The SCSI driver of the engineering
`
`workstation is used as a driver for connecting a hard disk, performing
`
`operations in accordance with the SCSI standards. Id. at 7.
`
`Figure 2 of Kawaguchi is reproduced below.
`
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`
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`As shown in Figure 2 of Kawaguchi, the processing procedure
`
`includes an initialization process which includes: “Inquiry” that represents
`
`reporting of attribute information of a target and logical units (identification
`
`code of a device type); “Start/Stop Unit” that represents start/stop of the
`
`logical unit; “Test Unit Ready” that represents testing whether or not the
`
`logical unit is available; and “Mode Sense” that represents reporting of
`
`various parameter values (data format and storage medium configuration).
`
`Id. at 7. The initialization process allows the writing and reading units of the
`
`SCSI device converter to be activated for the host engineering workstation.
`
`After the initialization process, the host engineering workstation “performs
`
`writing to or reading from the writing units and reading units.” Id.
`
`Specifically, “Read Extended” represents “reading data from a designated
`
`block, i.e., the data reading unit (12) or the interrupt data reading unit (14).”
`
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`Id. And “Write Extended” presents “writing data to a designated block, i.e.,
`
`the data writing unit (11) or the control data writing unit (13).” Id.
`
`2. Overview of Matsumoto (Ex. 1208)
`
`
`
`Matsumoto discloses a “facsimile apparatus having a scanner for
`
`reading original images, a memory for storing images, a printer for recording
`
`images, and a communication control section for controlling the
`
`transmission/reception of data with a receiving communication apparatus.”
`
`Ex. 1208, Abstract. An object of Matsumoto’s invention is to increase the
`
`speed at which data is transferred between a host computer and a facsimile
`
`apparatus by using a SCSI interface. Id. at 1:37–45.
`
`
`
`Figure 1 of Matsumoto, reproduced below, illustrates a block diagram
`
`of a facsimile apparatus.
`
`
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`As shown in Figure 1 of Matsumoto, the facsimile apparatus includes
`
`CPU 1, ROM 2, RAM 3, image memory 4, image conversion section 5,
`
`scanner 6, printer 7, line control section 8, interface section 9, file
`
`management section 10, storage device 11, and operation section 12. Id. at
`
`3:1–34. CPU 1 controls the entire apparatus in accordance with control
`
`programs stored in ROM 2. Id. Communication protocols between the
`
`facsimile apparatus and host computer 15 are controlled by interface
`
`section 9, using a SCSI interface. Id.
`
`3. Obviousness Over Kawaguchi and Matsumoto
`
`
`
`After considering Petitioner’s contentions and Patent Owner’s
`
`arguments in opposition, we are persuaded that Petitioner has shown a
`
`reasonable likelihood of prevailing on showing the challenged claims would
`
`have been obvious over the combination of Kawaguchi and Matsumoto.
`
`
`
`
`
`Claim 1
`
`First, for purposes of this Decision, we are persuaded that Petitioner
`
`has shown that Kawaguchi allegedly discloses the “analog signal acquisition
`
`channel” recited by claim 1 at least by pointing to the analog-to-digital
`
`(A/D) converter 19. Pet. 1819; Ex. 1207, 5 (“an A/D converter (19) may
`
`be installed to receive analog data from an analog device (18) such as a
`
`sensor”). Applying our construction of “analog signal acquisition channel,”
`
`we agree that Petitioner has shown sufficiently that Kawaguchi’s A/D
`
`converter (19) receives an analog signal from an analog source (sensor 18).
`
`
`
`Second, for purposes of this Decision, we are persuaded that
`
`Petitioner has shown sufficiently that Kawaguchi, in view of Matsumoto,
`
`teaches or suggests the recited “data generation process” of claim 1. For this
`
`element, Petitioner asserts that the control unit retrieves data from sensor 18
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`via the A/D converter 19 and the data is digitized. Pet. 20 (citing Ex. 1204
`
`¶¶ 108112). Further, Petitioner asserts that “the processor-implemented
`
`code converting unit processes the data (e.g., converts the data format) and
`
`during the processing stores the data in data storage memory (e.g., RAM) as
`
`digitized analog data.” Id. (citing Ex. 1204 ¶ 108).
`
`
`
`Patent Owner argues that Kawaguchi is silent “as to what would
`
`happen to the data coming from the analog to digital converter 19, and
`
`whether the microcomputer would be involved in the process of acquiring
`
`and processing the incoming analog data.” Prelim. Resp. 28. Further, Patent
`
`Owner points out that Kawaguchi does not describe the control unit’s
`
`operation with regards to the A/D converter (19) and the acquisition of
`
`analog data from sensor (18). Id. at 2829. Ultimately, Patent Owner
`
`argues, Petitioner’s reliance on Dr. Reynolds testimony fails to establish the
`
`alleged missing limitation. In short, Patent Owner contends that Dr.
`
`Reynold’s testimony fails to link the A/D converter 19 and sensor 18
`
`embodiments to the opinions regarding the Kawaguchi and Matsumoto
`
`combination of “storing in a file system” limitation. Id.
`
`
`
`Although Petitioner’s arguments and evidence do not explain in detail
`
`the operation of “storing in a file system” particularly with regard to A/D
`
`converter 19, at this juncture in the proceeding, we recognize Petitioner’s
`
`argument that, generally, the code converting unit of Kawaguchi “during the
`
`processing[,] stores the data in data storage memory [] as digitized analog
`
`data.” See Pet. 20 (citing Ex. 1024 ¶ 108). Whether sufficient evidence
`
`ultimately supports Petitioner’s contentions is a determination we will make
`
`on the basis of a full record.
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`IPR2016-01211
`Patent 8,504,746 B2
`
`
`
`Therefore, for purposes of this Decision, we are not persuaded by
`
`Patent Owner’s assertions that the arguments in the Petition and the
`
`teachings of Kawaguchi, in combination with Matsumoto, are so limited as
`
`to preclude institution of trial. Instead, we conclude that Petitioner has
`
`shown sufficiently a reasonable likelihood of prevailing with respect to its
`
`challenges of unpatentability of claim 1.
`
`
`
`
`
`Claims 31 and 34
`
`Claims 31 and 34, as noted above in our claim construction of “analog
`
`signal acquisition device,” have different claim scope from claim 1
`
`concerning this term. Patent Owner’s arguments considered above, with
`
`respect to claim 1, were also considered for claims 31 and 34. We are
`
`persuaded, for purposes of this Decision, that Petitioner has sufficiently
`
`shown, that the “data generation process” as recited by claims 31 and 34
`
`would have been obvious over the combination of Kawaguchi and
`
`Matsumoto. See Pet. 5556; 5961. Petitioner proffers a reasonable
`
`rationale for the combination of Kawaguchi’s EWS and the teachings of
`
`Matsumoto. Id. at 2122.
`
`
`
`Dependent Claims
`
`Patent Owner does not provide separate arguments with respect to
`
`claims 2–12, 14, 15, 17–19, 26, 29, 30, and 35. We have reviewed
`
`Petitioner’s arguments and evidence regarding claims 212, 15, 1719, 26,
`
`29, 30, and 35, and we are persuaded, on this record, that Petitioner has
`
`shown a reasonable likelihood that the asserted prior art combination also
`
`renders these claims obvious. See Pet. 27–54, 61–62.
`
`With regard to claim 14, Petitioner asserts that Kawaguchi discloses
`
`input device 5 and interrupt control device 6 as analog sources each
`
`17
`
`

`
`IPR2016-01211
`Patent 8,504,746 B2
`
`including the “at least first and second transducers” recited by claim 14.
`
`Pet. 36. We are not persuaded that Petitioner has demonstrated sufficiently
`
`that either of Kawaguchi’s CD-ROM (input device 5) or sequencer (interrupt
`
`control device 6) are analog sources as required by claim 1. More
`
`particularly, Petitioner has failed to show that the “analog signal acquisition
`
`channel” in Kawaguchi (i.e., A/D converter 19), as we have construed the
`
`term, receives an analog signal from either the CD-ROM or the sequencer in
`
`Kawaguchi. Accordingly, we determine that Petitioner has not shown a
`
`reasonable likelihood of prevailing with respect to the challenge of
`
`unpatentability of claim 14.
`
`3. Obviousness Over Kawaguchi, Matsumoto, and Saito
`
`Petitioner asserts that claim 20 would have been obvious over the
`
`combination of Kawaguchi, Matsumoto, and Saito. For purposes of this
`
`Decision, Petitioner provides a reasonable rationale for adding Saito’s
`
`teachings to those of Kawaguchi and Matsumoto. Pet. 43–44. Thus, we are
`
`persuaded, on this record, that Petitioner has shown a reasonable likelihood
`
`on prevailing on its assertion that the asserted prior art combination renders
`
`claim 20.
`
`4. Obviousness Over Kawaguchi, Matsumoto, Saito, and Muramatsu
`
`Petitioner asserts that claim 23 would have been obvious over the
`
`combination of Kawaguchi, Matsumoto, Saito, and Muramatsu. For
`
`purposes of this Decision, Petitioner provides a reasonable rationale for
`
`adding Muramatsu’s teachings to those of Kawaguchi, Matsumoto, and
`
`Saito. Pet. 48–50. Thus, we are persuaded, on this record, that Petitioner
`
`has shown a reasonable likelihood on prevailing on its assertion that the
`
`asserted prior art combination renders claim 23.
`
`18
`
`

`
`IPR2016-01211
`Patent 8,504,746 B2
`
`
`5. Obviousness Over Kawaguchi, Matsumoto, and DASM-AD14
`
`Petitioner asserts that claims 21, 24, 25, 27, and 28 would have been
`
`obvious over the combination of Kawaguchi, Matsumoto, and DASM-
`
`AD14. For purposes of this Decision, Petitioner provides a reasonable
`
`rationale for adding DASM-AD14’s teachings to those of Kawaguchi and
`
`Matsumoto. Pet. 44–48, 50–53. Thus, we are persuaded, on this record, that
`
`Petitioner has shown a reasonable likelihood on prevailing on its assertion
`
`that the asserted prior art combination renders claims 21, 24, 25, 27, and 28.
`
`6. Obviousness Over Kawaguchi, Matsumoto, and Takahashi
`
`Petitioner asserts that claim 14 would have been obvious over the
`
`combination of Kawaguchi, Matsumoto, and Takahashi. Pet. 3637. Claim
`
`14 depends from claim 1 and further recites “wherein the analog source
`
`includes at least first and second transducers both of which are designed to
`
`transmit data.” Pointing to Takahashi’s image reading device, Petitioner
`
`asserts that Takahashi discloses the analog source with first and second
`
`transducers, as required by claim 14. Claim 1, however, requires an “analog
`
`signal acquisition channel,” which we have construed above as receiving an
`
`analog signal. Petitioner has now shown sufficiently how it contends that
`
`Kawaguchi’s “analog signal acquisition channel” (i.e, A/D converter 19)
`
`receives an analog signal from Takahashi’s image reader. Accordingly, we
`
`are not persuaded that Petitioner has shown a reasonable likelihood of
`
`prevailing with respect to the challenge of unpatentability of claim 14.
`
`7. Other Asserted Grounds
`
`
`
`Petitioner asserts a separate ground of unpatentability under § 102(b)
`
`as anticipated by Kawaguchi. However, in light of the determination that
`
`there is a reasonable likelihood that the challenged claims are unpatentable
`
`19
`
`

`
`IPR2016-01211
`Patent 8,504,746 B2
`
`based on the ground on which we institute an inter partes review, we
`
`exercise our discretion and decline to institute review on these asserted
`
`grounds of unpatentability. See 37 C.F.R. § 42.108(a); Synopsys, Inc. v.
`
`Mentor Graphics Corp., 814 F.3d 1309, 1316 (Fed. Cir. 2016) (holding that
`
`37 C.F.R. § 42.108(a) is “plainly an exercise” of the PTO’s rulemaking
`
`authority and “is a reasonable interpretation of the statutory provision
`
`governing the institution of inter partes review”); see also Harmonic Inc. v.
`
`Avid Tech., Inc., 815 F.3d 1356, 1366–1368 (Fed. Cir. 2016) (Pursuant to
`
`37 C.F.R. § 42.108(b), the Board may decline to institute some grounds
`
`asserted by the petitioner).
`
`III. CONCLUSION
`
`For the foregoing reasons, we institute inter partes review of claims
`
`112, 15, 1721, 2331, 34, and 35 of the ’746 patent based on the
`
`following grounds.
`
`Reference(s)
`
`Kawaguchi, and Matsumoto
`
`Kawaguchi, Matsumoto, and
`DASM-AD14
`Kawaguchi, Matsumoto, and
`Saito
`Kawaguchi, Matsumoto, Saito,
`and Muramatsu,
`
`
`Basis
`
`§ 103
`
`§ 103
`
`§ 103
`
`§ 103
`
`Claim(s)
`
`112, 15, 1719, 26,
`2931, 34, and 35
`21, 24, 25, 27, and 28
`
`20
`
`23
`
`We do not institute inter partes review as to claim 14 on any of the
`
`asserted grounds.
`
`
`
`At this point in the proceeding, we have not made a final
`
`determination with respect to the patentability of the challenged claims, nor
`
`with respect to claim construction.
`
`20
`
`

`
`IPR2016-01211
`Patent 8,504,746 B2
`
`
`
`IV. ORDER
`
`In consideration of the foregoing, it is hereby:
`
`ORDERED that the Petition is granted as to claim 112, 15, 1721,
`
`2331, 34, and 35 of the ’746 patent as stated in our Conclusion;
`
`FURTHER ORDERED that the Petition is denied as to claim 14; and
`
`FURTHER ORDERED that pursuant to 35 U.S.C. § 314(a), inter
`
`partes review of the ’746 patent is hereby instituted with trial commencing
`
`on the entry date of this decision, and pursuant to 35 U.S.C. § 314(c) and 37
`
`C.F.R. § 42.4, notice is hereby given of the institution of trial.
`
`
`
`21
`
`

`
`IPR2016-01211
`Patent 8,504,746 B2
`
`PETITIONER:
`
`T. Vann Pearce Jr. (Lead Counsel)
`PapstPTABPetitioners@Jonesday.com
`
`
`
`PATENT OWNER:
`
`Nicholas T. Peters
`ntpete@fitcheven.com (Lead Counsel)
`
`
`
`
`
`
`
`22

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