Rubicon Communications, LP
`Ex. 1044
`Rubicon Communications, LP
`v. LEGO A/S
`IPR2016-01187
`
`

`

`US. Patent
`
`Apr. 17, 2001
`
`Sheet 1 0f 7
`
`US 6,219,797 B1
`
`
`
`

`

`US. Patent
`
`Apr. 17, 2001
`
`Sheet 2 0f 7
`
`US 6,219,797 B1
`
`P0.0—P0.7
`
`¢
`(D
`
`P2.0—P2.7
`
`l' ______ 'I
`I
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`P1 .0-P1 .7
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`P3.0-P3.7
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`1
`IPortLatchISerialPort
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`

`US. Patent
`
`Apr. 17, 2001
`
`Sheet 3 0f 7
`
`US 6,219,797 B1
`
`Enter Power Management Mode
`
`Exiting Power Management Mode
`
` cause a switchbock
`
`N
`
`
`Allow
`
`hardware to
`
`
`
`
`Software deeded to exut
`
`—
`SW3“. .and external
`actwut occurs
`
`_
`CULCDO—Ol FOR 4
`
`'arware au oma ICO y
`switches CDl.CDO
`
`
` Check Status
`
`0
`
`514
`Y
`
`Check 8c clear
`
`im-cendin activit
`
`S16
`
` Invoke PMM
`
`Clock Speed=64 or 1024
`C01, CDO=1O or 64
`C01, CDO= 111 or 1024
`
`
`
`
`
`
`
`Operate without crystal
`
`I,
`
`Y M
`XT/RG = 0
`
`
`
`N
`
`Y m
`
`m
`
`>
`
`/RG=1
`
`$24
`
`Disable crystal?
`(no fast switch to XTAL
`
`822
`
`N
`
`
`
`

`

`US. Patent
`
`Apr. 17, 2001
`
`Sheet 4 0f 7
`
`US 6,219,797 B1
`
`STOP MODE WITHOUT START-UP
`
`400
`
`I/l/
`
`uC Operating
`Crystal
`OscillationW ........mmmIilllllllllllllll“l”mIH“mlI""“Hllmnnmll”
`l
`l
`l
`l
`
`uC Enters
`Interrupt
`Clock
`uC Enters
`STOP mode
`Clock starts
`stable
`STOP mode
`Power —_|—J———|—
`
`/l/
`uC Operating
`Crystal
`OscillationW)—
`
`402
`
`Ring
`Oscnllation__fl)_____—
`l
`l
`l
`
`uC Enters
`STOP mode
`Power saved
`PM"W
`
`uC Enters
`STOP mode
`
`Interrupt
`Ring starts
`
`Diagram assumes that the operation following STOP
`requires less than 16mS to complete.
`
`FIG. 4
`
`

`

`US. Patent
`
`Apr. 17, 2001
`
`Sheet 5 0f 7
`
`US 6,219,797 B1
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`

`

`US. Patent
`
`Apr. 17, 2001
`
`Sheet 6 0f 7
`
`US 6,219,797 B1
`
`
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`

`

`US. Patent
`
`Apr. 17, 2001
`
`Sheet 7 0f 7
`
`US 6,219,797 B1
`
`Allowed
`
`State
`
`8c CDO
`
`Flow for
`
`CD1
`
`Switch
`
`Back Paths
`
`Supported
`
`By External
`Interrupts or
`
`Activity
`
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`® 800
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`
`

`

`US 6,219,797 B1
`
`1
`MICROCONTROLLER WITH SELECTABLE
`OSCILLATOR SOURCE
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`
`This application is a continuation-in-part of Ser. No.
`08/412,664 filed Mar. 29, 1995, now abandoned, which is a
`continuation in part of both Ser. No. 08/015,691 filed Feb. 9,
`1993, now US. Pat. No. 5,473,271 and Ser. No. 08/196,273
`filed Feb. 9, 1994, now abandoned. These applications are
`all co-assigned and are also hereby incorporated by refer-
`ence.
`
`BACKGROUND OF THE PRESENT
`INVENTION
`
`1. Field of the Invention
`
`The present invention relates to integrated circuit elec-
`tronic devices, and, more particularly, to microcomputers,
`microcontrollers, and microprocessors.
`2. Background and Objects of the Present Invention
`The demand for ever higher performance from computers
`generally, and microprocessors and microcontrollers in
`particular, has led to various enhancements, including higher
`clock rates and simpler instruction sets. Consequently, the
`control and flexibility of clock speeds and rates for all
`circuits, especially microprocessor and microcontroller inte-
`grated circuits, has become critical, as designers attempt to
`design faster and faster microprocessors and microcontrol-
`lers. Previous control systems for oscillators were simplistic
`and/or relied primarily on prewired hardware circuits, which
`are not very flexible.
`
`SUMMARY OF THE INVENTION
`
`Preferred system embodiments of the disclosed CMOS
`8-bit Microcontroller System Specification have a number of
`unique features. Preferred embodiments provide the soft-
`ware control of either an external crystal oscillator or an
`on-chip internal ring oscillator, so that the user can choose
`whether to use external crystal oscillator or internal ring
`oscillator as the main source clock to the system. Preferred
`embodiments also provide for software control to disable/
`enable the external oscillator while running from the internal
`ring oscillator, so that the user has the ability to disable an
`external oscillator to reduce current consumption tremen-
`dously. Preferred embodiments also provide for software
`control to divide the main system clock (ring or external
`crystal oscillator) to provide lower operating current, so that
`the user can change system clock divide ratio to lower
`operating current. Preferred embodiments have software
`enable/disable of a “Switch-back” mode to allow interrupts
`or serial port activity to immediately switch high divide
`ratios (slow clocks) to a lower divide ratio (high speed
`clocks), which allows switching back immediately in the
`event of interrupts or serial port activity,
`it will process
`information as soon as possible without losing any kind of
`data. Preferred embodiments also enable the software selec-
`
`tion of a DX2 clocking system in which the DX2 clock
`generator is software enabled/disabled and provides 2><
`frequency multiplication of the crystal oscillator for use as
`an optional system clock source, so that the frequency is
`doubled. Preferred embodiments also provide a frequency
`doubler with 50 percent duty cycle.
`Preferred embodiments have the following features and
`advantages: compatible with Intel 80C52 (in that preferred
`embodiments have pin orientation and instruction sets that
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`are compatible with the Intel 8051, four 8-bit I/O ports, three
`16-bit
`timer/counters, and 256 bytes scratchpad RAM);
`large on-chip memory (16K bytes EPROM (OTP) and 1K
`byte extra on-chip SRAM for MOVX); ROMSIZE Feature
`(selects effective on-chip ROM size from 0 to 16K; allows
`access to entire external memory map; dynamically adjust-
`able by software and useful as boot block for external
`FLASH); High-Speed Architecture (4 clocks/machine cycle
`(Intel 8051 has 12); Runs DC to 33 MHZ clock rates;
`Single-cycle instruction in 121 nS; Dual data pointer;
`Optional variable length MOVX to access fast/slow RAM/
`peripherals; Power Management Mode (Programmable
`clock source to save power; CPU runs from (crystal/64) or
`(crystal/1024); provides automatic hardware and software
`exit); EMI Reduction Mode disables ALE; two full-duplex
`hardware serial ports; High integration controller (power-
`fail reset; early-warning power-fail interrupt; programmable
`Watchdog timer); and 16 total
`interrupt sources with 6
`external. Preferred embodiments have 40-pin PDIP, 44-pin
`PLCC, 44-pin PQFP, and 40-pin windowed CERDIP pack-
`ages.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Further features and advantages will become apparent
`from the following and more particular description of the
`various embodiments of the invention, as illustrated in the
`accompanying drawings, wherein:
`FIGS. 1A, 1B and 1C show diagrams of preferred pin-
`outs of preferred system embodiments;
`FIG. 2 is a system block circuit diagram of a preferred
`microcontroller;
`FIG. 3 is a flow chart showing the invoking and clearing
`of PMM;
`FIG. 4 is a timing diagram of a ring oscillator exit from
`stop mode;
`FIG. 5 is a functional/structural block circuit diagram
`showing at least a portion of the enhanced circuitry portion
`of an exemplary microprocessor.
`FIG. 6 is a preferred circuit diagram for a ring oscillator
`control circuit;
`FIG. 7 is a state diagram corresponding power manage-
`ment register; and
`FIG. 8 is a state diagram corresponding power manage-
`ment register.
`DETAILED DESCRIPTION OF THE
`PREFERRED EXEMPLARY EMBODIMENTS
`
`Generally, at the outset, note that preferred exemplary
`embodiments of the microcontroller disclosed below pro-
`vide one of the fastest 8051 compatible microcontrollers
`available. It features a redesigned processor core without
`wasted clock and memory cycles. FIG. 2 is a system block
`circuit diagram of a preferred embodiment of a microcon-
`troller 100, which includes the enhanced circuitry portion 20
`that provides for, among other things, the enhanced speed.
`Preferred embodiments of the present microcontroller
`execute every 8051 instruction between 1.3 and 3 times
`faster than an ordinary 8051 microprocessor for the same
`crystal speed. Typical applications will see a speed improve-
`ment of 2.5 times using the same code and the same crystal.
`Preferred embodiments offer a maximum crystal speed of
`33 MHZ, resulting in apparent execution speeds of 62.5
`MHZ (approximately 2.5><).
`Preferred embodiments are pin compatible with all three
`packages of the standard 8051 and include standard
`
`

`

`US 6,219,797 B1
`
`3
`resources such as 3 timer/counters, serial port, and four 8-bit
`I/O ports. It features 16K bytes of EPROM with an extra 1K
`byte of data RAM. Both OTP and windowed packages are
`available. FIGS. 1A, 1B and 1C show diagrams of preferred
`pin-outs of preferred system embodiments. Corresponding 5 DIP
`pin descriptions may be found in Chart 1 below:
`
`4
`
`TABLE 1-continued
`
`PIN DESCRIPTION
`
`PQFP
`
`NAME DESCRIPTION
`
`PLCC
`
`P .1
`
`P .2
`P .3
`P .4
`
`
`
`TABLE 1
`
`PIN DESCRIPTION
`
`NAME
`
`DESCRIPTION
`
`DIP
`
`PLCC
`
`40
`20
`
`44
`22, 23,
`
`10
`
`PQFP
`38
`16, 17,
`39
`4
`
`VCC
`GND
`
`RST
`
`18
`19
`
`20
`21
`
`14
`15
`
`XTAL2
`XTAL1
`
`29
`
`32
`
`26
`
`PSEN\
`
`30
`
`33
`
`27
`
`ALE
`
`39
`38
`37
`36
`35
`34
`33
`32
`
`43
`42
`41
`40
`39
`38
`37
`36
`
`37
`36
`35
`34
`33
`32
`31
`30
`
`P0.0
`P0.1
`P0.2
`P0.3
`P0.4
`P05
`P06
`P0.7
`
`1—8
`
`2—9
`
`40—44
`1—3
`
`P1.0—
`P1.7
`
`P20
`P21
`P22
`P23
`P24
`P25
`P26
`P27
`
`40
`
`41
`
`42
`43
`44
`
`1 2 3 1
`
`8
`19
`20
`21
`22
`23
`24
`25
`
`m4;
`
`LII-bu)
`
`21
`22
`23
`24
`25
`26
`27
`28
`
`24
`25
`26
`27
`28
`29
`30
`31
`
`10—
`17
`
`11, 13—
`19
`
`5, 7—13 P30—
`P37
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`VCC - +5 V
`GND - Digital circuit ground
`
`RST - Input. The RST input pin
`contains a Schmitt voltage input to
`recognize external active high Reset
`inputs. The pin also employs an
`internal pull-down resistor to allow
`for a combination of wired OR
`external Reset sources. An RC is not
`required for power-up, as the
`DS87C520 provides this function
`internally.
`XTAL1, XTAL2 - The crystal
`oscillator pins XTAL1 and XTAL2
`provide support for parallel
`resonant, AT cut crystals, XTAL1
`acts also as an input if there is an
`external clock source in place of a
`crystal. XTAL2 serves as the output
`of the crystal amplifier.
`PSEN\ - Output. The Program Store
`Enable output. This signal is com-
`monly connected to optional external
`ROM memory as a chip enable.
`PSEN\ will provide an active low
`pulse and is driven high when
`external ROM is not being accessed.
`ALE - Output. The Address Latch
`Enable output functions as a clock to
`latch the external address LSB from
`the multiplexed address/data bus on
`Port 0. This signal is commonly
`connected to the latch enable of an
`external 373 family transparent
`latch. ALE has a pulse width of 1.5
`XTAL1 cycles and a period of 4
`XTAL1 cycles. ALE is forced high
`when the DS87C520 is in a Reset
`condition. ALE can also be disabled
`using the EMI reduction mode.
`Port 0 (ADO-7) - I/O. Port 0 is an
`open-drain 8-bit bi—directional I/O
`port. As an alternate function Port
`0 can function as the multiplexed
`address/data bus to access, off-chip
`memory. During the time when ALE
`is high, the LSB of a memory address
`is presented. When ALE falls to a
`logic 0, the port transitions to a bi-
`directional data bus. This bus is
`used to read external ROM and
`read/write external ROM memory or
`peripherals. When used as a memory
`bus, the port provides active high
`drivers. The reset condition of Port
`0 is tri—state. Pull-up resistors
`are required when using Port 0 as an
`I/O port.
`Port 1 - I/O. Port 1 functions as
`both an 8-bit bi-directional I/O port
`and an alternate functional interface
`for Timer 2 I/O, new External
`Interrupts, and new Serial Port 1.
`The reset condition of Port 1 is with
`all bits at a logic 1. In this
`state, a weak pull-up holds the port
`
`high. This condition also serves as
`an input mode, since any external
`circuit that writes to the port will
`overcome the weak pull-up. When
`software writes a O to any port pin,
`the DS87C520 will activate a strong
`pull-down that remains on until
`either a 1 is written or a reset
`occurs. Writing a 1 after the port
`has been at 0 will cause a strong
`transition driver to turn on,
`followed by a weaker sustaining pull-
`up. Once the momentary strong
`driver turns off, the port again
`becomes the output high (and input)
`state. The alternate modes of Port 1
`are outlined as follows.
`Port
`Alternate Function
`P .0
`Ex ernal I/O for
`Timer/Counter 2
`Timer/Counter 2
`Ca3ture/Reload
`Trigger
`Serial Port 1 Input
`Serial Port 1 Output
`Ex ernal Interru 3t 2
`(Positive Edge
`De ect)
`Ex ernal Interru 3t 3
`(Negative Edge
`De ect)
`Ex ernal Interru 3t 4
`(Positive Edge
`De ect)
`Ex ernal Interru 3t 5
`(Negative Edge
`De ect)
`Port 2(AB-16) - I/O. Port 2 is a 3i-
`directional I/O port. The reset
`condition of Port 2 is logic high.
`In this state, a weak pull-up holcs
`he por high. This condition also
`serves as an input mode, since any
`externa circuit that writes to the
`aort wi l overcome the weak pul -up.
`When software writes an 0 to any
`aort pin, the DS87C520 will activate
`a strong pull-down that remains on
`until ei her a 1 is written or a
`reset occurs. Wri ing a 1 after the
`aort has been at 0 will cause a
`strong ransition driver to turn on,
`ollowed by wea {er sustaining pull-
`up. Once the momentary strong
`driver urns off, he port again
`aecomes both the output high and
`input s ate. As an alternate function
`Port 2 can function as MSB of the
`external address aus. This bus can
`3e usec to read external ROM and
`read/write external RAM memory or
`aeripherals.
`Port 3 - I/O. Por 3 functions as
`30th an 8-bit bi—directional I/O port
`and an alternate unctional interface
`or External Interrupts. Serial Port
`0, Timer 0 & 1 Inputs, and RD\ and
`WR\ Strobes. The reset condition of
`Port 3 is with all bits at a logic 1.
`In this state, a weak pull-up holds
`the port high. This condition also
`serves as an input mode, since any
`external circuit that writes to the
`port will overcome the weak pull-up.
`When software writes a 0 to any port
`
`T2
`
`T2EX
`
`RXD1
`TXD1
`INT2
`
`INT3\
`
`INT4
`
`INT5\
`
`
`
`
`
`
`
`
`
`
`
`

`

`US 6,219,797 B1
`
`5
`
`TABLE 1-continued
`
`PIN DESCRIPTION
`
`DIP
`
`PLCC
`
`PQFP
`
`NAME DESCRIPTION
`
`6
`Preferred embodiments provide several new hardware
`features implemented by new Special Function Registers
`(SFRs). A summary of these SFRs is provided below.
`Regarding the performance overview, preferred embodi-
`ments feature a high speed 8051 compatible core. Higher
`speed comes not just from increasing the clock frequency,
`but from a newer, more efficient design.
`This updated core does not have the dummy memory
`cycles that are present in a standard 8051. A standard 8051
`generates machine cycles using the clock frequency divided
`by 12. In preferred embodiments, the same machine cycle
`takes 4 clocks. Thus the fastest instruction, 1 machine cycle,
`executes 3 times faster for the same crystal frequency. Note
`that these are for identical instructions. The majority of
`instructions on preferred embodiments of the present inven-
`tion will see the full 3 to 1 speed improvement. Some
`instructions will get between 1.5 and 2.4 speed improve-
`ment. All instructions are faster than the original 8051.
`The numerical average of all opcodes gives approxi-
`mately a 2.5 to 1 speed improvement. Improvement of
`individual programs will depend on the actual instructions
`used. Speed sensitive applications would make the most use
`of instructions that are 3 times faster. However, the sheer
`number of 3 to 1 improved opcodes makes dramatic speed
`improvements likely for any code. These architecture
`improvements and 0.8M CMOS produce a peak instruction
`cycle in 121 nS (8.25 MIPS). The Dual Data Pointer feature
`also allows the user to eliminate wasted instructions when
`
`moving blocks of memory.
`
`Regarding the Instruction Set Summary, all instructions in
`preferred embodiments perform the same functions as their
`8051 counterparts. Their effect on bits, flags, and other status
`functions is identical. However, the timing of each instruc-
`tion is different. This applies both in absolute and relative
`number of clocks.
`
`Counter/timers default to run at the older 12 clocks per
`increment. In this way,
`timer-based events occur at
`the
`standard intervals with software executing at higher speed.
`Timers optionally can run at 4 clocks per increment to take
`advantage of faster processor operation.
`
`The relative time of two instructions might be different in
`the new architecture. For example,
`in the original
`architecture, the “MOVX A, @DPTR” instruction and the
`“MOV direct, direct” instruction used two machine cycles or
`24 oscillator cycles. Therefore,
`they required the same
`amount of time. In preferred embodiments,
`the MOVX
`instruction takes as little as two machine cycles or 8 oscil-
`lator cycles but the “MOV direct, direct” uses three machine
`cycles or 12 oscillator cycles. While both are faster than their
`original counterparts,
`they now have different execution
`times. This is because preferred embodiments usually use
`one machine instruction cycle for each instruction byte.
`
`Regarding the Special function Registers (“SFRs”), SFRs
`control most special features of preferred embodiments.
`This allows preferred embodiments to have many new
`features but use the same instruction set as an 8051. When
`
`writing software to use a new feature, an equate statement
`defines the SFR to an assembler or compiler. This is the only
`change needed to access the new function. Preferred
`embodiments duplicate the SFRs contained in the standard
`80C52. Table 2 shown below shows the register addresses
`and bit locations. Many are standard registers.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`RXDO
`TXDO
`INTO\
`INT1\
`TO
`
`P3.5
`
`T1
`
`pin, the DS87C520 will activate a
`strong pull-down that remains on
`until either a 1 is written or a
`reset occurs. Writing a 1 after the
`port has been at 0 will cause a
`strong transaction driver to turn on,
`followed by a weaker sustaining pull-
`up. Once the momentary strong
`driver turns off, the port again
`becomes both the output high and
`input state. The alternate modes of
`Port 3 are outlined below.
`Port
`Alternate Mode
`P3.0
`Serial Port 0 Input
`P3.1
`Serial Port 0 Output
`P3.2
`External Interrupt 0
`P33
`External Interrupt 1
`P34
`Timer 0 External
`Input
`Timer 1 External
`Input
`External Data
`Memory
`Write Strobe
`External Data
`Memory
`Read Strobe
`EA\ - Input. Connect to ground to
`force the DS87C520 to use an exter-
`nal ROM. The internal RAM is still
`accessible as determined by register
`settings. Connect EA\ to VCC to use
`internal ROM.
`NC - Reserved. These pins should not
`be connected. They are reserved for
`use with future devices in this
`family.
`
`P3.6 WR\
`
`P3.7 RD\
`
`10
`11
`12
`13
`14
`
`15
`
`16
`
`17
`
`31
`
`11
`13
`14
`15
`16
`
`17
`
`18
`
`19
`
`35
`
`12
`34
`
`HOWQUI
`
`0
`
`11
`
`12
`
`13
`
`29
`
`EA\
`
`6
`
`NC
`
`Besides greater speed, preferred embodiments may com-
`prise a second serial port, seven additional interrupts, a
`programmable watchdog timer, a brown-out monitor, and
`power-fail reset circuitry.
`Preferred embodiments are also fully static CMOS 8051
`compatible microcontrollers designed for high performance.
`In most cases, preferred embodiments can be placed into an
`existing socket for the 80C51, 80C52, 87C51, or 87C52 to
`improve the overall circuit operation significantly. While
`remaining familiar to 8051 family users, the present exem-
`plary microcontroller has many new features. In general,
`software written for existing 8051 based systems works
`without modification on preferred system embodiments. the
`exception to this is that critical timing functions may not
`operate correctly since the High Speed Micro performs its
`instructions much faster than the Standard 8051 for any
`given crystal selection. Preferred embodiments run the stan-
`dard 8051 family instruction set and is pin compatible with
`DIP, PLCC or QFP packages.
`Preferred embodiments of the present microcontroller
`provide three 16-bit timer/counters, full-duplex serial port
`(2), 256 bytes of direct RAM plus 1K bytes of extra MOVX
`RAM. I/O ports have the same operation as a standard 8051
`product. Timers default to a 12 clock per cycle cooperation
`to keep their timing compatible with original 8051 family
`systems. However, timers are individually programmable to
`run at the new 4 clocks per cycle if desired.
`
`

`

`US 6,219,797 B1
`
`TABLE 2
`
`SPECIAL FUNCTION REGISTER LOCATIONS
`
`BIT7
`
`PO.7
`
`BIT6
`
`PO.6
`
`BIT5
`
`P05
`
`BIT4
`
`PO.4
`
`BIT3
`
`P03
`
`BIT2
`
`P02
`
`BII‘1
`
`PO.1
`
`BITO
`
`P0.0
`
`ADD.
`
`80h
`81h
`
`82h
`83h
`84h
`85h
`86h
`87h
`88h
`89h
`8Ah
`8Bh
`8Ch
`8Dh
`8Eh
`90h
`91h
`98h
`99h
`A0 1
`A8 1
`A9 1
`AAH
`BO
`B8 1
`B9 1
`BAH
`C6—Oh
`R1
`T1
`C1 1
`SBO
`SB1
`C2 1
`RSO
`R51
`C4 1
`DMEO
`DME1
`SPTAO SPRAO C5 1
`C7 1
`CP/RL2 C8 1
`DCEN C9 1
`CAh
`CBh
`CCh
`CDh
`DOh
`Dah
`EOh
`E8h
`FOh
`F8h
`
`0
`0
`0
`SMOD SMODO —
`TF1
`TR1
`TFO
`GATE
`C/T\
`M1
`
`WDO
`WD1
`P1.6
`P1.7
`IE4
`IE5
`SMO/FE SM1
`SB7
`SB6
`P2.7
`P2.6
`EA
`ES1
`
`P3.7
`—
`
`P3.6
`PS1
`
`T2M
`P15
`IE3
`SM2
`SB5
`P25
`ET2
`
`P35
`PT2
`
`0
`—
`TR0
`M0
`
`TlM
`P1.4
`IE2
`REN
`SB4
`P2.4
`ES0
`
`P3.4
`PS0
`
`0
`GFl
`IE1
`GATE
`
`0
`GFO
`1T1
`C/T\
`
`MD2
`TOM
`P12
`P13
`XT/RG RGMD
`TB8
`RB8
`SB3
`SB2
`P23
`P22
`ET1
`EX1
`
`P33
`PT1
`
`P32
`Px1
`
`SMO/FE SM1
`SB7
`SB6
`—
`—
`CD1
`CD0
`PIP
`HIP
`
`REN
`SM2
`SB4
`SB5
`—
`—
`SWB —
`LIP
`XTUP
`
`RB8
`TB8
`SB2
`SB3
`RS2
`—
`XTOFF ALEOFF
`SPTA1
`SPRA1
`
`TE2
`EXF2
`RCLK TCLK EXEN2 TR2
`
`
`AC
`CY
`SMOD POR
`
`FO
`EPE2
`
`RS1
`EE2
`
`0v
`RS0
`WDIF WTRF
`
`—
`
`—
`
`—
`
`—
`
`—
`
`—
`
`EWDl
`
`Ex5
`
`PWDl
`
`Px5
`
`EX4
`
`PX4
`
`REGISTER
`
`P0RT0
`STACK
`POINTER
`DPL
`DPH
`DPLl
`DPH1
`DPS
`PCON
`TCON
`TMOD
`TLO
`TL1
`THO
`TH1
`CKCON
`P0RT1
`EXIF
`SCONO
`SBUFO
`P0RT2
`IE
`SADDR0
`SADDRl
`P0RT3
`IP
`SADEN0
`SADENl
`SCONl
`SBUFl
`ROMSIZE
`PMR
`STATUS
`TA
`T2C0N
`T2M0D
`RCAP2L
`RCAP2H
`TL2
`TH2
`PSW
`WDCON
`ACC
`EIE
`
`BE
`
`IP
`
`O
`STOP
`IEO
`M1
`
`SEL
`IDLE
`ITO
`M0
`
`MD1
`P1.1
`RGSL
`T1
`SB1
`P2.1
`ETO
`
`P3.1
`PTO
`
`MDO
`P1.0
`BGS
`R1
`SBO
`P2.0
`EXO
`
`P3.0
`PXO
`
`C/I‘2\
`T2CE
`
`FL
`EWT
`
`EX3
`
`PX3
`
`P
`RWT
`
`WX2
`
`PX2
`
`
`
`*New Functions in Bold
`
`Referring to FIG. 2 and regarding memory resources, like
`the 8051, preferred embodiments use three memory areas.
`These are program (ROM), data (RAM), and scratchpad
`RAM (registers). Preferred embodiments contain on-chip
`quantities of all three areaS.
`The total memory configuration of preferred embodi-
`ments is 16K bytes of ROM 40, 1K byte of data SRAM 42
`and 256 byteS of scratchpad or direct RAM 44. The 1K byte
`of data Space SRAM 42 is read/write accessible and is
`memory mapped. This on-chip SRAM is reached by the
`MOVX instruction. It is not used for executable memory.
`The scratchpad area is 256 byteS of register mapped RAM
`44 and is identical to the RAM found on preferred embodi-
`ments. There is no conflict or overlap among the 256 byteS
`and the 1K aS they “use” or “are accessed by” different
`addressing modes and separate instructions.
`Regarding program memory access, on-chip ROM 40
`begins at address 0000h and is contiguous through 3FFFh
`(16K). Exceeding the maximum address of on-chip ROM
`will cause preferred embodiments to access off-chip
`memory. However, the maximum on-chip decoded address
`
`50
`
`55
`
`6O
`
`65
`
`is selected by software using the ROMSIZE feature. Soft-
`ware can cause preferred embodiments to behave like a
`device with leSS on-chip memory. This is beneficial when
`overlapping external memory, such aS FLASH, is used.
`
`The maximum memory Size is dynamically variable.
`Thus, a portion of memory can be removed from the
`memory map to access off-chip memory, then restored to
`access on-chip memory. In fact, all of the on-chip memory
`can be removed from the memory map allowing the full 64K
`memory Space to be addressed from off-chip memory. ROM
`addresses that are larger than the selected maximum are
`automatically fetched from outside the part via Ports 0 & 2.
`
`ROMSIZE register is used to select the maximum on-chip
`decoded address of ROM. Bits RSZ, RSI, RSO have the
`following effect.
`
`

`

`US 6,219,797 B1
`
`10
`
`TABLE 3
`
`RS2
`0
`0
`0
`0
`1
`1
`1
`1
`
`RS1
`0
`0
`1
`1
`0
`0
`1
`1
`
`RSO
`0
`1
`0
`1
`0
`1
`0
`1
`
`Maximum on-chip ROM Address
`0K
`1K
`2K
`4K
`8K
`16K (default)
`Invalid - reserved
`Invalid - reserved
`
`The reset default condition is a maximum on-chip ROM
`address of 16K bytes. Thus, no action is required if this
`feature is not used. Thus when accessing external program
`memory, the first 16K bytes would be inaccessible. To select
`a smaller effective ROM size, software must alter bits
`RSZ-RSO. Altering these bits requires a Timed Access pro-
`cedure as explained below.
`The ROMSIZE register should be manipulated from a
`safe area in the program memory map. This is a program
`memory address that will not be affected by the change. For
`example, one should not select a maximum ROM size of 4K
`from an internal ROM address of 5K. This would cause a
`current address to switch from internal to external and cause
`
`invalid operation. Similarly, one should not instantly switch
`from external to internal memory. For example, do not select
`a maximum ROM address of 16K from an external ROM
`address of 12K.
`
`Off-chip memory is accessed using the multiplexed
`address/data bus on P0 and the MSB address of P2. While
`serving as a memory bus, these pins are not I/O ports. This
`convention follows the standard 8051 method of expanding
`on-chip memory. Off-chip ROM access also occurs if an EA\
`pin is a logic 0. The EA\ overrides all bit settings. The
`PSEN\ signal will go active (low) to serve as a chip enable
`or output enable when Ports 0 & 2 fetch from external ROM.
`Regarding data memory access, unlike many 8051
`derivatives, preferred embodiments contain on-chip data
`memory. It also contains the standard 256 bytes of RAM
`accessed by direct instructions. These areas are separate. The
`MOVX instructions access the on-chip data memory.
`Although physically on-chip, software treats this area as
`though it was located off-chip. The 1K byte of SRAM is
`between address 000h and 03FFh.
`
`Access to the on-chip data RAM 42 is optional under
`software control. When enabled by software,
`the data
`SRAM is between 000h and 03FFh. Any MOVX instruction
`that uses this area will go to the on-chip RAM while enabled.
`MOVX addresses greater than 1K automatically go to
`external memory through Ports 0 & 2.
`When disabled, the 1K SRAM memory area 42 is trans-
`parent to the system memory map. Any MOVX directed to
`the space between 0000h and FFFFh goes to the expanded
`bus on Ports 0 & 2 (46, 48). This also is the default
`condition. This default allows preferred embodiments to
`drop into an existing system that uses these addresses for
`other hardware and still have full compatibility.
`The on-chip data area is software selectable using two bits
`in the Power Management Register 50 at location C4h. This
`selection is dynamically programmable. Thus access to the
`on-chip area becomes transparent to reach off-chip devices
`at the same addresses. The control bits are DME1 (PMR.1)
`and DMEO (PMR.0). They have the following operation:
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`DATA MEMORY ACCESS CONTROL
`
`DME1
`
`Data Memory
`DMEO Address
`
`Memory
`Function
`
`0
`
`0
`1
`1
`
`0
`
`1
`0
`1
`
`OOOOh-FFFFh
`
`OOOOh-OSFFh
`0400h-FFFFh
`Reserved
`OOOOh-OSFFh
`0400h-FFFBh
`FFFCh
`
`External Data Memory
`*Default Condition
`Internal SRAM Data Memory
`External Data Memory
`
`Internal SRAM Data Memory
`Reserved-no external access
`Read access to the status
`of lock bits
`
`Regarding the stretch memory cycle, preferred embodi-
`ments allow software to adjust the speed of off-chip data
`memory access. The micro is capable of performing the
`MOVX in as little as two instruction cycles. The on-chip
`SRAM 42 uses this speed and any MOVX instruction
`directed internally uses two cycles. However, the time can
`be stretched for interface to external devices. This allows
`
`access to both fast memory and slow memory or peripherals
`with no glue logic. Even in high-speed systems, it may not
`be necessary or desirable to perform off-chip data memory
`access at full speed. In addition, there is a variety of memory
`mapped peripherals such as LCDs or UARTs that are slow.
`
`The Stretch MOVX is controlled by the Clock Control
`Register at SFR location 8Eh as described below. It allows
`the user to select a Stretch value between zero and seven. A
`
`stretch of zero will result in a two machine cycle MOVX. A
`Stretch of seven will result in a MOVX of nine machine
`
`cycles. Software can dynamically change this value depend-
`ing on the particular memory or peripheral.
`
`On reset, the Stretch value will default to a one resulting
`in a three cycle MOVX for an external access. Therefore,
`off-chip RAM access is not at full speed. This is a conve-
`nience to existing designs that may not have fast RAM in
`place. Internal SRAM access is always at full speed regard-
`less of the Stretch setting. When desiring maximum speed,
`software should select a Stretch value of zero. When using
`very slow RAM or peripherals, select a larger Stretch value.
`Note that this affects data memory only and the only way to
`slow program memory (ROM) access is to use a slower
`crystal.
`
`Using a Stretch value between one and seven causes the
`microcontroller to Stretch and read/write strobe and all
`related timing. Also, setup and hold times are increased by
`1 clock when using a Stretch greater than 0. This results in
`a longer read/write strobe and relaxed interface timing,
`allowing more time for memory/peripherals to respond. The
`timing of the variable speed MOVX is in the Electrical
`Specifications. Table 4 below shows the resulting strobe
`widths for each Stretch value. The memory Stretch uses the
`Clock Control Special Function Register at SFR location
`8Eh. The Stretch value is selected using bits CKCON.2-0. In
`the table, these bits are referred to as M2 through M0. The
`first Stretch (default) allows the use of common 120 nS
`RAMs without dramatically lengthening the memory access.
`See Table 4.
`
`

`

`US 6,219,797 B1
`
`11
`
`TABLE 4
`
`DATA MEMORY CYCLE STRETCH VALUES
`
`CKCON. 2-0 MEMORY
`
`RD/ 0r WR/
`STROBE WIDTH
`
`STROBE WIDTH
`TIME @
`
`M2 M1 M0
`
`CYCLES
`
`IN CLOCKS
`
`0
`
`0
`
`0
`0
`1
`1
`1
`1
`
`0
`
`0
`
`1
`1
`0
`0
`1
`1
`
`0
`
`1
`
`0
`1
`0
`1
`0
`1
`
`2
`(forced
`internal)
`3
`(default
`external)
`4
`5
`6
`7
`8
`9
`
`2
`
`4
`
`8
`12
`16
`20
`24
`28
`
`33 MHZ
`
`60 nS
`
`121 nS
`
`242 nS
`364 nS
`485 nS
`606 nS
`727 nS
`848 nS
`
`the timing of block
`Regarding the dual data pointers,
`moves of data memory is faster using Dual Data Pointer
`(DPTR) 52. The standard 8051 DPTR is a 16-bit value that
`is used to address off-chip data RAM or peripherals. In
`preferred embodiments, this data pointer is called DPTRO,
`located at SFR addresses 82h and 83h. These are the original
`locations. Using DPTRO requires no modification of stan-
`dard code. The new DPTR at SFR 84h and 85h is called
`
`DPTRl. The DPTR Select bit (DPS) chooses the active
`pointer. Its location is the 1 sb of the SFR location 86h. No
`other bits in register 86h have any effect and are 0. The user
`switches between data pointers by toggling the 1 sb of
`register 86h. The increment (INC) instruction is the fastest
`way to accomplish this. All DPTR-related instructions use
`the currently selected DPTR for any activity. Therefore it
`takes only one instruction to switch from a source to a
`destination address. Using the Dual Data Pointer saves code
`from needing to save source and destination addresses when
`doing a block move. The software simply switches between
`DPTRO and DPTRl 52 once software loads them. The
`relevant register locations are as follows:
`
`DPID
`DPHO
`DPL1
`DPH1
`DPS
`
`82h
`83h
`85h
`85h
`86h
`
`Low byte original DPTR
`High byte original DPTR
`Low byte new DPTR
`High byte new DPTR
`DPTR Select (15b)
`
`Regarding power management circuitry, along with the
`standard IDLE and power down (STOP) modes of the
`standard referred embodiments, preferred embodiments pro-
`vided a new Power Management Mode. This mode allows
`the processor to continue functioning, yet to save power
`compared with full operation. Preferred embodiments also
`feature several enhancements to STOP mode that make it
`more useful.
`
`Regarding the power management mode (PMM), power
`management mode offers a complete scheme of reduced
`internal clock speeds that allow the CPU to run software and
`use substantially less power. During default operation, pre-
`ferred embodiments use 4 clocks per machine cycle. Thus
`the instruction cycle rate is Clock/4. At 33 MHZ crystal
`speed, the instruction cycle speed is 8.25 MHZ (33/4). In
`PMM, the microcontroller continues to operate but uses an
`internally divided version of the clock source. This creates
`a lower power state without external components. It offers a
`choice of two reduced instruction cycle speeds (and two lock
`sources—discussed below). The speeds are (Clock/64) and
`(Clock/1024).
`
`12
`PMM is preferably invoked via software. Table 5 illus-
`trates the instruction cycle rate in PMM for several common
`crystal frequencie