Rubicon Communications, LP
`Ex. 1042
`Rubicon Communications, LP v.
`LEGO A/S
`IPR2016-01187
`
`

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`US. Patent
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`Apr. 16, 1996
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`Sheet 1 of 8
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`5,508,836
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`+5V
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` IRDA
`COMPLIANT
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`US. Patent
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`Apr. 16, 1996
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`Sheet 2 of 8
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`5,508,836
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`US. Patent
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`Apr. 16, 1996
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`Sheet 3 of 8
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`Apr. 16, 1996
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`Sheet 5 of 8
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`US. Patent
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`Apr. 16, 1996
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`Sheet 6 of 8
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`US. Patent
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`Apr. 16, 1996
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`Sheet 7 of 8
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`US. Patent
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`Apr. 16, 1996
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`Sheet -8 of 8
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`5,508,836
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`20>
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`

`1
`INFRARED WIRELESS COMIVIUNICATION
`BETWEEN ELECTRONIC SYSTEM
`COMPONENTS
`
`BACKGROUND OF THE INVENTION
`
`This invention relates to two-way wireless communica—
`tion using infrared radiation as a transmission medium. It
`may be used in electronic systems for interaction between
`computers, peripherals, and serial communication ports,
`where relatively short distance information exchanges are
`needed. The information is conveyed by infrared (IR)
`pulses. The primary interest is in serial IR (SIR) communi-
`cation, but parallel IR is also feasible.
`The use of infrared communications channels allows for
`
`short range, point—to—point data transfer and communica-
`tions. Palmtop and laptop computers,
`in particular, will
`benefit from the ability to communicate without increasing
`system size, weight and, most importantly, power dissipa-
`tion. Moreover, the use of wireless IR eliminates the need for
`bulky connectors. Wireless IR also has potential in many
`other applications, including information consumer appara-
`tus, e.g., cellular phones, pagers and watches, remote unit
`data down-load, computer tablets, barcode readers, wireless
`LANs, data logging equipment, and more. Wireless IR has
`a potential application in any data transfer application where
`mechanical connector interface is impractical.
`Recent developments have introduced such wireless com-
`munication systems, initially as a means of enhancing com-
`puter system portability. The infrared Data Association
`(IrDA) has pioneered standards for short-range, point-to-
`point communications. Narrow-field infrared is considered
`desirable for such communications. Each component in the
`communications network has a transmitter and a receiver.
`
`The following relevant information is copied from an
`article in Electronic Engineering Times (Feb. 21, 1994):
`The user model is a walk-up, point-to—point connection
`model.
`It
`involves making a conscious connection
`between the mobile and the fixed assets in the work
`environment, including desktop computers, printers,
`systemizers, modems, and, later, telephones.
`Depending on the system maker,
`the operating range
`varies between either 0 to l or 0 to 3 meters. The
`number zero is actually a system driver, because mak—
`ers of the earliest systems using serial IR found that
`users, when they aren’t getting the kind of response
`they want, tend to put the diodes right next to each
`other. This fact stresses the dynamic-range requirement
`in the analog portion of the receiver. The l— or 3-meter
`numbers relate to what different company focus groups
`have found that users want. These groups have also
`found that a 30° cone (the angular relationship between
`the transmitter and receiver) is suflicient for doing
`serial IR.
`
`IrDA members have already agreed on a number of key
`technical parameters. First, the maximum baud rate to
`be supported is 115.2 kbits/second. This is also the
`maximum baud rate for high speed PC serial ports.
`IrDA has decided to leave open the possibility of moving
`to l Mbit/s in the future. Such a jump requires a change
`in the wavelength of IrDA-compliant devices to 880
`nm from 950 nm used in existing devices. Yet, most
`880-nm devices still will be able to converse with
`950—nm devices. Beyond this, serial IR operates in
`half-duplex and assumes an asynchronous charter—
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`receiver/transmitter
`asynchronous
`based universal
`(UART) interface. To minimize power, the transmitter
`time is either 3/16 of the bit rate, or 1.6 microseconds.
`
`In the hardware portion of the serial IR approach, the link
`data comes from a UART. The format transmitter takes
`
`this data and translates it to a 3/15 pulse that is 3/16 of the
`bit time, or 1.6 microseconds. In other words,
`the
`format transmitter limits the duty cycle on the light
`pulse via the interaction of the shift register and the
`flip/flop. Specifically, the shift register outputs 1/16 the
`data and the flip/flop runs it out to 3/16 before closing
`off. Following this step, a GaAlAs LED translates the
`“data” current into “data” photons.
`On the receiving side, a lensed photodiode detector
`receives the “data” photons from the transmitter and
`translates it back into “data” current. The recovered
`
`current is amplified, digitized, and input to a format
`decoder to stretch the data back to the full bit time.
`
`Key trade-oifs concern range vs. power, and power con-
`sumption vs. battery life, especially if the system needs
`a sleep mode. Accomplishing any of these allows
`increased receiver sensitivity and reduced transmitter
`power. The move to 3 meters alone requires a tenfold
`increase in power if the receiver system sensitivity does
`not increase. The best solutions will need to be able to
`take advantage, where possible, of low—power opera-
`tion, especially because many PDAs are planning to
`operate on AA or AAA batteries.
`Regardless of the implementation, one issue is clear: The
`complete hardware system must be inexpensive. Many
`systems makers have already indicated their target cost
`for all elements of a system is less than $5.
`The foregoing quotation identifies several problems in
`providing a satisfactory wireless IR system:
`(1) A wide dynamic range is necessary because of the
`variations in distance between transmitter and receiver.
`
`(2) High speed signal transmission is required, and delays
`within and between transmissions must be minimized.
`
`(3) The intention to use batteries calls for significant
`conservation of power.
`Experience has shown that it is very diflicult to provide a
`receiver which satisfies the desires of potential users, as
`outlined in the quoted material. In fact, it appears that no
`satisfactorily workable SIR receiver has been developed
`prior to the present invention.
`SUMMARY OF THE INVENTION
`
`The present invention deals successfully with the chal-
`lenges identified by IrDA. But it also provides insights and
`solutions going beyond the IrDA analysis.
`is to
`An important need from a practical standpoint
`provide a receiver which is ready to receive signals at all
`times,
`i.e., which is “on” in what might be termed an
`“idling” mode. The practical advantage is that the transmit-
`ter isn’t required to communicate with the receiver to turn it
`on before transmitting. This need, combined with the
`planned use of relatively low power batteries, necessitates
`drastic power reduction in the receiver. It appears that this
`issue has not been recognized prior to this invention.
`Another important need, which apparently has not previ-
`ously been perceived, is the elimination of “down” time in
`the system due to saturation of the receiver input. At least
`two sources of such saturation exist.
`
`A major, and perhaps primary, saturation problem in serial
`IR devices is due to the wide dynamic range necessitated by
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`5,508,836
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`3
`frequent variations in the distance between transmitter and
`receiver. The signal strength at the receiver will vary by at
`least an order of magnitude as distance from the transmitter
`is varied.
`'
`
`Another cause of saturation is the proximity to the
`receiver of the transmitter which is included in the same
`package, i.e., the transmitter which sends response signals to
`the other unit involved in the wireless communication. With
`a receiver and transmitter mounted side-by—side, any signal
`sent from the transmitter will cause a delay before the
`receiver can function, unless the saturation problem is
`solved.
`
`the present
`In dealing with the battery-life problem,
`invention provides a receiver for a wireless two-way con-
`nection which reduces the required power by an order of
`magnitude (or more) compared to receivers previously
`developed. At the same time, size, cost, and noise are
`minimized.
`
`In order to attain very low power in the receiver operation,
`the circuitry uses mosfet transmitters operating in the sub-
`threshold (weak inversion) region. Such sub-threshold tran-
`sistor operation is combined with other transistors operating
`in strong inversion, where such higher power operation is
`necessary.
`
`The use of sub-threshold amplification, because it
`requires low input current values, is associated with high
`impedance values, which in turn tend to increase noise
`problems and cross-talk problems. Also adequate bandwidth
`must be maintained. The present invention provides solu-
`tions for these problems, based on extensive research and
`testing efforts.
`In dealing with the problem caused by possible receiver
`amplifier saturation, the present invention radically differs
`from prior devices, in which downtime has generally been
`about ten milliseconds. In other words, saturation, for any
`reason, would cause a 10 ms delay before subsequent
`processing of signals. One reason for the long delay has been
`the conventional use of automatic gain control (AGC) as a
`saturation-controlling concept at the receiver input amplifier.
`The present invention provides novel circuitry, which
`may be referred to as “clamping” circuitry, which tends to
`prevent saturation, and eliminate the resulting recovery
`period. Using the present invention, saturation recovery time
`has been reduced to a point where no signal transfer delay
`occurs.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`FIG. 1 is a diagrammatic showing of a Serial IR (SIR)
`operating circuit;
`FIG. 2 is a schematic showing diagrammatically the
`circuitry of the receiver portion of an SIR apparatus;
`FIG. 3 shows schematically the components of the input
`amplifier of the SIR receiver;
`FIG. 4 shows schematically the details of the clamp
`circuit, which prevents saturation of the input amplifier.
`FIG. 5 shows schematically the details of amplifier 48;
`FIG. 6 shows the circuin details of amplifier 52;
`FIG. 7 shows the circuitry details of comparator 54;
`FIG. 8 shows the circuitry details of output buffer 58; and
`FIG. 9 shows the circuitry details of bias block 60.
`DETAILED DESCRIPTION OF PREFERRED
`EMBODIMENT
`
`FIG. 1 shows a typical Serial IR operating circuit. Each
`unit has a universal asynchronous
`receiver/transmitter
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`(UART) interface 20. It also has a transmitter 22 and a
`receiver 24. The transmitter 22 will send pulsed signals to
`the receiver of another UART; and the receiver 24 will
`receive pulsed signals from the transmitter of another
`UART. For example, one operating circuit of the type shown
`in FIG. 1 might be mounted on a portable computer, and
`another such operating circuit might be mounted on a printer
`signals can be sent in both directions, but not at the same
`trme.
`
`The present invention is concerned primarily with the
`receiver circuitry. The transmitter signal may be sent from
`an LED 26, and received by a photodetector (photodiode)
`28. The most critical part of the system is the receiver
`circuitry represented by block 30. This circuitry is preferably
`a custom designed integrated circuit (IC) chip, rather than a
`collection of discrete circuit components.
`As shown in FIG. 1, the chip 30 may have eight (or more)
`connection pins. Pin 1 is connected to the cathode of
`photodiode 28, and to a capacitor 32 (e.g., 10 pi). Pin 2 is
`connected to the anode of photodiode 28. Pin 3 is designated
`Vss analog, and is connected to ground 34. Pin 4 is desig-
`nated Vss digital, and is connected to ground 34.
`Pin 5 is output, and is connected to UART 20 or to
`receiver format decoder logic. Pin 6 is used to switch
`between 1 meter operation and 3 meter operation. It is
`connected at 36 to Vdd for 1 meter operation, and is
`connected to Vss or is left floating for 3 meter operation. Pin
`7 is used to switch between 5 volt and 3 volt operation. It is
`connected to Vdd for 5V supply and is connected to Vss or
`is left floating for 3V operation. Pin 8 is connected to the
`plus terminal of power supply 36.
`FIG. 2 is a schematic showing diagrammatically the
`circuitry of receiver 30, which is preferably incorporated
`into a single IC chip. The incoming information signals are
`pulsed, and the eventual receiver output is pulsed. However,
`the signals require initial stages of amplification in the
`analog mode, prior to later amplification in the digital mode.
`The analog mode amplification is important for purposes of
`range variation, and noise avoidance.
`Prior to the present invention, the SIR receiver circuits
`have generally been provided by combining discrete com-
`ponents, a strategy aimed at cost reduction. The present
`invention provides completely redesigned receiver circuitry,
`preferably incorporated into a single IC chip.
`As stated above, the present invention has reduced the
`required receiver power by at least an order of magnitude. It
`is believed to be the first receiver provided for full time
`availability, i.e., it is kept “on” at a low quiescent current,
`removing the need for on—oif switching.
`Using batteries, particularly small batteries (e.g., size AA
`or AAA) limits the available power needed to keep the
`receiver continuously ready for signal inputs. It has been
`generally established that a quiescent current drain in the
`neighborhood of 100 microamps (uA) is the maximum
`power level usable in a receiver—ready SIR. Above that
`current level, battery life would be too short, or batteries
`would be too large and heavy, to satisfy user needs.
`The present receiver has succeeded in reducing the qui-
`escent receiver-ready current as low as 11 microamps. But
`this has been accomplished by violating conventional wis-
`dom. This “violation” involves the extensive use of mosfet
`transistors operating in the sub-threshold (weak inversion)
`region, as distinguished from the usual strong—inversion
`region. Strong inversion is referred to as the “square law
`region”. Weak inversion is referred to as the “logarithmic
`region”.
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`The present invention, for the first time, uses transistors
`operating in the sub-threshold mosfet region in an SIR
`receiver. This has required complete and repeated redesign
`and testing, because of the practical difliculties encountered.
`Although the availability of sub-threshold operation of mos-
`fets has been known,
`the prevailing models for mosfet
`design have been dictated by the digital industry, where low
`power has not been a major goal. Analog design of mosfet
`transistors has been neglected.
`There are inherent trade-offs involved in sub-threshold
`
`mosfet operation. When power is lowered, bandwidth will
`be lowered, unless voltage is also lowered. Voltage swing is
`restricted by the use of subthreshold operation. As voltages
`are lowered, noise becomes a greater problem, because the
`signal—to~noise ratio is reduced.
`The receiver circuitry described below has been designed
`to meet the low power targets, without creating functional
`problems in the receiver.
`Referring to FIG. 2, pin 2 is the input signal to the receiver
`circuitry from the IR detector diode 28. Input amplifier 40 is
`a transimpedance amplifier, which converts the current on
`line 42 from the detector 28 into a voltage at output 44.
`Amplifier 40 is designed with a unique circuit configuration
`that reverse biases the detector diode, and stabilizes the input
`amplifier with varying detector quiescent current levels. If
`the detector current exceeds the linear operating range of
`amplifier 40, a clamp circuit 46 will divert current from
`input 42 to ground. This preserves the low impedance
`presented to the detector by amplifier 40, which in turn
`maintains the amplifier signal bandwidth. The signal
`is
`amplified and bandpass filtered by amplifier 48, which
`outputs at 50.
`The incoming signal is a pulsed signal, which doesn’t
`allow an additional AC-coupled stage at the comparator.
`Therefore, a DC compensation circuit is required to elimi—
`nate the effect of output offset of amplifier 48. An amplifier
`52 is matched to amplifier 48, so that the DC output voltage
`of amplifier 52 is equal to that of amplifier 48. This is used
`as a DC compensation circuit into the following stage. The
`analog signal from amplifier 48 is converted to digital logic
`levels by a comparator 54. The digital output from com—
`parator 54 is buffered to an output line 56 by a buffer
`amplifier 58. Bias circuitry shown at block 60 provides the
`proper biasing and voltage references to all circuit blocks.
`VD and VDG are digital supply voltages. C1 and C2 are
`trim controls for compensating process variations of well
`resistance. CG is a gain control. VSE is a supply selection
`control, which is high for 5 volt operation and low for 3 volt
`operation. To is a test output. VDDl is a bypassed supply pin
`to which a 10 uF capacitor is connected. Transistor 62 is a
`protection diode.
`Low power operation of the receiver circuitry has been
`achieved by starting with minimal circuit architecture to
`accomplish the design requirements of detector current
`amplification, noise rejection, adequate bandwidth, and low
`quiescent currents. The VSE control used to select supply
`voltage is unique, in the sense that ICs designed to operated
`in 3—5 V ranges typically have no supply select
`line.
`Deleting this control pin normally would be desirable,
`because the IC could have a smaller footprint and test time;
`thus price would be reduced. In this design, however, a
`select is required to keep biasing of circuits in the low power
`region when switching from 3 to 5 V operation. No on—chip
`circuits were added to automatically adjust for supply selec-
`tion, because these circuits would require current themselves
`and thereby increase the total chip power.
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`Another circuit compromise used to achieve low power
`was the sharing of reference voltage VR (see block 60). This
`voltage is used to set all circuit current levels in the bias
`block 60, and also is used to set a clamp level in the clamp
`block 46. This sharing of a single reference voltage reduces
`the IC current that would be required if two reference
`voltages were separately generated, at the expense of the
`possibility of noise from the clamp circuit 46 corrupting bias
`currents via parasitic feedback of switching transients when
`clamping the input. Parasitic feedback of transients to the
`input of amplifier 40 is of great concern in this high gain
`amplifier design, and has been avoided only by careful
`circuit design and physical layout.
`Further power-saving design considerations have been
`made throughout the design, the details of which will be
`included in the block descriptions below. The transistors in
`the amplifiers were biased with currents just large enough to
`have low noise, and high enough gain to meet circuit
`operation requirements. Special unusual circuit configura-
`tions have been used to eliminate bias voltage generators
`and excessive quiescent currents.
`Another unique and significant feature of this circuit is the
`clamp Circuit 46 around the input amplifier 40. The receiver
`circuitry operates in a half-duplex mode,
`in which the
`received signal can be as low as 300nA, followed by the
`signals in the 3mA range from its own transmitter cross talk
`when duplexing. The input circuit must recover from large
`input transients such as these in typical operation, in order
`to maintain efficient effective data rates. One approach to
`handling large dynamic range DC operation, which has not
`been used in this application, would have been Automatic
`Gain Control (AGC) in the input stage. AGC circuits typi—
`cally have recovery times in the 10 ms range after detecting
`large signals. This would result in the requirement of waiting
`10 ms after transmitting, before a low level signal could be
`detected, thereby reducing the available transmit duty cycle
`and effective data rate. The diiferent approach taken has
`been use of a clamping circuit that has a fast recovery time,
`whose details are described below.
`
`FIG. 3 is a schematic showing the details of amplifier 40,
`a transimpedance amplifier used to convert the detector
`current input to a voltage output at 44, as shown in the
`diagram. There are several design parameters that relate to
`this amplifier:
`in order to
`1. Input impedance is below 20 kOhrns,
`maintain a signal bandwidth of 116 kHz, with a 70pF
`detector capacitance.
`2. A wide pulse current dynamic range extends from 100
`nA to 80 mA, and the quiescent current range extends
`from 0 to 30 uA.
`3. Low input referred noise current of 4 HA is required to
`meet the bit error rate requirements.
`Following the schematic diagram, the amplifier circuit
`operation is described. Mosfet transistor 80 and the series
`combination of resistors 82, 84, 86 and 88 form a common
`gate amplifier. Control inputs 90 and 92 control mosfet
`switches 89, 91, 93 and 95, which are used to trim the series
`combination of resistors, in order to compensate for process
`variations. VBP comes from a reference current mirror and
`biases a mosfet transistor 96 as a 263 nA quiescent current
`source into the mosfet transistor 80. Without this source, the
`input transistor 80 would have to meet all design require-
`ments with currents as low as 100 nA. The channel thermal
`
`noise at 100 nA would not meet the design requirements.
`The transconductance of transistor 80 is also too low to meet
`the desired 20 kOhm input impedance at low quiescent
`currents.
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`Feedback from the source to the gate of transistor 80 is
`used to reduce the input impedance at low quiescent current
`operating conditions. The feedback amplifier combines an
`input transistor 100 and a load consisting of the series
`combination of transistors 102 and 104. The combination of
`
`transistors 106, 108 and 110, and capacitor 90, form a
`current source to bias the feedback amplifier.
`The gate-to-source voltage (Vgs) values at the transistors
`80, 100, 102 and 104 need to be interrelated in such a way
`as to cause proper functioning of the transimpedance input
`amplifier 40. The amplifier, as stated above, converts pho-
`todetector current into an output voltage. The amplifier must
`present a low impedance to the detector, in order to increase
`the detector bandwidth, because the bandwidth decreases as
`the amplifier impedance increases, and vice versa.
`If the design of amplifier 40 were conventional, transis—
`tors 100, 102, 104, 106, 108 and 110 would form ahigh gain
`amplifier, having a relatively narrow bandwidth. Because
`the wireless IR system requires a bandwidth of about 200
`KHz, the input amplifier impedance must be reduced to
`about 16 Kohms, or less.
`The present invention provides means for enhancing the
`bandwidth, without sacrificing the low power goals, and
`with a minimum number of additional transistors. The gain
`of the amplifier is a controlled value of approximately 10, in
`order to meet the low input impedance of 16 Kohms, without
`using high current or power.
`Reverse bias of detector 28 is achieved with transistors
`102 and 104, and transistors 80 and 100 ratios. Also, as
`stated above, transistor 96 provides a bias current source,
`which keeps transistor 80 turned on more than normal, at
`very low detector currents, thereby achieving the desired
`bandwidth. In other words, the detector is not required to
`supply all the current.
`The loop gain of the amplifier has been made independent
`of signal level by the addition of transistors 102 and 104, and
`by setting the transistor ratios so that, at low input currents,
`Vgs of transistor 104 plus Vgs of transistor 102 equals Vgs
`of transistor 80 plus Vgs of transistor 100.
`The width-to-length ratios of the transistors in FIG. 3 are
`as follows: transistor 80 is 74.4/l.2 microns, transistor 96 is
`102/10.2 microns; transistor 100 is 30.0/l.8 microns; tran-
`sistor 102 is 108/1.8 microns; transistor 104 is l98.0/1.2
`microns; transistor 106 is 49.2/ 10.2 microns; transistor 108
`is 12.6/10.2 microns; and transistor 110 is 102/10.2
`microns.
`
`Because of the emphasis on low current and thus low
`power, all current values are set forth, by referring to arrows
`shown in the drawing; at arrow 120, 266 nA; at arrow 122,
`263.5 nA; at arrow 124, 558 nA; at arrow 126, 623 nA; at
`arrow 128, 64.9 nA; at arrow 130, 65 nA; and at arrow 132,
`276.5 nA. The total current in amplifier 40 is approximately
`1.1 pk, a very low value.
`The transistors 89, 91, 93 and 95 operate as switches,
`controlled by inputs 90 and 92. These inputs are 5 to 0 volts,
`or 3 to 0 volts. The transistor switches are set in manufac-
`turing; they select which of the resistors 82, 84, 86 and 88
`are inserted in the path between the output and ground
`(VSS). These transistors dissipate no power because the
`voltage across them is near or at zero.
`The input amplifier 40 is designed to meet the design
`requirements at detector currents up to about 30 uA. Above
`this level, noise performance and linear operation is not
`critical because the signal
`level
`is large. The values of
`resistors 82, 84, 86 and 88 have been selected to give a linear
`operating range of about 30 uA without degrading the noise
`performance of the circuit.
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`Simplifying the amplification in the gate—to—source path of
`transistor 80 is a primary source of power savings in this
`circuitry. Usually full operational amplifiers with many
`more transistors, and bias paths with voltage reference
`generators, are used for this function. Even with the sim-
`plified amplification, the quiescent current in transistor 106
`must be carefully designed to provide the desired bandwidth
`with low noise. The current in transistor 96, which sets the
`minimum quiescent current in transistor 80, was made as
`low as possible while maintaining stable operation, thus
`preventing circuit oscillations. The load resistance was made
`as large as possible without degrading noise performance,
`thereby reducing the requirement for greater signal gain in
`the subsequent stages. Transistors 80, 100, 102,104, 106 and
`108 are operating in the sub-threshold region, thereby con-
`tributing to low power operation of the receiver.
`Another feature of amplifier 40 is that, at low detector
`current, the gain of the amplifier is at its peak value; but
`when the detector current increases, the ratio of currents
`through transistors 100 and 102 tends to decrease the
`amplifier gain, accompanied by decreasing input impedance.
`The net result is that the bandwidth tends to stay essentially
`constant, independently of input current. This has two ben-
`efits. First, the noise bandwidth of the input is constant,
`providing better signal—to-noise performance. Second, the
`amplifier is in a feedback loop around transistor 80, which
`is stable with constant loop gain.
`FIG. 4 shows schematically the details of the clamp
`circuit 46, which‘essentially prevents saturation. At large AC
`signal levels amplifier 40 would saturate, requiring long
`recovery times, which would severely degrade signal band-
`width performance. Clamp circuit 46 is arranged to sense the
`signal level at the output 44 of amplifier 40, and to divert
`excess current from the detector input to VSS if the output
`at 44 is above a certain predetermined value, in this case
`about 1 Volt. Therefore the input amplifier 40 stays in a
`linear operating region, and signal bandwidth is maintained.
`In the clamp circuit 46, transistors 150, 152, 154, 156 and
`158 form a differential amplifier input stage. A positive input
`line 160 is connected to the gate of transistor 150; and a
`negative input line 162 is connected to the gate of transistor
`152. A reference voltage of about 1 volt is maintained on line
`160, and at transistor 150. The output of amplifier 40 is
`connected to line 162 and to transistor 152. The voltage level
`at transistor 150 is selected to avoid amplifier saturation.
`The output stage of the clamp circuit has an open drain
`transistor 164, and a compensation capacitor 166. A resistor
`168 is a current limiting resistor in series with open drain
`transistor 164.
`
`When the output from amplifier 40 on line 162 is less than
`the reference voltage on line 160, node 170 is low, and
`transistor 164 is off. In this condition, the clamp circuit does
`not drain any current from the detector input signal. When
`the voltage level at transistor 152 equals the reference level
`at transistor 150, drain transistor 164 turns on,
`thereby
`maintaining the level of current going into amplifier 40. This
`selected current level is about 30 uA, which will avoid
`saturation of amplifier 40. The clamp circuit 46 is operating
`in a linear region around amplifier 40, and compensation is
`provided by capacitor 166,
`in order to maintain circuit
`stability.
`By avoiding saturation of the amplifier, turn around time
`in the system is eliminated. Avoiding saturation is particu—
`larly important at amplifier 40. It
`is also important at
`subsequent components of the receiver, e.e., amplifier 48,
`and comparator 54.
`When currents from the detector are higher than about 3
`mA, the clamp circuit can no longer drain current from the
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`9
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`10
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`5,508,836
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`detector, and the detector becomes its own clamp diode
`when it forward biases itself. The clamp circuit will still
`cause the circuitry to recover from these over loads, because
`it actively drains current from the detector, unlike RC
`passive circuits.
`The power consumed by the clamp circuit has been
`minimized by careful circuit design with respect to amplifier
`gain and bandwidth. When the clamp circuit starts to acti-
`vate, it is part of the feedback circuit around the amplifier,
`and therefore gain stability is an important design consid-
`eration. Excess gain and bandwidth would make the design
`very stable at the expense of more current. The input stage
`to the clamp circuit operates in the subthreshold region, with
`just enough transconductance to drive the compensation
`capacitor 166 and transistor 164. The whole clamp circuit
`consumes about 269 nA, or 1.35 pW, when the clamp is not
`activated.
`The width-to-length ratios of the clamp circuit transistors
`are: transistors 150 and 152, each 50.4/6.0 microns; transis—
`tors 154 and 156, each 50.4/10.2 microns; transistor 158,
`10.2/10.2 microns; and transistor 164, l99.2/1.2 microns.
`The approximate current levels at “idling” are as follows:
`at each of arrows 176, 178 and 180, the current is 269 nA;
`at arrow 182, O; at arrow 184, 29 pA; and at arrow 186, 0.4
`pA.
`In clamp circuit 46, excess current is drained at the input
`of amplifier 40. The signal could be limited at the output of
`the amplifier, but the arrangement shown is considered
`preferable. The fact that pulsed signals are being transmitted
`makes the clamping more effective. The clamping effect acts
`instantaneously on each individual pulse. In other words, the
`clamping circuit monitors the signal continuously, and
`makes an instantaneous decision whether to divert excess
`current.
`
`The clamping circuit 46, and the clamps applied to
`amplifier 48 and comparator 54, constitute means for avoid-
`ing saturation. They control the absolute signal levels in
`order to guarantee that the amplifiers do not saturate. This
`can be accomplished either at the inputs of the amplifiers or
`at the outputs of the amplifiers.
`If higher power levels were being used, clamping would
`be easier. In the present invention, clamping is more effec-
`tive because current is shunted before it reaches the ampli-
`fier. Above the selected value of 30 pA. the system goes into
`a non-linear range of operation.
`FIG. 5 shows schematically the details of amplifier 48,
`which receives as its input signal the output signal from
`amplifier 40 on line 44. The output from amplifier 40 must
`be filtered and amplified in order to be detected reliably.
`Amplifier 48 functions as a bandpass filter as well as an
`amplifier. The signal on line 44 is input to amplifier 49 at the
`IP pin into a high pass RC filter, comprising capacitor 200,
`and resistors 202,204,206, 208 and 210. Mosfet transistor
`switches 212,214, 216 and 218, which are controlled by C1
`and C2 inputs, are used to compensate the resistance for
`process variations. The input stage of the differential ampli-
`fier comprises mosfet transistors 220, 222, 224, 226 and 228.
`Transistor 230 is turned off during normal operation.
`The output