UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_______________
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`_______________
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`
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`MICROSOFT CORPORATION, MICROSOFT MOBILE INC., SAMSUNG
`ELECTRONICS AMERICA, INC. AND SAMSUNG ELECTRONICS CO. LTD.,
`Petitioners
`
`v.
`
`FASTVDO LLC,
`Patent Owner
`
`_______________
`
`Case IPR2016-01179
`Patent 5,850,482
`
`_______________
`
`
`
`DECLARATION OF KENNETH A. ZEGER, PH.D., IN SUPPORT OF
`PATENT OWNER’S RESPONSE TO PETITION
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`_______________
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`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`
`
`_______________
`
`
`
`MICROSOFT CORPORATION, MICROSOFT MOBILE INC., SAMSUNG
`ELECTRONICS AMERICA, INC. AND SAMSUNG ELECTRONICS CO. LTD.,
`Petitioners
`
`v.
`
`FASTVDO LLC,
`Patent Owner
`
`_______________
`
`Case IPR2016-01179
`Patent 5,850,482
`
`_______________
`
`
`
`DECLARATION OF KENNETH A. ZEGER, PH.D., IN SUPPORT OF
`PATENT OWNER’S RESPONSE TO PETITION
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`I.
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`INTRODUCTION
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`1. I, Dr. Kenneth A. Zeger, have been retained by Patent Owner FASTVDO
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`LLC (“FASTVDO” or “Patent Owner”) through Zunda LLC to provide my
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`opinions in support of their Response to the Petition for Inter Partes Review
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`of U.S. Patent No. 5,850,482 to Meany et al., issued on December 15, 1998
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`(“’482 Patent,” Ex. 1001) pursuant to the legal standards set forth below.
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`Zunda LLC is being compensated for my time at the rate of $790 per hour
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`for time spent on non-deposition tasks and for deposition time. I have no
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`interest in the outcome of this proceeding, and no part of my compensation
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`is contingent upon the outcome of this proceeding.
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`2. I have also been asked to provide my technical review, analysis, insights, and
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`opinions regarding the Declaration of Professor Robert L. Stevenson, Ph.D.
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`(“Stevenson Declaration,” Ex. 1005) on the patentability of claims 1-3, 5, 6,
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`12-14, 16, 17, and 28 of the ’482 Patent and Microsoft Corporation,
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`Microsoft Mobile Inc, Samsung Electronics America, Inc. and Samsung
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`Electronics Co. Ltd.’s (“Petitioners”) Petition that relies on the Stevenson
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`Declaration. I have also reviewed the deposition transcript of Dr. Stevenson
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`from March 9, 2017 (Ex. 2006).
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`3. In preparing this Declaration, I have also reviewed U.S. Patent No. 5,392,037
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`to Kato (“Kato,” Ex. 1002) and U.S. Patent No. 5,243,629 to Wei (“Wei,”
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`Ex. 1004), portions of the file history of the ‘482 patent (Ex. 1003), as well
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`as other documents referenced below in this Declaration.
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`4. The statements made herein are based on my own knowledge and opinions.
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`II. BACKGROUND AND QUALIFICATIONS
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`5. I have studied, taught, and practiced electrical and computer engineering for
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`more than thirty years.
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`6. I received a Bachelor’s degree in Electrical Engineering and Computer
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`Science from the Massachusetts Institute of Technology in 1984.
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`7. I received a Master of Science degree in Electrical Engineering and
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`Computer Science from the Massachusetts Institute of Technology in 1984.
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`8. I received a Master of Arts degree in Mathematics from the University of
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`California, Santa Barbara, CA in 1989.
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`9. I received a Ph.D. degree in Electrical and Computer Engineering from the
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`University of California, Santa Barbara, CA in 1990.
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`10. I am currently a Full Professor of Electrical and Computer Engineering at
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`the University of California, San Diego (UCSD). I have held this position
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`since 1998, having been promoted from Associated Professor after two years
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`at UCSD. I have been an active member of the UCSD Center for Wireless
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`Communications for 18 years. I teach courses full-time at UCSD in the
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`fields of Electrical and Computer Engineering, and specifically in subfields
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`including communications and information theory at the undergraduate and
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`graduate levels. Prior to my employment at UCSD, I taught and conducted
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`research as a faculty member at the University of Illinois, Urbana-
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`Champaign for four years, and at the University of Hawaii for two years.
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`11. My twenty-plus years of industry experience includes consulting work for
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`the United States Department of Defense as well as for private companies
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`such as Xerox, Nokia, MITRE, ADP, and Hewlett-Packard. The topics upon
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`which I provide consulting expertise include data communications for
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`wireless networks, digital communications, information theory, computer
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`software, and mathematical analyses.
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`12. I have authored approximately 73 peer-reviewed journal articles, the
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`majority of which are on the topic of communications, information theory,
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`or signal processing. I have also authored over 100 papers at various
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`conferences and symposia over the past twenty-plus years, such as the: IEEE
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`International Conference on Communications; IEEE Radio and Wireless
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`Symposium; Wireless Communications and Networking Conference; IEEE
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`Global Telecommunications Conference; International Symposium on
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`Network Coding; IEEE International Symposium on Information Theory;
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`UCSD Conference on Wireless Communications; International Symposium
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`on Information Theory and Its Applications; Conference on Advances in
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`Communications and Control Systems; IEEE Communication Theory
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`Workshop; Conference on Information Sciences and Systems; Allerton
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`Conference on Communications, Control, and Computing; Information
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`Theory and Its Applications Workshop; Asilomar Conference on Signals,
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`Systems, and Computers. Roughly half of those papers relate to data
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`compression. I also am co-inventor on a US patent disclosing a memory
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`saving technique for image compression.
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`13. I was elected a Fellow of the IEEE in 2000, an honor bestowed upon only a
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`small percentage of IEEE members. I was awarded the National Science
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`Foundation Presidential Young Investigator Award in 1991, which included
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`$500,000 in research funding. I received this award one year after receiving
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`my Ph.D.
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`14. I have served as an Associate Editor for the IEEE Transactions on
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`Information Theory and have been an elected member of the IEEE
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`Information Theory Board of Governors for three, three-year terms. I
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`organized and have been on the technical advisory committees of numerous
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`workshops and symposia in the areas of communications and information
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`theory. I regularly review submitted journal manuscripts, government
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`funding requests, conference proposals, student theses, and textbook
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`proposals. I also have given many lectures at conferences, universities, and
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`companies on topics in communications and information theory.
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`15. I have extensive experience in electronics hardware and computer software,
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`from academic studies, work experience, and supervising students. I
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`personally program computers on an almost daily basis and have fluency in
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`many different computer languages.
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`16. My curriculum vitae, attached to this declaration as Exhibit 2005 (“Zeger
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`CV”), lists my publication record in archival journals, international
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`conferences, and workshops.
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`III. LEGAL PRINCIPLES
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`17. I am not an attorney and therefore I offer no opinions on the law. I have
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`been advised of the following general principles of patent law to be
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`considered in formulating my opinions as to the issues of the validity of the
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`challenged claims.
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`18. Anticipation: I have been informed by counsel that for a claim to be invalid
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`as anticipated, the challenger in an inter partes review must show, by a
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`preponderance of the evidence, that all the elements of a claim are present in
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`a single previous device or method, or sufficiently described in a single
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`previous printed publication or patent. To anticipate the claim, the prior art
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`does not have to use the same words as the claim, but all the requirements of
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`the claim must have been disclosed expressly or inherently, so that looking
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`at that one reference, a person of ordinary skill in the art could make and use
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`the claimed invention. A requirement of a claim that is missing from a prior
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`art may be disclosed inherently if that missing requirement is necessarily
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`present in that prior art. All elements of the claim must also be disclosed in
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`the reference as they are arranged in the claim.
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`19. I have been informed by counsel that if a prior art reference discloses two or
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`more embodiments, none of which disclose all elements of a claim as
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`arranged in the claim, those embodiments cannot be combined for
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`anticipation purposes. Instead, the party asserting invalidity must present an
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`obviousness analysis to support the combination of the embodiments.
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`20. Obviousness: I have been informed by counsel that for a claim to be invalid
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`as obvious, it must be obvious to a person of ordinary skill in the field of
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`technology of the patent at the relevant time. The existence of every element
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`of the claimed invention in multiple prior art references or systems does not
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`necessarily prove obviousness. Most, if not all, inventions rely on building
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`blocks of prior art. Obviousness may be found in an inter partes review
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`proceeding only where there is a preponderance of evidence that the
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`differences between the subject matter sought to be patented and the prior art
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`are such that the subject matter as a whole would have been obvious at the
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`time the invention was made to a person having ordinary skill in the art to
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`which said subject matter pertains. Obviousness analysis involves
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`determining the scope and content of the prior art; ascertaining the
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`differences between the prior art and the claims at issue; and analyzing
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`secondary considerations of non-obviousness (as explained below).
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`21. I have been informed by counsel that in determining whether any of the
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`challenged claims are obvious, I should consider whether the prior art
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`discloses or suggests all the elements of the challenged claims. I understand
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`that I should also consider whether there was a reason that would have
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`prompted a person having ordinary skill in the art to combine the known
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`elements (whether those elements are disclosed in different prior art
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`references or in different embodiments in a single reference) in a way the
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`claimed invention does, taking into account such factors as (1) whether the
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`claimed invention was merely the predictable result of using prior art
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`elements according to their known function(s); (2) whether the claimed
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`invention provides an obvious solution to a known problem in the relevant
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`field; (3) whether the prior art teaches or suggests the desirability of
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`combining elements claimed in the invention; (4) whether the prior art
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`teaches away from combining elements in the claimed invention; (5)
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`whether it would have been obvious to try the combinations of elements,
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`such as when there is a design need or market pressure to solve a problem
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`and there are a finite number of identified, predictable solutions; and (6)
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`whether the change resulted more from design incentives or other market
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`forces. To render a claim obvious, the prior art must have provided a
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`reasonable expectation of success.
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`22. I have been informed by counsel that I should also consider any objective
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`evidence (sometimes called “secondary considerations”) that may have
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`existed at the time of the invention and afterwards that may shed light on the
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`obviousness of the claims, such as:
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`a. Whether the invention was commercially successful as a result of the
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`merits of the claimed invention (rather than the result of design needs
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`or market-pressure advertising or similar activities);
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`b. Whether the invention satisfied a long-felt need;
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`c. Whether others had tried and failed to make the invention;
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`d. Whether others invented the invention at roughly the same time;
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`e. Whether others copied the invention;
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`f. Whether there were changes or related technologies or market needs
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`contemporaneous with the invention;
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`g. Whether the invention achieved unexpected results;
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`h. Whether others in the field praised the invention;
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`i. Whether persons having ordinary skill in the art of the invention
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`expressed surprise or disbelief regarding the invention;
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`j. Whether others sought or obtained rights to the patent from the patent
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`holder; and
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`k. Whether the inventor proceeded contrary to accepted wisdom in the
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`field.
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`l. I have been informed by counsel that differences between the prior art
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`reference and a claimed invention, however slight, invoke the
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`question of obviousness, not anticipation. Thus, the question of
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`obviousness is invoked if a prior art reference, or a single embodiment
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`of a prior art reference, discloses part but not all of the claimed
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`invention, or if the prior art reference includes multiple, distinct
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`teachings or embodiments that separately fail to disclose the claimed
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`invention as arranged in the claims.
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`IV. LEVEL OF ORDINARY SKILL
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`23. Dr. Stevenson, Petitioner’s declarant, submitted a declaration stating that
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`the person of ordinary skill in the art (“POSITA”) of the patented technology
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`at the time of the invention of the ‘482 Patent, or April 17, 1996, would have
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`a bachelor’s degree in electrical engineering, computer engineering, or the
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`equivalent and 2-3 years of work experience with compression, encoding,
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`and decoding.
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`24. The Stevenson Declaration specifically states: “an undergraduate degree in
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`computer science, computer engineering, or electrical engineering, as well as
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`two years’ experience or a graduate degree with focus in the area of data
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`compression, encoding, and decoding.” Ex. 1005, ¶40.
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`25. I disagree with Dr. Stevenson’s definition of a POSITA in this case. I note
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`that under Dr. Stevenson’s definition, a person of ordinary skill in the art
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`would have experience with data compression and encoding, but would not
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`necessarily have any experience or training in the subjects of error
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`protection, including unequal error protection, error-resilient data
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`transmission, or the equivalent.
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`26. Based on my education and experience, as of April 1996, it was not
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`standard practice in engineering to use unequal error protection (“UEP”)
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`even when systems transmitted data of varying levels of importance. A
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`POSITA as of the time of the ‘482 patent would have understood the costs
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`and complexities that would have been incurred as a result of incorporating
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`UEP in a system. The actual design of a UEP application would have
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`generally required additional training and/or education, and would have been
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`performed by advanced inventors or Ph.D.-level researchers.
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`27. My opinion is that a POSITA would have an undergraduate degree in
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`computer science, computer engineering, or electrical engineering, or the
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`equivalent, as well as at least two to three years of work experience with
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`error protection and error-resilient data transmission, or the equivalent.
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`Equivalent knowledge and/or experience could have been acquired through
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`other means. For example, a POSITA could have an undergraduate degree
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`in a different field, but could have acquired the requisite knowledge in the
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`subject of error protection and error-resilient data transmission through work
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`experience.
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`V.
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`THE ‘482 PATENT
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`28. A digital transmission system typically provides the function of
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`communicating information (e.g., source bits) across a distance at a desired
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`rate through a given transmission channel. A transmission channel can be
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`noisy (i.e., subject to transmission errors), and therefore would have a
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`limited capacity, known as the channel capacity. In the field of information
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`theory, if the source entropy is below the channel capacity, all channel errors
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`can in principle be overcome, and the source bits can be received entirely
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`intact. To achieve this, channel encoding is applied to the source bits. This
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`means that the source bits are encoded into another corresponding set of bits
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`by an operation known as error control coding (e.g., block coding or
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`convolutional coding). This operation increases the overall number of bits
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`being transmitted by adding redundancy to the information. These channel
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`encoded bits are transmitted and subject to the noisy transmission channel
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`errors discussed previously. But despite the introduction of such errors in the
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`bits received from the transmission channel, the redundancy introduced at
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`the channel encoding stage can be utilized to accurately reproduce the source
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`bits despite the channel noise and signal degradation. In general, more
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`redundancy introduced in the channel encoding process confers greater
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`robustness and resistance to channel errors, but also comes at a cost.
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`29. The approach described above provides for equal error protection to the
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`source bits. However, not all transmission errors due to transmission channel
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`noise have the same effect on the receipt and correct decoding of the source
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`bits. Some errors may be unnoticeable or inconsequential, while other errors
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`may propagate and corrupt many source bits, or may result in the loss of
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`synchronization. One of the benefits of the ’482 invention is the provision of
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`greater error protection to bits more susceptible to consequential or
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`catastrophic errors, i.e. those bits including some information that represents
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`a property of the less or unprotected bits.
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`30. According to the prior art, encoded code words could generally be highly
`
`susceptible to channel errors. If certain portions of the code word were
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`corrupted, serious or catastrophic corruption could result. Error protection
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`can include the transmission of additional redundant bits enabling the
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`recipient to identify whether and how transmitted data differs from the
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`source bits. For example, additional redundant data may be transmitted in a
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`way that permits the original data to be reconstructed even if multiple errors
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`are introduced. Another approach for alerting the system to errors is to
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`append to the data cyclic redundancy check (“CRC”) bits, which represent
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`the result of a particular mathematical operation performed upon the data.
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`The recipient may perform the same mathematical operation upon the
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`incoming data, and if the result is different from the appended CRC bits, the
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`recipient can become aware of one or more errors in the data.
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`31. Adding error protection information increases bandwidth requirements in
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`the case of transmission over a noisy channel or storage capacity
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`requirements in the case of storage in a storage medium. Therefore, the ’482
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`invention contemplates the selective application of unequal error protection.
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`It does this by distinguishing between those portions of the code word or
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`data that are susceptible to errors and those portions that are resilient to
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`errors, and applying more error protection to the portions susceptible to
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`errors while applying less or no error protection to the portions resilient to
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`errors. For example, one portion (e.g., “first portion” or “prefix”) may
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`contain information about how to decode other portions (e.g., “second
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`portion” or “suffix”). In this case, it can be beneficial to apply greater error
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`protection to the first portion since an error in that portion would
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`compromise the receiver’s ability to accurately decode the contents of the
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`second portion. Thus, the invention prioritizes, and applies more protection
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`to, those portions of the data that are more sensitive to errors (i.e., those
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`areas that represent some property of the less protected, or unprotected, bits),
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`as shown in Fig. 1 of the ’482 Patent reproduced below.
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`
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`32. The ’482 Patent discloses and claims devices and methods for organizing
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`and encoding the data or code word and selectively applying error
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`protection. This is beneficial in several ways, including the ability to
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`minimize necessary transmission bandwidth or storage capacity.
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`Furthermore, by structuring the data or code words into vulnerable portions
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`and resilient portions, and then unequally protecting only those vulnerable
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`portions against errors, the ’482 Patent reduces the need for more
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`comprehensive error protection of all the data regardless of importance or
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`error resilience of the data. These portions receiving higher levels of error
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`protection contain information useful to decoding and/or decompressing the
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`information contained in the error-resilient portions.
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`VI. CLAIM CONSTRUCTION
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`33. I have been informed that the ‘482 patent is expired as of April 17, 2016. I
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`have also been informed that the claims of an expired patent are construed in
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`inter partes review according to a district court’s standard. I understand that
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`standard states that words of a claim are generally given their ordinary and
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`customary meaning as understood by a person of ordinary skill in the art. I
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`have reviewed the District Court’s claim construction order (Ex. 1014) and
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`the Patent Trial and Appeal Board’s Institution Decision (Paper 15) and have
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`applied the constructions set forth in those documents for the purpose of
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`rendering my opinions below. I note that the District Court’s construction of
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`“code word” differs slightly, and in my view, insignificantly, from the Patent
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`Trial and Appeal Board’s construction of “code word.” I take no position on
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`whether the constructions issued by the District Court and Patent Trial and
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`Appeal Board represent the ordinary and customary meaning as understood
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`by a POSITA as of the filing date of the ’482 patent.
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`34. I note that neither the Petitioners nor the District Court construed the term
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`“storage medium” as it appears in claims 5, 16, and 28. I have reviewed the
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`‘482 patent and believe that based on the contents of the patent, the term
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`“storage medium” should be interpreted as a physical storage device. This
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`term should not be construed to cover transmission channels or data links,
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`which generally do not store data.
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`35. The specification and drawings of the ‘482 patent support the proper
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`interpretation of a “storage medium” as a physical storage device. In FIG. 1
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`of the ‘482 patent, the storage medium 18 is arranged parallel to a
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`transmitter block 20 for transmitting via data links 22 and 24. Ex. 1001,
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`FIG. 1. The ‘482 specification explains that the storage medium 18 may be
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`a “magnetic disk storage which is error protected as shown in FIG. 6.” Ex.
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`1001, 17:15-19. Instead of storing the data in a storage medium 18, the ’482
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`patent discloses that “the compressed and encoded data can be efficiently
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`transmitted, such as via first and second data links.” Ex. 1001, 17:26-27. I
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`read this disclosure in the ‘482 patent to indicate that storing data in a
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`storage medium should be interpreted differently from transmitting data via
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`a data link. While I do not take the position that the preamble of claim 28 is
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`a limitation, I have used the preamble of claim 28 to inform my construction
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`of “storage medium.” Specifically, the preamble of claim 28 states a
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`“computer readable memory.” ‘482 patent, 22:23. A POSITA would not
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`characterize the transmission of data as a “computer readable memory,” and
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`would not characterize the transmission of data as a “storage medium.” The
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`‘482 patent claims also clearly distinguish between the concept of “storing”
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`data “in a first data block of a storage medium” and the concept of
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`“transmitting” data “via a first data link,” such as shown in the different
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`word choices used in claims 5 and 6. Ex. 1001, 18:57-59; 19:1-2.
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`VII. NON-OBVIOUSNESS OF THE CHALLENGED CLAIMS
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`36. The Stevenson Declaration includes unsupported assertions as to the
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`combinability of Kato’s embodiments. Ex. 1005, ¶¶ 80-88. But Dr.
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`Stevenson does not provide rationale to support the specific combinations of
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`embodiments except to state that the different embodiments allegedly
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`disclose specific claim elements (i.e., unequal error protection. Ex. 1005, ¶¶
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`83-84, 87-88). As I will explain below, I disagree with Dr. Stevenson’s
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`conclusion that the challenged claims are obvious over Kato alone, and Kato
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`in view of Wei (for claims 6 and 17).
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`Kato
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`37. The Stevenson Declaration argues that there was motivation for a POSITA
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`to combine completely distinct embodiments in Kato. Ex. 1005, ¶¶80-88. I
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`disagree. For example, the Stevenson Declaration purports to modify the
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`first embodiment of Kato with the fourth embodiment of Kato in order to
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`provide unequal protection against error propagation. But according to
`
`Kato, the first embodiment already contains this benefit. I view this
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`oversight by the Stevenson Declaration as an indication that Dr. Stevenson
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`was relying upon impermissible hindsight to support the combination of
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`embodiments. I will explain my opinions in greater detail below.
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`38. For at least the reasons discussed in this Declaration, it is my opinion that
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`the Stevenson Declaration does not establish that Kato renders obvious the
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`challenged claims.
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`39. Kato separately discloses four separate embodiments. Three of the
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`embodiments relied upon by Dr. Stevenson are introduced in Kato as a
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`“Description of the First Preferred Embodiment” (6:55-16:28), a
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`“Description of the Third Preferred Embodiment” (19:36-23:43), and a
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`“Description of the Fourth Preferred Embodiment” (23:44-33:12). Likewise,
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`Figures 1(a) and 1(b) of Kato relate to the first embodiment; Figures 4(a),
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`4(b), and 5 relate to the third embodiment; and Figures 6(a), 6(b), and 7
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`relate to the fourth embodiment.
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`40. The fourth embodiment describes an “encoding circuit 602” that “encodes
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`the input data Di into variable-length code words, which are sequentially
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`arranged in one or more data store regions within a transmission format.
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`Thus, the variable-length code words are converted into bitserial-format
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`data, which are outputted from the encoding circuit 602.” Kato, 24:24-30.
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`Then, after briefly describing the error correcting code (ECC) encoder 603’s
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`operation, which includes the addition of error correcting code “to the output
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`data from the encoding circuit 602” (Kato, 24:32-3), Kato resumes the
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`discussion of the encoding circuit 602: “The operation of the encoding
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`circuit 602 will now be described in more detail. As described previously,
`
`the encoding circuit 602 encodes the input data Di into the variable-length
`
`code word Ci, and locates the variable-length code word Ci in the data store
`
`region within the data transmission format.” Kato, 24:40-45. Kato then
`
`describes the arrangement of the data store region(s) with respect to the
`
`encoding circuit 602. Kato, 24:46-27:31.
`
`41. Specifically, Kato describes the RAM 617 as being “formed with one or
`
`more data store regions corresponding to the data store region or regions in
`
`the transmission format.” Kato, 25:31-34. The writing of the first portion Pi
`
`and second portion Ri into the RAM 617 is described at 25:45-26:4, and the
`
`conclusion of this process is described by Kato as “the arrangement of one
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`IPR2016-01179 Ex. 2004
`Page 20 of 35
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`
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`variable-length code word Ci into the data store region.” Kato, 26:5-7. The
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`arrangement of code words stored in the data store region(s) of RAM 617 by
`
`encoding circuit 602 is described by Kato as a “transmission format.” Kato,
`
`25:33-34; 23:54-57; 24:41-45; 24:46-48.
`
`42. To the extent Dr. Stevenson’s opinion is that Kato’s first and fourth
`
`embodiments should be combined, I disagree. Nothing in Kato suggests that
`
`the method of the first embodiment should be combined with the apparatus
`
`of the fourth embodiment. In fact, Kato specifically teaches that the data
`
`output from the first embodiment are code words that are inherently resilient
`
`to error propagation, while Kato’s fourth embodiment provides an alternate
`
`solution for preventing error propagation. As a result, Kato’s first
`
`embodiment has no need for unequal error protection because Kato’s first
`
`embodiment already “prevents error propagation, and … is advantageous
`
`from the standpoint of error-propagation suppressing characteristics.” Kato,
`
`16:4-7. Kato explains that the first embodiment decodes and recovers the
`
`correct original data Di “even when there is a certain error between the
`
`estimate Pi used in the equations (5)-(7) and the estimate used in the
`
`encoding.” Kato, 15:66-16:1.
`
`43. Thus, Kato discloses that the first embodiment “prevents error propagation,”
`
`but Dr. Stevenson is attempting to modify Kato’s first embodiment to add
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`IPR2016-01179 Ex. 2004
`Page 21 of 35
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`
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`unequal error protection, which is also intended to avoid error propagation.
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`Dr. Stevenson does not offer any engineering analysis to justify the increase
`
`costs in bandwidth or power that come with transmitting additional bits due
`
`to error protection (and unequal error protection). Kato, 16:4-5. Dr.
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`Stevenson also does not offer any analysis explaining the benefit that this
`
`modification would achieve, if any, over the natural error protection already
`
`taught in Kato’s first embodiment. He also does not explain what results he
`
`believes would result from this modification.
`
`44. I believe Dr. Stevenson fundamentally misinterprets Kato’s first
`
`embodiment. I understand he gave the following testimony at deposition:
`
`“The way I view Kato is – something called the first embodiment is this
`
`predictive coding technique they have. And then the other three things they
`
`add are enhancements to that addition of that first embodiment, the
`
`predictive coding section.” Ex. 2006, 50:19-51:2. But Dr. Stevenson’s view
`
`of the first embodiment fails to take into account Kato’s full disclosure. In
`
`particular, Kato believes that the predictive coding technique of the first
`
`embodiment includes characteristics of error protection to avoid error
`
`propagation, and I agree with Kato’s characterization of the first
`
`embodiment in this regard. Kato, 15:66-16:7. Dr. Stevenson’s analysis
`
`assumes that the incorporation of the ECC encoder 603 from Kato’s fourth
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`IPR2016-01179 Ex. 2004
`Page 22 of 35
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`
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`embodiment will improve the risk of error propagation in Kato’s first
`
`embodiment. This analysis ignores what Kato explains about the error
`
`resiliency of the first embodiment. A POSITA would not overlook these
`
`disclosures, and would not incur the cost of adding unequal error protection
`
`to Kato’s first embodiment to avoid error propagation where Kato’s first
`
`embodiment already possesses this ability.
`
`45. In conclusion, a person of ordinary skill would not be motivated to combine
`
`Kato’s first embodiment with the fourth embodiment, or vice versa. Since
`
`the code words in the first embodiment are inherently resilient to error
`
`propagation, there is no reason that a POSITA would have combined the
`
`first embodiment with the fourth embodiment, which is also directed to
`
`preventing error propagation. There would be no benefit for this
`
`modification.
`
`46. Additionally, Dr. Stevenson has not explained or remedied the
`
`incompatibilities that would result from his proposed combination of
`
`embodiments. For example, Kato’s first embodiment sub-encodes category
`
`index Ji and remainder data Ei using sub encoding circuits 109 and 110, and
`
`then combines the coded data into the multiplexed coded data Ci using
`
`multiplexing circuit 111. Kato, Fig. 1(a); 10:44-46; 11:1-2; 11:5-9. From
`
`the multiplexing circuit 111, the output data is transmitted via output
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`IPR2016-01179 Ex. 2004
`Page 23 of 35
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`
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`terminal 108. Kato, 11:9-11. Unlike the first embodiment, the data stored in
`
`RAM 617 and then passed to ECC encoder 603 in the fourth embodiment
`
`does not require multiplexing. This is because the fourth embodiment stores
`
`the first and second portions in the RAM 617 in a “transmission format.”
`
`Kato, 25:31-34. The output from the ECC encoder 603 is sent to modulator
`
`604, and then to an output terminal 605. Kato, 23:57-63. Dr. Stevenson has
`
`not explained how the ECC encoder 603 would be incorporated into the first
`
`embodiment, where it would be located, and how it would interact with the
`
`sub encoding circuits 109 and 110, multiplexing circuit 111, and output
`
`terminal 108.
`
`47. Further, I understand from Dr. Stevenson’s deposition testimony that he has
`
`suggested the disclosure in Kato of
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