Filed on behalf of TQ Delta, LLC
`By: Peter J. McAndrews
`Thomas J. Wimbiscus
`Scott P. McBride
`Christopher M. Scharff
`McAndrews, Held & Malloy, Ltd.
`500 W. Madison St., 34th Floor
`Chicago, IL 60661
`Tel: 312-775-8000
`Fax: 312-775-8100
`E-mail: pmcandrews@mcandrews-ip.com
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`
`
`ARRIS GROUP, INC.,
`Petitioner,
`v.
`
`TQ DELTA, LLC,
`Patent Owner.
`_____________
`
`Case IPR2016-01160
`Patent No. 8,611,404
`_____________
`
`PATENT OWNER’S RESPONSE
`
`
`
`
`
`
`
`
`
`

`

`Patent Owner’s Response
`IPR2016-01160
`
`
`I. 
`
`II. 
`
`TABLE OF CONTENTS
`
`
`
`INTRODUCTION ........................................................................................... 1 
`
`OVERVIEW OF U.S. PATENT No. 8,611,404 ............................................. 5 
`
`A.  Background of the Technology .............................................................. 5 
`
`B.  The 404 Patent ........................................................................................ 8 
`
`III.  Overview of the cited references ................................................................... 10 
`
`A.  Bowie .................................................................................................... 10 
`
`B.  Vanzieleghem ....................................................................................... 14 
`
`C.  The 1995 ADSL Standard .................................................................... 15 
`
`IV.  LEVEL OF ORDINARY SKILL IN THE ART ........................................... 18 
`
`V. 
`
`CLAIM CONSTRUCTION .......................................................................... 19 
`
`A. 
`
`“Synchronization Signal” ..................................................................... 19 
`
`1. 
`
`2. 
`
`Petitioner’s Proposed Construction Is Incorrect ....................... 19 
`
`Patent Owner’s Proposed Construction Is The Broadest
`Reasonable Interpretation ......................................................... 23 
`
`B. 
`
`“Parameter Associated with the Full Power Mode Operation” ............ 24 
`
`C.  Other Limitations .................................................................................. 25 
`
`VI.  PETITIONER HAS FAILED TO SHOW THAT THE CLAIMS OF
`THE 404 PATENT ARE UNPATENTABLE OVER THE CITED
`ART 26 
`
`A.  Petitioner Did Not Perform a Proper Obviousness Analysis ............... 26 
`
`B. 
`
`Petitioner Has Failed To Establish That Bowie Discloses Storing
`In A Low Power Mode A “Parameter Associated With the Full
`Power Mode Operation” ...................................................................... 28 
`
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`Patent Owner’s Response
`IPR2016-01160
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`
`
`C. 
`
`Petitioner Fails To Establish That “Storing, In the Low Power
`Mode . . . At Least One of a Fine Gain Parameter and a Bit
`Allocation Parameter” Would Have Been Obvious Over Bowie
`and the 1995 ADSL Standard .............................................................. 29 
`
`1. 
`
`2. 
`
`Bowie’s Loop Characteristics Are Not the Claimed Fine
`Gain and Bit Allocation Parameters ......................................... 31 
`
`Bowie’s Teachings Undermine Petitioner’s Reasons for
`Modifying It to Store Bit Allocation or Fine Gain
`Parameters in a Low Power Mode ............................................ 36 
`
`D.  Bowie and the 1995 ADSL Standard Do Not Disclose Exiting
`the Low Power Mode without Needing To Reinitialize the
`Transceiver .......................................................................................... 38 
`
`E.  Bowie Would Have Led A POSITA Away From the Inventions
`of the 404 Patent .................................................................................. 42 
`
`F. 
`
`Petitioner Failed To Establish That Vanzieleghem and the 1995
`ADSL Standard Disclose the Claimed “Synchronization
`Signals” ............................................................................................... 45 
`
`1. 
`
`2. 
`
`Overview of Petitioner’s Argument .......................................... 45 
`
`Petitioner’s Argument Does Not Establish That the Cited
`Art Teaches the Synchronization Signal Limitations ............... 46 
`
`G.  A POSITA Would Not Have Modified Bowie to Transmit or
`Receive, In the Low Power Mode, a Synchronization Signal ............ 49 
`
`1. 
`
`Petitioner Failed To Provide Any Explanation as To Why
`or How A POSITA Would Have Combined
`Vanzieleghem with the Bowie Device ...................................... 49 
`
`2.  Modifying Bowie to Send or Receive a Synchronization
`Signal in the Low Power Mode As Petitioner Proposes
`Would Render Bowie Inoperable For Its Intended Use ............ 51 
`
`a. 
`
`The Proposed Modification Would Greatly Reduce
`Bowie’s Power Savings .................................................. 51 
`
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`Patent Owner’s Response
`IPR2016-01160
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`
`
`b. 
`
`The Proposed Modification Would Render
`Bowie’s Low Power Mode Inoperable ........................... 55 
`
`H.  Petitioner’s Proposed Reasons for Combining the Cited
`References Conflict with the Teachings of Those References ........... 57 
`
`VII.  CONCLUSION .............................................................................................. 62 
`
`iii
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`Patent Owner’s Response
`IPR2016-01160
`
`TABLE OF EXHIBITS
`
`
`
`
`Exhibit 2001 Declaration of Douglas A. Chrissan, Ph.D. for Inter Partes Review
`No. IPR2016-01160
`
`Exhibit 2002 February 23, 2017 Deposition Transcript of Lance J. McNally
`(IPR2016-01160)
`
`IEEE 100 The Authoritative Dictionary of IEEE Standards Terms,
`Seventh Edition
`
`Exhibit 2004 Curriculum Vitae of Douglas A. Chrissan, Ph.D.
`
`
`Exhibit 2003
`
`
`
`
`
`iv
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`

`

`Patent Owner’s Response
`IPR2016-01160
`
`I.
`
`INTRODUCTION
`
`
`
`Patent Owner TQ Delta, LLC (“Patent Owner”) submits this Response under
`
`37 CFR § 42.120 to the Petition filed by Arris Group, Inc. (“Petitioner”) requesting
`
`inter partes review of claims 1-20 of U.S. Pat. No. 8,611,404 (“the 404 patent”).
`
`The Board instituted inter partes review based on a single Ground—alleged
`
`obviousness in view of a combination of U.S. Patent No. 5,956,323 (“Bowie”),
`
`U.S. Patent No. 6,247,725 (“Vanzieleghem”), and the American National
`
`Standards Institute (ANSI) T1.413-1995 Standard, entitled “Network and
`
`Customer Installation Interfaces—Asymmetric Digital Subscriber Line (ADSL)
`
`Metallic Interface” (the “1995 ADSL Standard”).
`
`For purposes of institution, the Board accepted as true several unsupported
`
`factual statements by Petitioner and its expert that are incorrect and contradicted by
`
`the asserted references themselves. The Board did not have the benefit of a
`
`complete record with respect to how a person of ordinary skill in the art
`
`(“POSITA”) would have understood the teachings of the cited references.
`
`Therefore, Patent Owner provides additional details and technical explanations
`
`from its own qualified expert (Dr. Douglas Chrissan), along with further legal
`
`support, that show that a POSITA would not have found the claims of the 404
`
`patent obvious in view of Bowie, Vanzieleghem, and the 1995 ADSL Standard.
`
`
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`1
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`Patent Owner’s Response
`IPR2016-01160
`
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`First, Petitioner has not established that Bowie teaches or suggests the
`
`limitation of storing, in the low power mode, at least one parameter associated with
`
`full power mode operation. Bowie discloses storing only “loop characteristics,”
`
`which are not associated with the “full power mode operation.” Indeed, loop
`
`characteristics, as disclosed in Bowie, are not associated with any power mode or
`
`operation.
`
`Second, Petitioner has not established that the combination of Bowie and the
`
`1995 ADSL Standard renders obvious “stor[ing], in the low power mode . . . at
`
`least one of a fine gain parameter and a bit allocation parameter,” which is recited
`
`by all of the claims. The Board relied on Petitioner’s mischaracterizations of the
`
`prior art – i.e., that a POSITA would have stored the 1995 ADSL Standard’s bit
`
`allocation and fine gain parameters “as Bowie’s loop characteristics” – in finding a
`
`basis for institution. Also, Bowie’s teachings, properly understood by a POSITA,
`
`undermine Petitioner’s proffered reasons for modifying Bowie to store bit
`
`allocation or fine gain parameters in a low power mode.
`
`Third, Petitioner has not established that the combination of Bowie and the
`
`1995 ADSL Standard renders obvious the limitation of “exit[ing] from the low
`
`power mode and restor[ing] the full power mode by using the at least one
`
`parameter and without needing to reinitialize the transceiver,” which is also recited
`
`by all of the claims. Bowie teaches that some reinitialization is required, so
`
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`2
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`Patent Owner’s Response
`IPR2016-01160
`
`
`combining the 1995 ADSL Standard with Bowie as Petitioner proposes would
`
`result in a device that still must re-initialize upon coming out of low power mode.
`
`Fourth, Bowie teaches a device that operates in a fundamentally different
`
`way than the claimed inventions of the 404 patent, and thus, would have led a
`
`POSITA on a path divergent from that taken by the inventors of the 404 patent.
`
`Bowie discloses a transceiver that performs re-initialization upon coming out of
`
`low power mode for the sake of insuring reliable transmission parameters upon the
`
`resumption of data transmission. In contrast, the inventions of the 404 patent do
`
`not re-initialize upon coming out of low power mode for the sake of a speedy
`
`resumption of data transmission (but at the risk of using parameters that will result
`
`in errored transmissions).
`
`Fifth, Petitioner has not established that the cited references disclose or
`
`render obvious the limitation of “a synchronization signal,” which is recited by all
`
`of the claims. Petitioner argues that Vanzieleghem and the 1995 ADSL Standard
`
`disclose a synchronization signal by teaching “frame synchronization.” Petitioner,
`
`however, has not shown how the claimed “synchronization signal,” properly
`
`construed, reads on the “frame synchronization” disclosed in Vanzieleghem and
`
`the 1995 ADSL Standard. Additionally, Petitioner has not established that it
`
`would have been obvious to modify the Bowie device to transmit or receive a
`
`synchronization signal in the low power mode. In fact, modifying Bowie as
`
`
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`3
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`Patent Owner’s Response
`IPR2016-01160
`
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`Petitioner proposes would render Bowie inoperable for its intended purpose of
`
`reducing power consumption.
`
`Sixth, Petitioner’s general arguments for combining the references – e.g.,
`
`that Bowie and Vanzieleghem are “well-suited” for combination and would have
`
`been obvious to combine because they “conform” to the 1995 ADSL Standard –
`
`are insufficient and conflict with the teachings of those references. By way of
`
`example, Bowie does not conform to the 1995 ADSL Standard because the 1995
`
`ADSL Standard does not allow Bowie’s power conservation scheme.
`
`Petitioner cannot rely on the Board to fill in the gaps or defects in its Petition
`
`or to infer or read into the Petition arguments that Petitioner did not make. See In
`
`re Magnum Oil Tools Int'l, Ltd., 829 F.3d 1364, 1381 (Fed. Cir. 2016) (the Board
`
`is not “free to adopt arguments on behalf of petitioners that could have been, but
`
`were not, raised by the petitioner during an IPR”).
`
`Nor can Petitioner fix the deficiencies and failures of proof in the Petition at
`
`a later stage by offering new arguments or evidence in a Reply. See Intelligent
`
`Bio-Sys., Inc. v. Illumina Cambridge, Ltd., 821 F.3d 1359, 1369 (Fed. Cir. 2016)
`
`(“the expedited nature of IPRs bring with it an obligation for petitioners to make
`
`their case in their petition to institute”); Office Patent Trial Practice Guide, 77 Fed.
`
`Reg. 48,767 (Aug. 14, 2012) (a Petitioner may not “raise[] a new issue or belatedly
`
`present[] evidence” that could have been, but was not, raised in the Petition).
`
`
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`4
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`Patent Owner’s Response
`IPR2016-01160
`
`
`Petitioner’s single Ground for alleged obviousness fails. Patent Owner
`
`respectfully requests that the Board issue a Final Written Decision upholding the
`
`patentability of claims 1-20 of the 404 patent.
`
`II. OVERVIEW OF U.S. PATENT NO. 8,611,404
`The 404 patent, entitled “Multicarrier Transmission System with Low Power
`
`Sleep Mode and Rapid-On Capability,” issued on December 17, 2013, to Patent
`
`Owner TQ Delta, LLC. The inventions of the 404 patent represented a significant
`
`improvement in the field of multicarrier transmission systems and multicarrier
`
`transceivers. In particular, the 404 patent teaches a transceiver that saves energy
`
`by operating in a low power mode, but that can go rapidly from the low power
`
`mode back to a full power mode, without needing to reinitialize the transceiver,
`
`when it is needed to transmit or receive data. See Ex. 2001 at ¶ 15.
`
`A. Background of the Technology
`Multicarrier transmission systems provide high speed data links between
`
`communication points. See Ex. 1001 at 1:37-38; Ex. 2001 at ¶ 16. A digital
`
`subscriber loop (“DSL”) system is an exemplary multicarrier transmission system
`
`that is used to provide high-speed data communication over the same local
`
`subscriber loop that is used to provide telephone service to a subscriber. See Ex.
`
`1001 at 1:38-41; Ex. 2001 at ¶ 16. In a DSL system, the overall communication
`
`bandwidth of the communication channel between the subscriber and the central
`
`
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`5
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`Patent Owner’s Response
`IPR2016-01160
`
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`office is divided into a number of separate sub-channels or carriers, e.g., 256 sub-
`
`channels. See Ex. 1001 at 1:48-55; Ex. 2001 at ¶ 16. A transceiver divides data to
`
`be transmitted into groups of bits, allocates each group of bits to a sub-channel,
`
`and modulates each group of bits onto its respective sub-channel. See Ex. 1001 at
`
`1:63-66; Ex. 2001 at ¶ 16.
`
`Prior to exchanging data over the channel, the DSL transceivers first go
`
`through an initialization process. See Ex. 1001 at 3:7-9; Ex. 2001 at ¶ 17. The
`
`initialization process includes several distinct phases. The first phase involves
`
`synchronizing the timing references of the transceivers. The transceivers
`
`synchronize their timing by exchanging information to synchronize and “lock” the
`
`timing of their respective clocks. Ex. 2001 at ¶ 18. This is called “timing
`
`synchronization” or “clock synchronization.” Id.
`
`After timing synchronization, the initialization process goes into its next
`
`phase, during which the transceivers determine characteristics of the wire loop
`
`connecting the transceivers, i.e., loop characteristics. Ex. 2001 at ¶¶ 19, 61.
`
`Attenuation is an example of a loop characteristic. Id. at ¶ 19; Ex. 2002 at 23:19-
`
`24, 35:20-36:2. Attenuation is the reduction in signal power a signal experiences
`
`as it travels across the wire from the originating transceiver to the destination
`
`transceiver. Ex. 2001 at ¶ 19. Attenuation is a function of different physical
`
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`Patent Owner’s Response
`IPR2016-01160
`
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`characteristics of the wire loop, such as the length, diameter, and composition. Id.
`
`Loop background noise is another example of a loop characteristic. Id.
`
`Once the loop characteristics are determined, the initialization process
`
`continues with a sub-channel characterization and analysis phase. During this
`
`phase, the transceivers determine equalization settings and echo canceller settings
`
`and measure signal to noise ratios (“SNR”) on a sub-channel basis. Id. at ¶ 20.
`
`SNR is a function of loop characteristics such as line noise levels and attenuation.
`
`Id.
`
`In
`
`the
`
`last phase of
`
`initialization,
`
`the sub-channel characterization
`
`information, including SNR, is used to determine transmission parameters that are
`
`used for data transmission. See id.; Ex. 1001 at 3:10-20. Examples of
`
`transmission parameters include transmission and reception data rates, fine gain
`
`parameters, and bit allocation parameters. Transmission parameters are specific to
`
`and conform to the communication protocol used for data transmission. See Ex.
`
`2001 at ¶ 67. The transceivers then go through the step of exchanging the
`
`transmission parameters. Id. at ¶ 20.
`
`When initialization has finished, the transceivers can start exchanging data
`
`using the transmission parameters. Id. at ¶ 21. In the context of DSL, data is sent
`
`in superframes. A superframe includes 68 data frames or DMT symbols followed
`
`by a synchronization frame or sync symbol. See id. The transceivers count the
`
`
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`

`Patent Owner’s Response
`IPR2016-01160
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`received frames and may use their respective timing references to synchronize their
`
`respective frame counters. See Ex. 1001 at 5:51–52. A transceiver may use the
`
`received synchronization frame to identify, in part, the superframe boundaries and
`
`maintain superframe alignment or synchronization. Ex. 2001 at ¶ 21. This is
`
`known as “frame synchronization.”
`
` Id. at ¶ 51.
`
` Importantly,
`
`timing
`
`synchronization is not the same as frame synchronization.
`
`The 404 Patent
`
`B.
`The 404 Patent recognizes that prior art multicarrier transceivers were
`
`commonly maintained in the “on” state because of their complexity and because
`
`they had to remain ready to immediately transmit or receive data. See Ex. 1001 at
`
`2:55-58; Ex. 2001 at ¶ 22. In this “on” state, both the transmitter and receiver
`
`portion of a prior art transceiver remained fully functional at all times. As a result,
`
`the multicarrier transceivers wasted a significant amount of power and had short
`
`life spans. See Ex. 1001 at 2:58-63; Ex. 2001 at ¶ 22. Although low power modes
`
`(in which data communications are temporarily suspended) were known in the
`
`prior art, they were unsatisfactory because, after exiting the low power mode, the
`
`transceivers still had to go through the lengthy re-initialization process to
`
`determine parameters necessary for full data transmission. See Ex. 1001 at 3:23-
`
`30; Ex. 2001 at ¶ 22. The initialization process could take, for example, “tens of
`
`seconds.”
`
` This was unacceptable because users
`
`typically desired near-
`
`
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`

`Patent Owner’s Response
`IPR2016-01160
`
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`instantaneous response for data communications. See Ex. 1001 at 3:23-25; Ex.
`
`2001 at ¶¶ 21-22. This inability to rapidly return to full power mode meant that the
`
`prior multicarrier transceivers were always kept “on” even in the absence of data
`
`communications, resulting in high power consumption.
`
`The inventions of the 404 patent (e.g., Claims 1-20) provide a unique low
`
`power mode that improves the operation of multicarrier transceivers. The
`
`inventions allow the multicarrier transceiver to enter a low power mode (and thus
`
`save power) while maintaining a framework that enabled rapid return to full data
`
`communication capability. See Ex. 1001 at 3:31-33. The inventive framework for
`
`rapid-on capability includes maintaining synchronization between first and second
`
`transceivers by transmitting or receiving a synchronization signal while in the low
`
`power mode, reducing power consumption of at least one portion of a transmitter,
`
`and/or storing, while in the low power mode, parameters used for full power mode
`
`data transmission (such as fine gain or bit allocation parameters).
`
`Storing parameters associated with full-power mode and maintaining
`
`synchronization in the low power mode allows the claimed multicarrier transceiver
`
`to rapidly emerge from the low power mode and resume full data transmission
`
`immediately without the necessity of performing time-consuming steps to re-
`
`initialize the transceivers. Id. at 7:13-15, 8:4-13; Ex. 2001 at ¶ 23.
`
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`Patent Owner’s Response
`IPR2016-01160
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`Thus, the claims of the 404 patent address the deficiencies of prior art
`
`transceivers that implement a low power mode by eliminating the need for a
`
`constant “on” mode while still providing the desired near-instantaneous response.
`
`Ex. 1001 at 3:38–41. As discussed below, none of Bowie, Vanzieleghem, and the
`
`1995 ADSL Standard teaches or suggests the novel systems and methods of the
`
`404 patent, and, in fact, those references disclose systems that operate very
`
`differently.
`
`III. OVERVIEW OF THE CITED REFERENCES
`A. Bowie
`Bowie relates to a power conservation method for an asymmetric digital
`
`subscriber line (“ADSL”) system that transmits wide-bandwidth modulated data
`
`over a two-wire loop using high frequency carrier signals. Ex. 1005 at 1:4-8, 1:23-
`
`25; Ex. 2001 at ¶ 25. Bowie’s system differs significantly from the inventive
`
`system of the 404 patent because, among other things, it shuts down all the data
`
`receiving, data transmission, and signal processing circuitry in its disclosed low
`
`power mode, requires initialization after coming out of a low power mode, does
`
`not store bit allocation or fine gain parameters in a low power mode, and does not
`
`send or receive a synchronization signal in the lower power mode.
`
`As shown below, the Bowie system uses ADSL units (e.g., modems) that are
`
`connected by a wire loop 120. Each ADSL unit includes signal processing
`
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`Patent Owner’s Response
`IPR2016-01160
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`electronics 111, data transmit circuitry 112, data receive circuitry 113, and a
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`resume signal detector 115 (which can be “a 16kHz AC signal detector 115 that
`
`employs conventional frequency detection techniques”). See Ex. 1005 at 5:52-55;
`
`Ex. 2001 at ¶ 25.
`
`
`
`Bowie explains that, prior to data being sent between two ADSL units over
`
`the loop, loop characteristics, such as “loop loss,” (i.e., attenuation) must be
`
`determined and exchanged. See Ex. 1005 at 4:64-5:3. Bowie describes this
`
`exchange of loop characteristics as “handshaking.” See id. at 5:3-5; Ex. 2001 at ¶
`
`26.
`
`Bowie further teaches that when an ADSL unit receives a shut-down signal,
`
`it enters a low power mode in which the signal processing, data transmit, and data
`
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`Patent Owner’s Response
`IPR2016-01160
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`receive circuitry all shut down; only the resume signal detector remains
`
`operational. See Ex. 1005 at 5:17-28. In the low power mode, the loop in Bowie is
`
`“in an inactive state.” Id. at 5:28-29; Ex. 2001 at ¶ 27. As Bowie explains,
`
`shutting down the transmitting, receiving, and signal processing circuitry, i.e., most
`
`of the transceiver’s circuitry, saves a significant amount of power – up to five watts
`
`per loop. See Ex. 1005 at 2:1-6. Bowie further teaches that, upon entering the low
`
`power mode, the ADSL units may “store[] in memory 117 characteristics of the
`
`loop 220 that were determined by . . . handshaking.” Ex. 1005 at 5:17-28. Such
`
`loop characteristics would include things like attenuation, i.e., “loop loss.” Ex.
`
`2001 at ¶¶ 19, 28. Importantly, and unlike the inventions of the 404 patent, Bowie
`
`does not teach storing bit allocation or fine gain parameters in the low power
`
`mode. Id. at ¶ 28.
`
`Upon receipt of a “resume signal” at the resume signal detector 115, the
`
`Bowie unit “returns the signal processing 111, transmitting 112, and receiving 113
`
`circuitry to full power mode.” Id. at 5:60-62; Ex. 2001 at ¶ 29. The stored “loop
`
`transmission characteristics . . . are retrieved from memory 117 and used to enable
`
`data transmission to resume quickly by reducing the time needed to determine loop
`
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`Patent Owner’s Response
`IPR2016-01160
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`transmission characteristics.”1 Ex. 1005 at 5:62-66; Ex. 2001 at ¶ 29. In this way,
`
`Bowie teaches using the stored loop characteristics as a starting point for
`
`determining the transmission parameters that are necessary for returning to full
`
`data transmission after coming out of the low power mode. Ex. 2001 at ¶ 29; Ex.
`
`1005 at Fig. 3 (step 306), 6:26-42 (describing additional handshaking after coming
`
`out of low power mode).
`
`According to Bowie, the additional handshaking (i.e., reinitialization) that
`
`occurs before returning to full data transmission includes a re-determination of
`
`loop characteristics to account for changes in loop characteristics that occurred
`
`while the system was in the low power mode. See Ex. 2001 at ¶ 30; Ex. 1005 at
`
`5:66-6:1 (“After resumption of full power mode, additional handshaking between
`
`ADSL units 232 and 242 may occur.”); id. at 6:37-41 (“Handshaking information
`
`may be required [after coming out of low power mode] where . . . loop
`
`characteristics have changed due, for example, to temperature-dependent changes
`
`in
`
`loop resistance.”); Ex. 2002 at 56:7-58:5.
`
` Re-determining
`
`the
`
`loop
`
`
`1 Bowie uses the terms “loop characteristics,” “electronic characteristics of the
`
`particular wire loop,” “loop transmission characteristics,” and “loop characteristic
`
`parameters” interchangeably. Ex. 1005 at 5:1-3, 5:23-25, 5:62-66, 6:25-33; Ex.
`
`2001 at ¶ 26.
`
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`13
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`Patent Owner’s Response
`IPR2016-01160
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`characteristics after coming out of low power mode is required to ensure “reliable
`
`data communication between the units.” Ex. 1005 at 6:36-37; Ex. 2001 at ¶ 30.
`
`Accordingly, in contrast to the inventions of the 404 patent, Bowie teaches
`
`that re-initialization (i.e., re-determining the loop characteristics and exchanging
`
`handshaking information) must occur when the transceiver comes out of the low
`
`power mode. See Ex. 1005 at 5:62-6:2, 6:35-43; Ex. 2001 at ¶ 31.
`
`Bowie also differs from the inventions of the 404 patent in that it does not
`
`transmit or receive a synchronization signal when in the low power mode. Ex.
`
`2001 at ¶ 33. Indeed, Bowie cannot transmit or receive a synchronization signal
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`when in the low power mode because all of the transceiver circuitry except for the
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`resume signal detector is shut off in a low power mode in order to save power. Ex.
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`1005 at 5:25-28.
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`B. Vanzieleghem
`Vanzieleghem discloses a multicarrier transmission system that differs
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`significantly from both the inventions of the 404 patent and Bowie. Vanzieleghem
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`discloses an ADSL transmitter for a multicarrier system that can reduce power
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`dissipation during operation depending on the type of input data it is being asked to
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`transmit. Ex. 1006 at 4:46-50, 6:29-36; Ex. 2001 at ¶ 34. The input data may be
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`either effective data or idle data. See Ex. 1006 at 5:33-35; Ex. 2001 at ¶ 34. When
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`effective data is to be transmitted, the transmitter uses all of its carriers (e.g., 256
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`carriers) to send the data to a receiver. See Ex. 1006 at 5:66-6:15; Ex. 2001 at ¶
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`34. When the transmitter has only idle data to transmit, it reduces power
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`dissipation by transmitting on a reduced number of carriers. See Ex. 1006 at 6:30-
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`41; Ex. 2001 at ¶ 34. Vanzieleghem teaches maintaining frame synchronization
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`with a receiver by periodically sending a synchronization symbol as part of a
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`superframe. See Ex. 1006 at 6:59–61; 5:53–65; Ex. 2001 at ¶ 34.
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`Unlike the claimed transceivers of the 404 patent, Vanzieleghem does not
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`disclose storing, in a low power mode, any transmission parameters such as fine
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`gain or bit allocation parameters. Ex. 2001 at ¶ 35. Vanzieleghem also does not
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`disclose exiting a low power mode and restoring a full power by using stored
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`transmission parameters. Id. Further, Vanzieleghem does not teach restoring a full
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`power mode without re-initialization. Id.
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`Moreover, unlike Bowie – which teaches reducing power by completely
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`shutting down the transmitter, receiver, and signal processing circuitry –
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`Vanzieleghem teaches reducing power usage of only the transmitter. Id. Thus,
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`Bowie’s low power mode saves more power than Vanzieleghem’s. Id.
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`C. The 1995 ADSL Standard
`The 1995 ADSL Standard discloses electrical characteristics of ADSL
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`signals appearing at a network interface and the requirements for transmission
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`between a network and customer installation. Ex. 1009 at 1; Ex. 2001 at ¶ 36. In
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`its obviousness argument, Petitioner relies on the 1995 ADSL Standard, in part, for
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`teaching determining fine gains and bit allocations as part of the initialization
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`process. Pet. at 40. Importantly, the 1995 ADSL Standard teaches that, in the
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`context of ADSL transceiver initialization, bit allocation and fine gain parameters
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`are different than, and, in fact, are determined in part from, loop characteristics like
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`those disclosed in Bowie.
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`In that regard, the 1995 ADSL Standard explains that initialization includes
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`separate, sequential steps of determining loop characteristics and then determining
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`bit and gain parameters based on the loop characteristics and other information.
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`See Ex. 2001 at ¶ 37. For example, the 1995 ADSL Standard states “[o]ne part of
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`the ADSL initialization and training sequence estimates the loop characteristics to
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`determine whether the number of bytes per Discrete MultiTone (DMT) frame
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`required for the requested configuration's aggregate data rate [i.e., bit allocation]
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`can be transmitted across the given loop.” Ex. 1009 at 9. The 1995 ADSL
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`Standard also states that “each receiver communicates to its far-end transmitter the
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`number of bits and relative power levels [i.e., bit allocation and fine gain
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`parameters] to be used on each DMT sub-carrier, as well as any messages and final
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`data rates information. For highest performance these settings shall be based on
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`the results [e.g.,, loop characteristics] obtained through the transceiver training and
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`channel analysis procedures.” Ex. 1009 at 87 (emphasis added); Ex. 2002 at 30:2-
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`31:11, 40:7-44:22. In this way, the 1995 ADSL Standard clearly distinguishes
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`between collecting loop characteristics, on one hand, and determining and
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`exchanging bit allocation and fine gain parameters, on the other hand. See Ex.
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`2001 at ¶ 37.
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`Though the 1995 ADSL Standard describes the steps taken to initialize and
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`operate an ADSL transceiver, the described technology differs in important ways
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`from the inventions of the 404 patent. Specifically, the 1995 ADSL Standard does
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`not describe, anywhere, operating in a low power mode, going into a low power
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`mode, or coming out of a low power mode. Ex. 2001 at ¶ 38; Ex. 2002 at 50:14-
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`22, 65:18-20. The 1995 ADSL Standard, therefore, does not disclose storing bit
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`allocation or fine gain parameters in a low power mode or how to use those
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`parameters to avoid re-initialization when coming out of a low power mode. Ex.
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`2001 at ¶ 38.
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`Moreover, it is important to note that the 404 patent teaches avoiding the
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`initialization steps disclosed in the 1995 ADSL Standard when transitioning from a
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`low power mode to a full power mode. See Ex. 1001 at 10:16-18, Ex. 2001 at ¶ 23.
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`None of the 1995 ADSL Standard, Bowie, and Vanzieleghem – either alone or in
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`combination with the other references – teaches such capability. Bowie and
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`Vanzieleghem fail to teach avoiding the step of determining bit allocation and fine
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`gain parameters. Ex. 2001 at ¶¶ 31, 35. Furthermore, Bowie, despite disclosing
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`storing loop characteristics, specifically teaches that some determination of those
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`characteristics and “handshaking information” occurs upon coming out of the low
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`power mode. Ex. 2001 at ¶ 31; Ex. 1005 at 5:62-6:2, 6:35-43. Similarly,
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`Vanzieleghem does not teach avoiding the step of determining loop characteristics.
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`And, of course, because the 1995 ADSL Standard does not deal with a low power
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`mode, it does not teach avoiding any initialization steps upon coming out of such a
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`mode. Ex. 2001 at ¶ 38.
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`In addition, the Bowie device, when in low power mode, does not comply
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`with the 1995 ADSL Standard. The 1995 ADSL Standard teaches that the
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`“mandatory control (C) channel” in the ADSL system “shall always be active.”
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`Ex. 1009 at 13; Ex. 2001 at ¶ 38. Bowie, however, teaches that the loop is inactive
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`when the system is in low power mode. Ex. 1005 at 5:28-29; Ex. 2001 at ¶ 27. As
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`such, the 1995 ADSL Standard precludes the low power mode of the Bowie
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`device. Ex. 2001 at ¶ 104.
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`IV. LEVEL OF ORDINARY SKILL IN THE ART
`As of January 1998, and with respect to the 404 patent, a POSITA would
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`have had an electrical engineering background and experience in the design of
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`multicarrier communication systems, such as
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`those employing orthogonal
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`frequency division multip