Trials@uspto.gov
`571-272-7822
`
`
` Paper No. 7
`
`Entered: December 6, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2016-01135
`Patent 5,812,789
`____________
`
`
`
`Before MICHAEL R. ZECHER, JAMES B. ARPIN, and
`MATTHEW R. CLEMENTS, Administrative Patent Judges.
`
`ZECHER, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314 and 37 C.F.R. § 42.108
`
`
`
`
`
`
`
`571-272-7822
`
`
` Paper No. 7
`
`Entered: December 6, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2016-01135
`Patent 5,812,789
`____________
`
`
`
`Before MICHAEL R. ZECHER, JAMES B. ARPIN, and
`MATTHEW R. CLEMENTS, Administrative Patent Judges.
`
`ZECHER, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314 and 37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`IPR2016-01135
`Patent 5,812,789
`
`
`I. INTRODUCTION
`
`Petitioner, Apple Incorporated (“Apple”), filed a Petition requesting
`
`an inter partes review of claims 1–8 and 11–14 of U.S. Patent No. 5,812,789
`
`(Ex. 1001, “the ’789 patent”). Paper 2 (“Pet.”). Patent Owner, Parthenon
`
`Unified Memory Architecture Limited Liability Corporation (“Parthenon”),
`
`filed a Preliminary Response. Paper 6 (“Prelim. Resp.”).
`
`Under 35 U.S.C. § 314(a), an inter partes review may not be instituted
`
`unless the information presented in the Petition shows “there is a reasonable
`
`likelihood that the petitioner would prevail with respect to at least 1 of the
`
`claims challenged in the petition.” Taking into account Parthenon’s
`
`Preliminary Response, we conclude that the information presented in the
`
`Petition establishes that there is a reasonable likelihood that Apple would
`
`prevail in challenging claims 1–8 and 11–14 of the ’789 patent as
`
`unpatentable under 35 U.S.C. § 103(a). Pursuant to § 314, we hereby
`
`institute an inter partes review as to these claims of the ’789 patent.
`
`A. Related Matters
`
`
`
`The ’789 patent is involved in the following district court cases: (1)
`
`Parthenon Unified Memory Architecture LLC v. LG Elecs. MobileComm,
`
`USA, No. 2:15-cv-01950 (E.D. Tex.); (2) Parthenon Unified Memory
`
`Architecture LLC v. Huawei Techs. Co., No. 2:14-cv-00687-JRG-RSP (E.D.
`
`Tex.); (3) Parthenon Unified Memory Architecture LLC v. Motorola
`
`Mobility, Inc., No. 2:14-cv-00689-JRG-RSP (E.D. Tex.); (4) Parthenon
`
`Unified Memory Architecture LLC v. HTC Corp., No. 2:14-cv-00690-RSP
`
`(E.D. Tex.); (5) Parthenon Unified Memory Architecture LLC v. LG Elecs.,
`
`Inc., No. 2:14-cv-00691-JRG-RSP (E.D. Tex.); (6) Parthenon Unified
`
`2
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`IPR2016-01135
`Patent 5,812,789
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`Memory Architecture LLC v. Samsung Elecs. Co., No. 2:14-cv-00902-JRG-
`
`RSP (E.D. Tex.); (7) Parthenon Unified Memory Architecture LLC v.
`
`Qualcomm Inc., No. 2:14-cv-00930-JRG-RSP (E.D. Tex.); (8) Parthenon
`
`Unified Memory Architecture LLC v. ZTE Corp., No. 2:15-cv-00225-JRG-
`
`RSP (E.D. Tex.); (9) Parthenon Unified Memory Architecture LLC v. Apple,
`
`Inc., No. 2:15-cv-00621-JRG-RSP (E.D. Tex.); and
`
`(10) STMicroelectronics, Inc. v. Motorola Inc., No. 4:03-cv-00276-LED
`
`(E.D. Tex.). Pet. 2–3; Paper 5, 2.
`
`In addition to this Petition, Apple filed another petition challenging
`
`the patentability of claims 1, 3–6, 11, and 13 of the ’789 patent (Case
`
`IPR2016-00923). Pet. 3. In that case, we instituted an inter partes review as
`
`to claims 1, 3, 5, 11, and 13 of the ’789 patent as unpatentable under
`
`35 U.S.C. § 102(e), and claims 4 and 6 of the ’789 patent as unpatentable
`
`under 35 U.S.C. § 103(a). Apple Inc. v. Parthenon Unified Memory
`
`Architecture LLC, Case IPR2016-00923 (PTAB Aug. 23, 2016) (Paper 10)
`
`(Ex. 2002).1
`
`B. The ’789 Patent
`
`The ’789 patent, titled “Video and/or Audio Decompression and/or
`
`Compression Device That Shares a Memory Interface,” issued September
`
`
`
`1 The statutory deadline to issue a Final Written Decision in Case IPR2016-
`00923 is August 23, 2017. Claims 1, 3–6, 11, and 13, upon which we now
`institute review, are currently under review in that earlier proceeding. If we
`issue a Final Written Decision in that proceeding, it will be appropriate to
`determine whether Apple is estopped from maintaining this proceeding with
`respect those claims. See 35 U.S.C. § 315(e)(1). If we determine at that
`time that Apple is estopped with respect to claims 1, 3–6, 11, and 13,
`because claim 1 is the sole independent claim under review, we may
`
`3
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`IPR2016-01135
`Patent 5,812,789
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`22, 1998, from U.S. Patent Application No. 08/702,911, filed on August 26,
`
`1996. Ex. 1001, at [54], [45], [21], [86]. Because the application that led to
`
`the ’789 patent was filed August 26, 1996, the ’789 patent expired on
`
`August 26, 2016.
`
`The ’789 patent generally relates to an electronic system having a
`
`video or audio decompression/compression device and, in particular, to
`
`sharing a memory interface between such a device and another device in the
`
`electronic system. Ex. 1001, 1:18–23. In the Background section, the ’789
`
`patent discloses advantages associated with using encoders and decoders to
`
`compress and decompress video and audio sequences, respectively. See id.
`
`at 1:32–2:3. The ’789 patent then proceeds to disclose the architecture of a
`
`conventional encoder/decoder prior to asserting that there are a number of
`
`problems associated with such an architecture. See id. at 2:4–25, Figs. 1a,
`
`1b. According to the ’789 patent, one of the problems includes dedicating
`
`memory to both the encoder and decoder, thereby increasing the cost of
`
`adding these components to an electronic system. Id. at 2:29–37.
`
`The ’789 patent purportedly solves this problem because the disclosed
`
`video or audio decompression/compression device does not need its own
`
`dedicated memory, but instead may share memory with another device and
`
`still operate in real time. Ex. 1001, 4:30–34. Figure 2 of the ’789 patent,
`
`
`
`terminate this proceeding with respect to claims 2, 7, 8, 12, and 14 and, if
`appropriate, vacate this Decision on Institution. See 35 U.S.C. § 315(d)
`(“[I]f another proceeding or matter involving the patent is before the Office,
`the Director may determine the manner in which the inter partes review or
`other proceeding or matter may proceed, including providing for stay,
`transfer, consolidation, or termination of any such matter or proceeding.”).
`
`4
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`IPR2016-01135
`Patent 5,812,789
`
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`reproduced below, illustrates a diagram of an electronic system containing a
`
`device having a memory interface, as well as an encoder and decoder. Id. at
`
`5:1–3.
`
`
`
`
`
`As shown in Figure 2, electronic system 40 includes first device 42,
`
`decoder 44, encoder 46, memory interface 48, and memory 50. Ex. 1001,
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`5:23–26. Each of first device 42, decoder 44, and encoder 46 accesses
`
`memory 50 through memory interface 48. Id. at 5:15–19. Memory interface
`
`48 further includes arbiter 54 that is configured to arbitrate between first
`
`device 42, decoder 44, and encoder 46, when these components request
`
`access to memory 50. Id. at 6:15–18, 9:43–49
`
`C. Illustrative Claim
`
`
`
`Of the challenged claims, claim 1 is independent. Independent claim
`
`1 is directed to an electronic system coupled to a memory. Claims 2–8 and
`
`11–14 directly or indirectly depend from independent claim 1. Independent
`
`claim 1 is illustrative of the challenged claims and is reproduced below:
`
`An electronic system coupled to a memory,
`
`1.
`comprising:
`a first device that requires access to the memory;
`
`5
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`IPR2016-01135
`Patent 5,812,789
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`a decoder that requires access to the memory sufficient to
`maintain real time operation; and
`a memory interface for coupling to the memory, and
`coupled to the first device and to the decoder, the memory
`interface having an arbiter for selectively providing access for
`the first device and the decoder to the memory and a shared bus
`coupled to the memory the first device, and the decoder, the bus
`having a sufficient bandwidth to enable the decoder to access
`the memory and operate in real time when the first device
`simultaneously accesses the bus.
`
`Ex. 1001, 12:29–41.
`
`D. Prior Art Relied Upon
`
`Apple relies upon the following prior art references:
`
`Inventor2 U.S. Patent No.
`Bowes
`5,546,547
`
`Thomas
`
`5,001,625
`
`Ran
`
`Celi
`
`5,768,533
`
`5,742,797
`
`
`Printed Publication
`
`Relevant Dates
`issued Aug. 13, 1996,
`filed Jan. 28, 1994
`issued Mar. 19, 1991,
`filed Mar. 24, 1988
`issued June 16, 1998,
`filed Sept. 1, 1995
`issued Apr. 21, 1998,
`filed Aug. 11, 1995
`
`Exhibit No.
`1005
`
`1007
`
`1009
`
`1010
`
`Exhibit No.
`
`TMS320C8x System-Level Synopsis, Literature Ref. No.
`SPRU113B, Texas Instruments, Inc. (Sept. 1995) (“TMS”)
`Robert J. Gove, The MVP: A Highly-Integrated Video
`Compression Chip, IEEE (1994) (“Gove”)
`
`1006
`
`1008
`
`
`
`
`
`2 For clarity and ease of reference, we only list the first named inventor.
`
`6
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`E. Asserted Grounds of Unpatentability
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`
`
`Apple challenges claims 1–8 and 11–14 of the ’789 patent based on
`
`the asserted grounds of unpatentability (“grounds”) set forth in the table
`
`below. Pet. 10–11, 19–69.
`
`References
`
`Basis
`
`Challenged Claim(s)
`
`Bowes, TMS, and Thomas3
`
`§ 103(a)
`
`1–5 and 12–14
`
`Bowes, TMS, Thomas, and Gove
`
`§ 103(a)
`
`6 and 8
`
`Bowes, TMS, Thomas, and Ran
`
`§ 103(a)
`
`7
`
`Bowes, TMS, Thomas, and Celi
`
`§ 103(a)
`
`11
`
`II. ANALYSIS
`
`A. Claim Construction
`
`In an inter partes review, we generally construe claims by applying
`
`the broadest reasonable interpretation in light of the specification. 37 C.F.R.
`
`§ 42.100(b). As we explained above, however, the ’789 patent expired on
`
`August 26, 2016; both parties acknowledge as much. See Pet. 15
`
`(“Petitioner believes that the ’789 Patent would expire during the pendency
`
`of the requested inter partes review proceeding.”); Prelim. Resp. 3 (“The
`
`’789 Patent is likely to expire before the Board is likely to issue a final
`
`written decision as to the patentability of the challenged claims.”).
`
`In order to determine if Apple has demonstrated a reasonable
`
`likelihood that it would prevail in this proceeding, given the ’789 patent has
`
`expired and consistent with our claim constructions in Case IPR2016-00923,
`
`
`
`3 Thomas is not listed as an asserted prior art reference in Apple’s
`“Identification of Challenges” (Pet. 10), but is relied upon in its substantive
`analysis (id. at 19–54).
`
`7
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`we analyze Apple’s arguments through the lens of the claim construction
`
`standard that will apply to our Final Written Decision. Thus, we construe
`
`the claims in accordance with the principles followed in district court. See
`
`Phillips v. AWH Corp., 415 F.3d 1303, 1314 (Fed. Cir. 2005) (en banc).
`
`37 C.F.R. § 42.5(b); see Toyota Motor Corp. v. Cellport Sys., Inc., Case
`
`IPR2015-00633, slip op. at 8–10 (PTAB Aug. 14, 2015) (Paper 11); cf. In re
`
`Rambus Inc., 694 F.3d 42, 46 (Fed. Cir. 2012) (“While claims are generally
`
`given their broadest possible scope during prosecution, the Board’s review
`
`of the claims of an expired patent is similar to that of a district court’s
`
`review.” (citation omitted)). Apple argues that its proposed constructions
`
`will remain the same even if we apply the principles set forth in Phillips.
`
`See Pet. 15 (“[T]he constructions proposed herein are consistent with both
`
`[the Phillips standard and the broadest reasonable interpretation standard].”).
`
`“In determining the meaning of the disputed claim limitation, we look
`
`principally to the intrinsic evidence of record, examining the claim language
`
`itself, the written description, and the prosecution history, if in evidence.”
`
`DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 469 F.3d 1005, 1014
`
`(Fed. Cir. 2006) (citing Phillips, 415 F.3d at 1312–17). The words of a
`
`claim generally are given their ordinary and customary meaning, and that is
`
`the meaning the term would have to a person of ordinary skill in the art at
`
`the time of the invention, in the context of the entire patent, including the
`
`specification. See Phillips, 415 F.3d at 1312–13. Claims are not interpreted
`
`in a vacuum, but are a part of and are read in light of the specification. See
`
`Slimfold Mfg. Co. v. Kinkead Indus., Inc., 810 F.2d 1113, 1116 (Fed. Cir.
`
`1987). Although it is improper to read a limitation from the specification
`
`into the claims, the claims still must be read in view of the specification of
`
`8
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`which they are a part. See Microsoft Corp. v. Multi-Tech Sys., Inc., 357 F.3d
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`1340, 1347 (Fed. Cir. 2004). “[A]n inventor is indeed free to define the
`
`specific terms used to describe his or her invention, [but] this must be done
`
`with reasonable clarity, deliberateness, and precision.” In re Paulsen, 30
`
`F.3d 1475, 1480 (Fed. Cir. 1994).
`
`In its Petition, Apple proposes constructions for the following claim
`
`terms or phrases: (1) “decoder” (all challenged claims); (2) “encoder”
`
`(claims 5–7); (3) “real time” (all challenged claims); and (4) “variable
`
`bandwidth” (claim 2). Pet. 15–18. In response, Parthenon proposes
`
`alternative constructions for the following claim terms or phrases: (1)
`
`“decoder”; (2) “encoder”; and (3) “variable bandwidth.” Prelim. Resp. 4–6.
`
`For purposes of this Decision on Institution, we need only assess the parties’
`
`proposed constructions for the claim terms “decoder” and “encoder.”
`
`See, e.g., Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803
`
`(Fed. Cir. 1999) (explaining that only those claim terms or phrases that are
`
`in controversy need to be construed, and only to the extent necessary to
`
`resolve the controversy).
`
`1. “decoder” (all challenged claims)
`
`
`
`In its Petition, Apple proposes to construe the claim term “decoder” to
`
`mean “a video and/or audio decompression device.” Pet. 15 (emphasis
`
`omitted). According to Apple, the specification of the ’789 patent provides
`
`a special definition for this claim term. Id. (citing Ex. 1001, 1:48–51, 5:28–
`
`31). In further support of its argument, Apple directs us to the supporting
`
`testimony of its expert witness, Robert Colwell, Ph.D. Id. (citing Ex. 1003
`
`¶¶ 40–42).
`
`9
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`In its Preliminary Response, Parthenon contends that, to the extent we
`
`determine a construction of the claim term “decoder” is necessary for
`
`purposes of this Decision, we should construe this claim term consistent
`
`with our construction in the parallel proceedings. Prelim. Resp. 4. That is,
`
`Parthenon asserts that we should construe the claim term “decoder” to mean
`
`“hardware and/or software that translates data streams into video and audio
`
`information.” Id. (citing Ex. 2002, 8–9). In further support of its argument,
`
`Parthenon directs us to various disclosures in the specification of the ’789
`
`patent and a dictionary definition for “decoder.” Id. (citing Ex. 1001, 1:49–
`
`50; Ex. 2003, 56).
`
`
`
`As an initial matter, we do not agree with Apple that the specification
`
`of the ’789 patent sets forth a special definition for the claim term
`
`“decoder.” For convenience, the disclosures in the specification relied upon
`
`by Apple to support its argument include the following: (1) “[t]he resulting
`
`bitstream is decoded by a video and/or audio decompression device
`
`(hereinafter decoder) before the video and/or audio sequence is displayed”
`
`(Ex. 1001, 1:47–51 (emphasis added)); and (2) “[f]or ease of reference, a
`
`video and/or audio decompression and/or compression device 45 will
`
`hereinafter be referred to as a decoder/encoder 45” (id. at 5:28–31
`
`(emphases added)). In our view, these cited disclosures do not amount to
`
`clear, deliberate, and precise statements as to the meaning or significance of
`
`the claim term “decoder” in the context of the ’789 patent, but rather simply
`
`indicate that “a decoder” is the shorthand description for “a video and/or
`
`audio decompression device.”
`
`
`
`To the extent Apple asserts that the claim term “decoder” should be
`
`limited to just a device, i.e., hardware, we are not persuaded. See Pet. 15.
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`10
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`The specification of the ’789 patent discloses that “[t]he audio decoding can
`
`be performed . . . through software.” Ex. 1001, 5:43–45. The specification
`
`further discloses that:
`
`In the preferred embodiment of the invention, when the
`decoder/encoder 45 is in a system containing a processor and is
`coupled to the process, the audio decoding is performed in
`software. . . . If the audio decoding is performed in software, the
`processor should preferably operates at a speed to allow the audio
`decoding to performed in real time without starving other
`components of the system that may need to utilize the process.
`
`Id. at 5:45–54 (emphases added). These cited disclosures in the
`
`specification clearly contemplate that decoding is not limited to hardware,
`
`but also may be performed in software. Apple’s proposed construction does
`
`not take into account this aspect of decoding disclosed in the specification.
`
`In light of our analysis above, we are persuaded that Parthenon’s
`
`proposed construction of the claim term “decoder” as “hardware and/or
`
`software that translates data streams into video or audio information” is the
`
`ordinary and customary meaning of this claim term, as would be understood
`
`by one of ordinary skill in the art, in the context of the entire disclosure of
`
`the ’789 patent. See Phillips, 415 F.3d at 1312–13. Parthenon’s proposed
`
`construction is consistent with the following: (1) certain disclosures in the
`
`specification of the ’789 patent (see, e.g., Ex. 1001, 5:43–45 (disclosing that
`
`“audio decoding can be performed . . . through software”)); (2) at least one
`
`dictionary definition of “decoder” (Ex. 2003, 56 (defining a “decoder” as
`
`“any hardware or software system that translates data streams into video or
`
`audio information”)); and (3) our construction of the claim term “video
`
`decoder” recited in dependent claim 3 of the ’789 patent in Case IPR2016-
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`00923 (Ex. 2002, 8–9 (construing the claim phrase “video decoder” as
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`“hardware and/or software that translates data streams into video
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`information”)).
`
`2. “encoder” (claims 5–7)
`
`
`
`In its Petition, Apple proposes to construe the claim term “encoder” to
`
`mean “a video and/or audio compression device.” Pet. 16 (emphasis
`
`omitted). According to Apple, the specification of the ’789 patent provides
`
`a special definition for this claim term. Id. (citing Ex. 1001, 1:46–48, 5:28–
`
`31). In further support of its argument, Apple directs us to the supporting
`
`testimony of Dr. Colwell. Id. (citing Ex. 1003 ¶¶ 43–45).
`
`In its Preliminary Response, Parthenon contends that, to the extent we
`
`determine a construction of the claim term “encoder” is necessary for
`
`purposes of this Decision, we should construe this claim term consistent
`
`with the our construction in the parallel proceedings. Prelim. Resp. 4. That
`
`is, Parthenon asserts that we should construe the claim term “encoder” to
`
`mean “hardware and/or software that translates video and audio information
`
`into data streams.” Id. at 4–5 (citing Ex. 2002, 8–9). In further support of
`
`its argument, Parthenon directs us to various disclosure in the specification
`
`of the ’789 patent. Id. at 5 (citing Ex. 1001, 1:46–47).
`
`As an initial matter, we do not agree with Apple that the specification
`
`of the ’789 patent sets forth a special definition for the claim term
`
`“encoder.” For convenience, the disclosures in the specification relied upon
`
`by Apple to support its argument include the following: (1) “[v]ideo and/or
`
`audio compression devices (hereinafter encoders) are used to encode the
`
`video and/or audio sequence before it is transmitted or stored” (Ex. 1001,
`
`1:45–47 (emphasis added)); and (2) “[f]or ease of reference, a video and/or
`
`audio decompression and/or compression device 45 will hereinafter be
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`referred to as a decoder/encoder 45” (id. at 5:28–31 (emphases added)). In
`
`our view, these cited disclosures do not amount to clear, deliberate, and
`
`precise statements as to the meaning or significance of the claim term
`
`“encoder” in the context of the ’789 patent, but rather simply indicate that
`
`“an encoder” is the shorthand description for “a video and/or audio
`
`compression device.”
`
`
`
`To the extent Apple asserts that the claim term “encoder” should be
`
`limited to just a device, i.e., hardware, we are not persuaded. See Pet. 16.
`
`The specification of the ’789 patent discloses that “[t]he audio encoding can
`
`be performed . . . through software.” Ex. 1001, 5:61–63. The specification
`
`further discloses that, “[i]n the preferred embodiment of the invention, when
`
`the decoder/encoder 45 is in a system containing a processor and is coupled
`
`to the process, the audio encoding is performed in software presenting the
`
`same advantages of freeing up space on the die without causing significant
`
`delay in the encoding.” Id. at 5:63–6:1 (emphasis added). These cited
`
`disclosures in the specification clearly contemplate that encoding is not
`
`limited to hardware, but also may be performed in software. Apple’s
`
`proposed construction does not take into account this aspect of encoding
`
`disclosed in the specification.
`
`In light of our analysis above, we are persuaded that Parthenon’s
`
`proposed construction of the claim term “encoder” as “hardware and/or
`
`software that translates video and audio information into data streams” is the
`
`ordinary and customary meaning of this claim term, as would be understood
`
`by one of ordinary skill in the art, in the context of the entire disclosure of
`
`the ’789 patent. See Phillips, 415 F.3d at 1312–13.
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`13
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`B. Obviousness Over the Combination of Bowes, TMS, and Thomas
`
`
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`Apple contends that claims 1–5 and 12–14 of the ’789 patent are
`
`unpatentable under § 103(a) over the combination of Bowes, TMS, and
`
`Thomas. Pet. 19–54. Apple explains how this proffered combination
`
`purportedly teaches the subject matter of each challenged claim (id.), and
`
`relies upon the Declaration of Dr. Colwell. (Ex. 1003 ¶¶ 58–95) to support
`
`its positions. At this stage of the proceeding, we are persuaded by Apple’s
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`explanations and supporting evidence.
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`We begin our analysis with the principles of law that generally apply
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`to a ground based on obviousness, followed by a brief overview of Bowes,
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`TMS, and Thomas, and then we address the parties’ contentions with respect
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`to independent claim 1.
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`1. Principles of Law
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`A claim is unpatentable under § 103(a) if the differences between the
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`claimed subject matter and the prior art are such that the subject matter, as a
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`whole, would have been obvious at the time the invention was made to a
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`person having ordinary skill in the art to which said subject matter pertains.
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`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The question of
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`obviousness is resolved on the basis of underlying factual determinations,
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`including (1) the scope and content of the prior art; (2) any differences
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`between the claimed subject matter and the prior art; (3) the level of skill in
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`14
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`the art;4 and (4) when in evidence, so-called secondary considerations.
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`Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966). We analyze this
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`asserted ground based on obviousness with the principles identified above in
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`mind.
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`2. Bowes Overview
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`Bowes generally relates to a memory bus arbiter for a computer
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`system having a digital signal processor (“DSP”) or co-processor. Ex. 1005,
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`at [54]. According to Bowes:
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`In prior art computer systems, because of the high bandwidth
`required for real-time processing by a DSP, it has not been
`possible for the DSP to run off of the computer system’s
`[dynamic random access memory (“DRAM”)] in the way the
`[central processor unit (“CPU”)] 10 utilizes it without adversely
`affecting the rest of the computer system. Thus, there has been
`provided a large block of [static random access memory
`(“SRAM”)] 24 for use by the DSP 20. . . .
`
`A significant disadvantage to the prior art computer
`architecture of FIG. 1 is the requirement of a substantial block of
`static random access memory 24. SRAMs are significantly more
`expensive than DRAM which greatly increases the cost of
`computer systems which incorporate SRAM.
`
`Id. at 2:26–48. Thus, it is an objective of Bowes “to provide a . . .
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`method for arbitrating the memory bus bandwidth to efficiently allow
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`the use of a [DSP] and a CPU over a common memory bus sharing the
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`
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`4 Apple’s declarant, Dr. Colwell, testifies as to the level of skill in the art as
`of August 26, 1996—the earliest effective filing date of the ’789 patent. Ex.
`1003 ¶ 20. Parthenon does not challenge this assessment of the level of skill
`in the art or propose an alternative to this assessment. For purposes of this
`Decision on Institution, and to the extent necessary, we accept the
`assessment offered by Dr. Colwell.
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`15
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`system’s [DRAM] subsystem without requiring an expensive block
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`[SRAM].” Id. at 2:57–63.
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`Figure 2 of Bowes, reproduced below, illustrates a block diagram of a
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`computer architecture incorporating the arbitration scheme disclosed in
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`Bowes. Ex. 1005, 3:65–67, 5:11–13.
`
`
`
`As shown in Figure 2, “[this arbitration] scheme is implemented such that
`
`the DSP is provided with sufficient bandwidth to perform real-time digital
`
`signal processing using the system’s [DRAM] and not requiring the
`
`incorporation of an expensive block of [SRAM].” Id. at 4:55–60.
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`Figure 2 further illustrates that the architecture or system includes
`
`CPU 10, memory controller and arbiter (“MCA”) 200, main memory
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`subsystem 14, and DSP 20. Id. at Fig. 2. “Unlike prior art computer
`
`systems, the [system of Bowes] provides for the DSP 20 to reside on the
`
`system’s memory bus and operate from the computer systems’ main
`
`memory subsystem 14.” Id. at 6:22–26. “[T]his greatly reduces system cost
`
`by eliminating the need for an expensive block of SRAM.” Id. at 6:26–29.
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`16
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`In a preferred embodiment, MCA 200 “is an application specific integrated
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`circuit (ASIC) for arbitrating memory bus 110 between the various bus
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`masters subject to the constraints each imposes to provide optimal
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`bandwidth for each, particularly the DSP which is responsible for a
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`significant amount of real-time signal processing.” Id. at 6:46–52.
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`3. TMS Overview
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`TMS generally relates to a TMS320C8x, which is a DSP that supports
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`a variety of parallel processing configurations. Ex. 1006, iii, SL:1–1.5
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`According to TMS, the TMS320C8x has a “high degree of on-chip
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`integration,” which allows it to replace multiple devices, such as other DSPs.
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`Id. at SL:1–1. TMS discloses that the TMS320C8x may be used to
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`accelerate applications “such as video compression and decompression,
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`image processing, and graphics manipulation.” Id. at A–6. In particular,
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`TMS contemplates that TMS320C8x may be used for Moving Pictures
`
`Expert Group (“MPEG”) video compression and decompression. Id. at A–5.
`
`4. Thomas Overview
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`Thomas generally relates to “[a]n improved system bus structure for
`
`versatile use in various digital computer architecture configurations.”
`
`Ex. 1007, Abstract. Thomas discloses that a requesting unit, such as a CPU
`
`215 illustrated in Figure 2, may request bus access to perform “a full bus
`
`transfer or a half bus transfer.” Id. at 15:40–45. If a half bus transfer is
`
`
`
`5 All references to the page numbers in TMS refer to the original page
`numbers in either the lower, right-hand corner or lower, left-hand corner of
`Ex. 1006.
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`17
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`requested by two different units at the same time, under certain
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`circumstances bus arbiter 251 also illustrated in Figure 2 may “provid[e]
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`duplex functioning of the system bus by allowing memory read transfers and
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`data returns to take place on the same bus cycle.” Id. at 15:57–16:4; see also
`
`id. at 14:6–32 (disclosing another example of two different units
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`simultaneously accessing the system bus).
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`5. Claim 1
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`
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`In its Petition, Apple presents detailed explanations and relies on
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`supporting evidence demonstrating how Bowes teaches most of the
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`limitations of independent claim 1. Pet. 33–44. In particular, Apple relies
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`upon Bowes’ main memory subsystem 14, CPU 10, DSP 20, MCA 200,
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`memory bus 110 to account for the “memory,” “first device,” “decoder,”
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`“memory interface having an arbiter,” and “shared bus,” as recited in
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`independent claim 1, respectively. Id. at 33–42 (citing Ex. 1005, Fig. 2).
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`Apple further argues that, to the extent Bowes’ DSP 20 that performs image
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`processing does not teach explicitly the claimed “decoder,” TMS teaches a
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`TMS320C8x, which is a DSP that can be used for audio and video
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`decompression. Id. at 36–37 (citing Ex. 1006, iii, A–5, A–6). Apple also
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`argues that, to the extent Bowes’ memory bus 110 does not teach explicitly
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`the implementation details of the claimed “shared bus,” Thomas teaches an
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`improved bus structure that allows two different requesting devices
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`simultaneous access to the bus and the main memory unit connected thereto.
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`Id. at 42–43 (citing Ex. 1007, Abstract, 15:45–6:4). Apple then provides
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`numerous reasons that would have prompted one of ordinary skill in the art
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`to combine or modify the teachings of Bowes with those of TMS and
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`Thomas. See id. at 23–26, 28–32.
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`In its Preliminary Response, Parthenon presents the following two
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`arguments: (1) Apple’s proposed combination does not teach “an arbiter for
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`selectively providing access for the first device and the decoder to the
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`memory,” as recited in independent claim 1; and (2) one of ordinary skill in
`
`the art would not have had a sufficient reason to combine the teachings of
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`Bowes with those of TMS. Prelim. Resp. 7–12, 17–27. We address each of
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`Parthenon’s arguments in turn.
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`a. “Arbiter”
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`In its Preliminary Response, Parthenon argues that “MCA (200)
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`(identified as the arbiter) arbitrates access to the memory bus (110), not the
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`main memory subsystem (14) identified by the Petition as the main
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`memory.” Prelim. Resp. 8. Parthenon further argues that (1) bus arbiters
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`and memory arbiters grant access differently; and (2) a memory arbiter is
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`more efficient than a bus arbiter. Id. at 9–11.
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`Parthenon’s arguments, however, are not commensurate with
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`independent claim 1, which does not recite, for example, (1) guaranteeing
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`access to the memory; (2) “a memory arbiter”; or (3) controlling access to
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`the [memory/bus] most efficiently. See In re Self, 671 F.2d 1344, 1348
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`(CCPA 1982) (stating that limitations not appearing in the claims cannot be
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`relied upon for patentability). As a result, based on the current record, we
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`are persuaded by Apple’s contention that Bowes’ MCA 200, by controlling
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`access to memory bus 110, also controls access to the main memory
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`subsystem 14. See Pet. 39–40.
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`b. Remaining Limitations
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`In its Preliminary Response, Parthenon does not address separately
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`Apple’s explanations and supporting evidence with respect to the remaining
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`limitations recited in independent claim 1. See generally Prelim. Resp. 6–
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`27. We have reviewed Apple’s explanations and supporting evidence
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`regarding these remaining limitations and find them persuasive. See Pet.
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`33–44.
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`c. Rationale to Combine
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`As an initial matter, based on the current record, we are persuaded that
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`the numerous reasons Apple provides, which would have prompted one of
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`ordinary skill in the art to combine or modify the teachings of Bowes with
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`those of TMS and Thomas (see Pet. 23–26, 28–32), suffice as articulated
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`reasoning with some rational underpinning that would support the legal
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`conclusion of obviousness. See KSR, 550 U.S. at 418 (citing In re Kahn,
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`441 F.3d 977, 988 (Fed. Cir. 2006)). For instance, we are persuaded by
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`Apple’s assertion that one of ordinary skill in the art would have substituted
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`or replaced Bowes’ DSP 20 with TMS’ TMS320C8x, which is a DSP that
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`can be us
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