IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`Apple, Inc.
`PETITIONER
`
`v.
`
`Parthenon Unified Memory Architecture LLC
`PATENT OWNER
`___________
`Case IPR No: 2016-01135
`Patent No. 5,812,789
`Title: VIDEO AND/OR AUDIO DECOMPRESSION AND/OR COMPRESSION
`DEVICE THAT SHARES A MEMORY INTERFACE
`____________
`PATENT OWNER’S PRELIMINARY RESPONSE
`UNDER 37 C.F.R. §42.107
`
`
`
`
`
`
`
`
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`Apple, Inc.
`PETITIONER
`
`v.
`
`Parthenon Unified Memory Architecture LLC
`PATENT OWNER
`___________
`Case IPR No: 2016-01135
`Patent No. 5,812,789
`Title: VIDEO AND/OR AUDIO DECOMPRESSION AND/OR COMPRESSION
`DEVICE THAT SHARES A MEMORY INTERFACE
`____________
`PATENT OWNER’S PRELIMINARY RESPONSE
`UNDER 37 C.F.R. §42.107
`
`
`
`
`
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`TABLE OF CONTENTS
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`INTRODUCTION ........................................................................................... 1
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`THE ‘789 PATENT ......................................................................................... 2
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`I.
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`II.
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`III. CLAIM CONSTRUCTION ............................................................................ 2
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`A.
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`B.
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`C.
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`“decoder” (claims 1-4, 6, 8, and 12-13) ................................................ 4
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`“encoder” (claims 5-7) .......................................................................... 4
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`“variable bandwidth” (claim 2) ............................................................. 5
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`D. Other Claim Terms ................................................................................ 6
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`
`
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`IV. PETITIONER DOES NOT ESTABLISH A REASONABLE LIKELIHOOD
`THAT ANY CHALLENGED CLAIM IS INVALID ..................................... 6
`
`A.
`
`Bowes in view of TMS and Thomas (claims 1-5 and 12-14) ............... 6
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`1.
`
`The Combination of Bowes, TMS, and Thomas Does Not Disclose
`Every Element of the Challenged Claims ............................................. 7
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`
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`
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`2.
`
`B.
`
`a.
`
`b.
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`The proposed combination does not disclose an arbiter for
`selectively providing access for the first device and the decoder
`to the memory [claim 1] .............................................................. 7
`
`The proposed combination does not disclose a video decoder
`[claim 3] .................................................................................... 12
`
`No Motivation to Combine Bowes and TMS ..................................... 17
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`Bowes in view of TMS, Thomas, and Gove (claims 6 and 8) ............ 27
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`ii
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`Bowes in view of TMS, Thomas, and Ran (claim 7) .......................... 28
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`C.
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`D.
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`Bowes in view of TMS, Thomas, and Celi (claim 11) ....................... 29
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`CONCLUSION .............................................................................................. 30
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`V.
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`iii
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`TABLE OF AUTHORITIES
`
`
`Cases
`In re Rambus Inc.,
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`694 F.3d 42 (Fed. Cir. 2012) ........................................................................... 3
`
`C.R. Bard, Inc. v. M3 Sys., Inc.,
`
`157 F.3d 1350 (Fed. Cir. 1998) ..................................................................... 17
`
`In re Fine,
`
`837 F.2d 1071 (Fed. Cir. 1988) .......................................................... 7, 28, 29
`
`In re Wilson,
`
`424 F.2d 1382 (CCPA 1970) ........................................................................... 7
`
`Kinetic Tech., Inc. v. Skyworks Solutions, Inc.,
`IPR2014-00530, 2014 WL 4925282, (Patent Tr. & App. Bd. Sep. 29, 2014) ........ 18
`
`KSR Int’l Co. v. Teleflex Inc.,
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`550 U.S. 398 (2007)....................................................................................... 17
`
`Phillips v. AWH Corp.,
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`415 F.3d 1303 (Fed. Cir. 2005) ....................................................................... 3
`
`Teleflex, Inc. v. Ficos N. America Corp.,
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`299 F.3d 1313 (Fed. Cir. 2002) ..................................................................... 17
`
`Toyota Motor Corp. v. Cellport Sys., Inc.,
`
`Case IPR2015-00633, (PTAB Aug. 14, 2015) (Paper 11) .............................. 3
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`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
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`200 F.3d 795 (Fed. Cir. 1999) ......................................................................... 6
`
`iv
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`
`Rules
`35 U.S.C. § 314(a) ..................................................................................................... 1
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`37 C.F.R. § 42.5(b) .................................................................................................... 3
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`
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`v
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`TABLE OF EXHIBITS
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`Exhibit Description
`
`
`Exhibit
`No.
`
`2001
`2002
`2003
`2004
`
`Institution Decision, IPR2015-01944 (U.S. Pat. No. 5,812,789)
`Institution Decision, IPR2016-00923 (U.S. Pat. No. 5,812,789)
`Brad Hansen, The Dictionary of Multimedia, 1997
`Excerpts from Stone, H.S., High-Performance Computer Architecture,
`Addison-Wesley Publishing Company, Reading, Massachusetts, 1993,
`ISBN 0-201-52688-3.
`2005 MPEG Standard
`2006
`AT&T DSP3210 Digital Signal Processor The Multimedia Solution,
`Data Sheet, AT&T Microelectronics, March 1993 (“DSP3210
`Data Sheet”)
`Developer Note – Macintosh Quadra 840AV and Macintosh Centris
`660AV Computers (“Quadra Developer Note”)
`
`2007
`
`vi
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`
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`I.
`
`INTRODUCTION
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`The patent owner Parthenon Unified Memory Architecture LLC (“Patent
`
`Owner”) respectfully requests that the Board deny the Petition for Inter Partes
`
`review (“Petition”) filed by Apple, Inc. (“Apple” or “Petitioner”) regarding certain
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`claims of U.S. Patent No. 5,812,789 (“`789 Patent”) because the Petition fails to
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`demonstrate a reasonable likelihood that the Petitioner would prevail as to at least
`
`one of the challenged claims, as required under 35 U.S.C. § 314(a).
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`The Petition proposes four grounds challenging claims 1–8 and 11–14
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`(“challenged claims”). Specifically, the Petitioner contends that certain challenged
`
`claims are invalid as obvious in view of Bowes, TMS, and Thomas (Ground A).
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`The Petitioner also contends that certain dependent challenged claims are obvious
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`in view of Bowes, TMS, Thomas, and Gove (Ground B) or Ran (Ground C) or Celi
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`(Ground D).
`
`Ground A fails at least because Bowes, TMS, and Thomas, alone or in
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`combination, do not disclose all limitations of independent claim 1. Moreover, one
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`of ordinary skill in the art would not have been motivated to combine Bowes with
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`TMS as the Petitioner proposes. At least for these reasons, Bowes, TMS, and
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`Thomas, alone or in combination, fail to disclose all limitations of independent
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`claim 1 and do not render that claim obvious. By extension, the challenged
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`1
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`dependent claims are also not obvious in view of Bowes, TMS, and Thomas for at
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`least the same reasons. Therefore, there is no reasonable likelihood that the
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`Petitioner would prevail with respect to any of the claims challenged in Grounds
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`A-D, and the Petition should be denied.
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`II. THE `789 PATENT
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`The `789 Patent is generally directed to sharing a memory interface and
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`memory between a video and/or audio decoder and another device contained in an
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`electronic system. `789 Pat. [Ex. 1001], Abstract;
`
`independent claim 1.
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`Accordingly, the electronic system includes a first device that requires access to
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`the memory and a decoder that requires access to the memory sufficient to
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`maintain real time operation. Id. at claim 1. A memory interface is coupled to the
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`memory, the first device and the decoder. Id. The memory interface includes an
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`arbiter for selectively providing access for the first device and the decoder to the
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`memory. Id. A shared bus is coupled to the memory, the first device and the
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`decoder. Id. The shared bus has sufficient bandwidth to enable the decoder to
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`access the memory and operate in real time when the first device simultaneously
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`accesses the shared bus. Id.
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`III. CLAIM CONSTRUCTION
`
`2
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`Pursuant to 37 C.F.R. § 42.100(b), “[a] claim in an unexpired patent shall be
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`given its broadest reasonable construction in light of the specification of the patent
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`in which it appears.” The `789 Patent is likely to expire before the Board is likely
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`to issue a final written decision as to the patentability of the challenged claims.
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`Therefore, the claim terms are to be construed in accordance with the standard set
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`forth in Phillips.1 37 C.F.R. § 42.5(b); see Toyota Motor Corp. v. Cellport Sys.,
`
`Inc., Case IPR2015-00633, slip op. at 8-10 (PTAB Aug. 14, 2015) (Paper 11); cf.
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`In re Rambus Inc., 694 F.3d 42, 46 (Fed. Cir. 2012) (“While claims are generally
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`given their broadest possible scope during prosecution, the Board’s review of the
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`claims of an expired patent is similar to that of a district court’s review.”) (internal
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`citation omitted). Under this standard, the claim terms are given their ordinary and
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`accustomed meaning as understood by one having ordinary skill in the art at the
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`time of the invention in the context of the entire patent, considering intrinsic
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`evidence (the claims, the specification, and the prosecution history), and extrinsic
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`evidence (technical dictionaries, treatises, etc.) to a lesser extent. Phillips v. AWH
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`Corp., 415 F.3d 1303, 1313, 1316-17 (Fed. Cir. 2005).
`
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`1 The construction of the terms and the analysis of the claims set forth herein
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`would have remained the same even if the broadest reasonable interpretation
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`standard was applied.
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`3
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`A. “decoder” (claims 1-4, 6, 8, and 12-13)
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`Patent Owner disagrees with Petitioner’s proposed construction for the term
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`“decoder.” Patent Owner requests that to the extent the Board deems a construction
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`necessary, it construe this term consistent with the term’s construction in parallel
`
`proceedings. Specifically, Patent Owner requests that the term “decoder” be
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`construed to mean “hardware and/or software that translates data streams into
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`video or audio information.” See [Ex. 2001 IPR2015-01944, Institution Dec. at 8-
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`9]; [Ex. 2002 IPR2016-00923, Institution Dec. at 8-9]. This construction is
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`consistent with the specification as well as the dictionary definition of the term
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`“decoder”. [`789 Pat., Ex. 1001, 1:49-50 (“a video and/or audio decompression
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`device (hereinafter decoder)”)]; [Ex. 2003, at 56 (“decoder (n). Any hardware or
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`software system that translates data streams into video or audio information”)].
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`B. “encoder” (claims 5-7)
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`Patent Owner disagrees with Petitioner’s proposed construction for the term
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`“encoder.” Patent Owner requests that to the extent the Board deems a construction
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`necessary, it construe this term consistent with the construction of the term
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`“decoder” in parallel proceedings. Specifically, Patent Owner requests that the
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`term “encoder” be construed to mean “hardware and/or software that translates
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`video or audio information into data streams.” See [Ex. 2001 IPR2015-01944,
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`4
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`Institution Dec. at 8-9]; [Ex. 2002 IPR2016-00923, Institution Dec. at 8-9]. This
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`construction is consistent with the specification as well as the dictionary definition
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`of the related term “decoder”. [`789 Pat., Ex. 1001, 1:46-47 (“Video and/or audio
`
`compression devices (hereinafter encoders)”)]; [Ex. 2003, at 56 (“decoder (n). Any
`
`hardware or software system that translates data streams into video or audio
`
`information”)].
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`C. “variable bandwidth” (claim 2)
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`Patent Owner disagrees with Petitioner’s proposed construction for the term
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`“variable bandwidth.” Petitioner’s construction unnecessarily limits the term to the
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`shared bus bandwidth. Dependent claim 2 refers to both the “first device” and the
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`“decoder” having a “variable bandwidth.” [Ex. 1001 at 12:43-45]. Independent
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`claim 1 continually refers to both the “first device” and the “decoder” having
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`access “to the memory.” [Ex. 1001 at 12:30, 12:31, 12:36-37, 12:39-40 (emphasis
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`added)]. Because the claimed “variable bandwidth” can refer to the memory
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`bandwidth rather than the bus bandwidth, Patent Owner requests that the Board
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`reject Petitioner’s overly limiting construction. To the extent the Board deems a
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`construction necessary, Patent Owner requests that the Board construe this term to
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`5
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`mean “variable rate at which 1) data is read from or written to the memory; or 2)
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`data is transferred over the bus.” 2
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`D. Other Claim Terms
`Only terms which are in controversy in this proceeding need to be construed,
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`and then only to the extent necessary to resolve the controversy. Vivid Techs., Inc.
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`v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
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`With respect to the claim terms “bus” and “arbiter,” unless otherwise noted,
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`the analysis below applies the constructions agreed to by the parties in the parallel
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`litigation. Ex. 1011, pp. 1-2. Those agreed constructions are consistent with the
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`Phillips standard. Moreover, unless explicitly noted below, the validity analysis
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`below remains unchanged even under a broadest reasonable interpretation of these
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`terms.
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`IV. PETITIONER DOES NOT ESTABLISH A REASONABLE LIKELIHOOD
`THAT ANY CHALLENGED CLAIM IS INVALID
`
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`A. Bowes in view of TMS and Thomas (claims 1-5 and 12-14)
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`2 The analysis herein would remain unchanged even if the Board were to adopt the
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`Petitioner’s proposed constructions for the terms “decoder,” “encoder,” “real
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`time,” and “variable bandwidth” or otherwise construe these terms.
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`6
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`Bowes in view of TMS and Thomas does not render the challenged claims
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`obvious because all three references fail to disclose at least one limitation of
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`independent claim 1, and all other challenged claims are dependent on claim 1. In
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`re Fine, 837 F.2d 1071, 1076 (Fed. Cir. 1988) (“Dependent claims are nonobvious
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`under § 103 if the independent claims from which they depend are nonobvious”)
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`1. The Combination of Bowes, TMS, and Thomas Does Not Disclose
`Every Element of the Challenged Claims
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`The proposed combination does not disclose “each and every” claim
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`limitation. See, e.g., In re Wilson, 424 F.2d 1382 1385 (CCPA 1970) (“All words
`
`in a claim must be considered in judging the patentability of that claim against the
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`prior art”).
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`a. The proposed combination does not disclose an arbiter for selectively
`providing access for the first device and the decoder to the memory
`[claim 1]
`
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`Independent claim 1 recites “an arbiter for selectively providing access for
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`the first device and the decoder to the memory.” Ex. 1001, claim 1.
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`7
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`Petitioner identifies Bowes’3 memory controller and arbiter (MCA) as the
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`recited arbiter. [Pet. at 39-40]. However, the MCA (200) (identified as the arbiter)
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`arbitrates access to the memory bus (110), not the main memory subsystem (14)
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`identified by the Petition as the main memory. [Bowes, 4:15-17 (“[a] method and
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`apparatus are described for the arbitration of a number of bus masters over a
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`memory bus in a computer system architecture support a digital signal processor”);
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`6:46-54 (“[T]he arbiter 200 is an application specific integrated circuit (ASIC) for
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`arbitrating the memory bus 110 between the various bus masters”); 7:64-8:7
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`(“[T]he resource propagates a bus request signal over the memory bus 110 to the
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`arbiter 200. … When the memory bus is available for assignment, the arbiter 200
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`will issue a bus grant signal to one of the resources according to a priority
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`scheme”); 8:5-7 (“When the memory bus is available for assignment, the arbiter
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`200 will issue a bus grant signal to one of the resources . . . .”)]. In fact, the
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`specification refers to the MCA (200) as the “bus arbiter” [Bowes, 8:23].
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`Essentially, selectively providing access to the bus is analogous to limiting
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`access to a toll road to a single class of vehicles whereas selectively providing
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`3 With respect to this limitation, the Petitioner only relies on Bowes. [Pet. at 39-
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`40]. Accordingly, the Patent Owner’s analysis also focuses on that reference.
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`However, TMS and Thomas do not disclose that which Bowes lacks.
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`access to the memory is analogous to allowing any vehicle on the toll road but only
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`allowing a single class of vehicles to take a particular single exit off of the toll
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`road. Accordingly, for at least two reasons, selectively providing access to the
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`memory as recited in claim 1 is not the same as merely selectively providing
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`access to a peripheral bus that can facilitate communication with the memory as
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`well as with other components as recited in Bowes.
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`First, an arbiter that selectively provides access to the bus, such as that
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`disclosed by Bowes, receives requests for access to the bus and determines which
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`device has sole ownership of the bus for a given period of time. The maximum
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`bandwidth of a bus relates to the maximum number of bus cycles per second. A
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`bus arbiter such as that disclosed in Bowes arbitrates access to the bus in
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`predetermined time slices which span multiple bus transaction cycles causing the
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`bus to be monopolized. [Bowes, 3:23-28; 8:9-10; 8:25-28; 9:26-35; 10:41-51]. In
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`contrast, a memory arbiter arbitrates access to memory in relation to the memory
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`read/write requests. Accordingly, a bus arbiter such as that disclosed in Bowes
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`grants a device access to the bus for a predetermined maximum possible time
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`period whereas a memory arbiter such as that disclosed in the `789 patent grants a
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`device access to the memory on a per memory transaction cycle basis.
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`Second, having an arbiter that selectively provides access to the memory
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`offers efficiencies that cannot be achieved in a system where the arbiter selectively
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`provides access to the bus. Specifically, the `789 Patent states that “[i]n the
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`preferred embodiment, even during decoding and encoding the decoder/encoder 45
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`does not always use the entire required bandwidth.” [`789 Pat., 7:10-13]. For
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`instance, the decoder/encoder (45) may use 60% of the available bandwidth while
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`the remaining bandwidth is available to the other devices with which the
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`decoder/encoder is sharing the main memory. [`789 Pat., 7:13-16]. As an
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`illustrative example, assume that the main memory has a bandwidth of 100
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`Mbytes/second. If the decoder/encoder (45) only uses 60% of the main memory
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`bandwidth, then the decoder may only read or write 60 Mbytes of data from or to
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`the main memory in 1 second. An arbiter that selectively provides access to the
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`memory can then allow another device to read or write the remaining 40 Mbytes of
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`data from or to the main memory during the same 1 second time interval.
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`Accordingly, having an arbiter that selectively provides access to the memory
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`allows the system of the `789 Patent to provide access by more than one device to
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`the memory in a given period of time, or, as referred to in Bowes, a time “slice” or
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`“slot” [Bowes, Abstract; 3:23-35; 4:3; 8:33-35; 8:41-50; 9:6-10; 9:21-26; 9:35-58;
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`7:48-50; 12:36-49]. In contrast, it is not possible for more than one device to
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`access the memory in a single time slice in the Bowes system where the Bowes bus
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`arbiter selectively provides access to the bus and limits that access to one of a
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`plurality of devices. Specifically, the arbiter of Bowes, which selectively provides
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`access to the bus, assigns the bus to one single device for a given time slice
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`regardless of whether that device uses the entire bandwidth of the main memory
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`assigned to it in that time slice or not. That is, in the illustrative example discussed
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`above, once the decoder reads and/or writes 60 Mbytes of data from or to the
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`memory in 1 second, the remaining 40 Mbytes that could also be accessed in that
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`same 1 second time slot will go unused and will not be available to another device.
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`Accordingly, an arbiter that selectively provides access to the main memory
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`facilitates accesses on a per memory transaction basis whereas an arbiter that
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`selectively provides access to the bus assigns the bus to a single master for a given
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`maximum period of time in a one of a finite number of predetermined sequences.
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`Bowes explicitly indicates that these inefficiencies are present and contemplates
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`the condition wherein the bus is assigned to a master wherein that master is not
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`utilizing the bus, even when some other subsystem may be in need of the bus:
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`“During the time that the DSP is granted the memory bus and the bus arbitration
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`logic 240 holds the bus busy signal active even though the DSP may not be
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`utilizing the memory bus, ….” [Bowes, 10:30-37; 10:41-51].
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`Therefore, Bowes’ alleged disclosure of a central arbiter that selectively
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`provides access to a bus does not satisfy the limitation of independent claim 1,
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`which recites an arbiter that selectively provides access to the memory.
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`b. The proposed combination does not disclose a video decoder [claim 3]
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`Dependent claim 3 recites “a video decoder.” Ex. 1001, claim 1. The
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`Petitioner relies on only Bowes and TMS with respect to this limitation. [Pet. at
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`47-49.]
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`Petitioner has identified the DSP of Bowes as being analogous to the video
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`decoder recited in the `789 Patent. [e.g., Petition at 47]. Bowes does not state that
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`the DSP is suitable for video compression and decompression applications such as
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`the implementations of the MPEG Standard. The words “decode” or “decoding”
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`never appear in Bowes. Indeed, Petitioner’s only support for its identification of
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`the Bowes DSP as a video decoder is that the DSP performs “image processing.”
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`Id.
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`A POSA would recognize that “image processing” is clearly distinct from
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`video compression and decompression. Therefore, a POSA would understand that
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`the “image processing” referenced in Bowes is distinct from the video decoding
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`implementations disclosed in the `789 Patent.
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`IPR2016-01135
`Patent Owner Preliminary Response
`U.S. Patent No. 5,812,789
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`In the 1993 time frame, “image processing” was defined as “a computation
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`performed on a digitized representation of an image whose purpose is to enhance
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`the image or to extract information about the image.” [Ex. 2004 at 499]. In
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`contrast, the MPEG Standard is directed to compressing and decompressing video
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`sequences. [Ex. 2005, p. 4]. Such a compression and decompression of video
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`sequences is wholly different from image processing. For example, video
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`compression and decompression requires maintaining the temporal relationship
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`between consecutive image frames, an important concept that is absent when
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`processing a single image.
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`There are additional reasons why a POSA would recognize that a DSP used
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`for image processing is not suitable for video compression and decompression.
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`Specifically, image processing requires precision and involves a host of arithmetic
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`operations. In contrast,
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`the primary concern
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`in video compression and
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`decompression is speed to ensure that video is delivered to viewer in real time.
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`Therefore, video compression and decompression processes typically do not
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`require the same level of precision and arithmetic operations as image processing.
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`As a result, a POSA would typically use a different type of DSP for image
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`processing as compared to video compression and decompression. Specifically, the
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`internal architecture of a DSP may be categorized according to the type of
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`U.S. Patent No. 5,812,789
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`numerical format it utilizes. A “floating point” DSP utilizes a format wherein a
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`single value is specified with three fields, a sign field indicating whether the value
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`is positive or negative; a mantissa or significand field indicating the precision of
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`the value; and a signed exponent field indicating the magnitude. In contrast, a
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`“fixed point” DSP utilizes a format wherein a single value represents the signed
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`value using an appropriate signed value encoding such as 2’s complement and
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`where the binary- or radix point is in a “fixed” position.
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`That the DSP of Bowes is not suitable for video compression and
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`decompression is further evident from the fact that Bowes states that in a preferred
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`embodiment, the DSP of Bowes is the AT&T DSP3210. [Bowes, 6:28-30]. Such a
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`DSP is not suitable for MPEG video decoding because it is a floating point DSP.
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`[Ex. 2006, at 1]. Specifically, the AT&T DSP3210 utilizes a floating-point Data
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`Arithmetic Unit (DAU) that “is the primary execution unit for signal processing
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`algorithms.” [Ex. 2006, at 5].
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`Due to its use of a more complex format, a floating point DSP generally
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`incurs increased latency but provides increased accuracy and dynamic range (i.e., it
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`can represent a wider range of numerical values). In contrast, a fixed point DSP
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`allows higher performance but at the expense of decreased accuracy and dynamic
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`range. Therefore, a POSA would appreciate that a floating point DSP is not well-
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`U.S. Patent No. 5,812,789
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`suited for video compression and decompression.
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`A POSA would appreciate that MPEG decoding is a high throughput
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`operation consisting in part, of repeated inverse discrete cosine transforms (IDCT),
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`VLD, de-quantization, and other processes. Floating-point DSPs (such as the
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`DSP3210) provide for higher dynamic range and more accuracy in their
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`computations, but at the expense of increased latency whereas a fixed point DSP
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`requires shorter internal data paths providing for performance advantages. While it
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`may appear that the increased accuracy provided by floating-point DSPs would be
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`advantageous in IDCT operations, for video and specifically MPEG video
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`decompression, the IDCT operations are performed over relatively short bit-exact
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`data that ultimately represents a pixel value, thus increased precision as provided
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`by a more costly floating-point DSP would offer no advantage when used as an
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`MPEG video decoder. Further, the other intensive processes require a considerable
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`amount of control instructions to be executed rather than arithmetic instructions
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`(e.g., table lookups). A POSA would therefore recognize that a floating point DSP
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`(such as the DSP3210 of Bowes) is not well-suited for MPEG video decoding.
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`Indeed the disclosed and intended applications of the DSP in the preferred
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`embodiments of Bowes are those that would require the extended dynamic range
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`and precision provided by a floating point DSP such as audio, image processing,
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`speech processing, and modem emulation. [Bowes Pat., 1:48-49; 6:32-37].
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`Floating-point processors are incompatible with MPEG decoding due to the
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`format of the encoded and decoded MPEG video data as in the MPEG standard
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`and the H.262 specifications. The video data as per the standard and specification
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`is not in the form of floating point values and would require conversions to
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`floating-point prior to decoding and a conversion back to its initial format after
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`decoding. A POSA would recognize that these conversions would incur additional
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`processing delay that would be otherwise unnecessary if a fixed-point DSP were
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`used. Floating-point values typically require that the significand fall within a
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`numerical range such as between 1 and 2, with the exponent field used to indicate
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`the actual location of the binary-point. Thus, all input encoded MPEG values
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`would need to be converted to this floating-point format before processing, and the
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`resulting decoded values would have to be converted back from this range to
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`appropriate pixel representations that are collections of fixed-point values. Such
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`numerous conversions to and from floating point data could cause the real time
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`decoding constraint to be unrealizable. Furthermore, floating-point representations
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`are unnecessary for MPEG decoding and cause additional processing delay with no
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`technical benefit.
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`TMS also fails to disclose a “video decoder.” This is because TMS is a
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`programmable multiprocessor system, and that does not include a decoder, video
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`decoder, or a video circuit.
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`2. No Motivation to Combine Bowes and TMS
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`One of ordinary skill in the art would not have been motivated to combine
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`Bowes and TMS as suggested by the Petitioner. There must be a clear and explicit
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`articulation of reasons why the claimed invention would have been obvious. KSR
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`Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). The law is clear that “a patent
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`composed of several elements is not proved obvious merely by demonstrating that
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`each of its elements was, independently, known in the prior art.” KSR, 550 U.S. at
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`418. Accordingly, a showing of a suggestion, teaching, or motivation to combine
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`the prior art references is an “essential evidentiary component of an obviousness
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`holding.” C.R. Bard, Inc. v. M3 Sys., Inc., 157 F.3d 1350, 1352 (Fed. Cir. 1998).
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`Petitioner suggests that any modifications to Bowes to accommodate the
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`teachings of TMS would have been within the level of a POSA. See, e.g., Pet. at
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`25-26. However, the “showing of a motivation to combine must be clear and
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`particular, and it must be supported by actual evidence.” Teleflex, Inc. v. Ficos N.
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`America Corp., 299 F.3d 1313, 1334 (Fed. Cir. 2002). The Petitioner offers no
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`evidence in support of its conclusory assertion that any such modifications would
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`be within the level of a POSA. Pet. at 25-26.4
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`A POSA would not have been motivated to combine Bowes with TMS. In
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`particular, replacing the Bowes DSP with the TMS DSP would not result in an
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`operable decoder. The Bowes bus arbitration functionality utilizes one of a set of
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`predetermined, statically fixed sequences of bus ownership among the four
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`disclosed potential bus masters in Bowes. Additionally, the time that each potential
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`bus master may utilize the system bus in Bowes is time limited by a fixed amount
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`in each arbitration cycle. A person of skill would be required to engage in
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`significant experimentation to predetermine that amount of time that should be
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`4 While the Petitioner submits a Declaration from Dr. Colwell, to the extent that
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`declaration merely repeats the same arguments from the Petition -- for instance
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`making the same conclusory statement that the combination would yield a
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`predictable result -- it should not be given probative weight. See, e.g., Kinetic
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`Tech., Inc. v. Skyworks Solutions, Inc., No. IPR2014-00530, 2014 WL 4925282,
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`*11 (P.T.A.B. Sep. 29, 2014) (“Merely repeating an argument from the Petition
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`in the declaration of a proposed expert does not give that argument enhanced
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`probative value. Accordingly, we give the cited evidence of [Expert’s]
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`Declaration no probative weight.”)
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`allotted to the TMS DSP and the other potential bus masters in the Bowes system
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`for each of the possible sequences of bus mastership allowed by the Bowes bus
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`arbitration state diagram. This represents an undue amount of experimentation.
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`Even if this undue amount of experimentation were undertaken and completed,
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`there is no guarantee that a set of maxim
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