`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`———————
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`———————
`
`
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`Parthenon Unified Memory Architecture LLC
`Patent Owner
`
`———————
`
`
`
`PETITION FOR INTER PARTES REVIEW
`
`OF
`
`U.S. PATENT NO. 5,812,789
`
`
`
`
`
`
`
`

`

`
`
`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
`TABLE OF CONTENTS
`
`I.
`
`INTRODUCTION ............................................................................................. 1
`
`II. MANDATORY NOTICES ............................................................................... 2
`
`A. Real Party-in-Interest................................................................................ 2
`
`B. Related Matters ......................................................................................... 2
`
`C. Lead and Back-up Counsel and Service Information .............................. 3
`
`III. GROUNDS FOR STANDING .......................................................................... 4
`
`IV. RELIEF REQUESTED ..................................................................................... 4
`
`V. THE REASONS FOR THE REQUESTED RELIEF ........................................ 4
`
`A. The ’789 Patent ......................................................................................... 5
`
`1. Overview .......................................................................................... 5
`
`2.
`
`Prosecution History .......................................................................... 9
`
`B.
`
`Identification of Challenges ................................................................... 10
`
`1. Challenged Claims ......................................................................... 10
`
`2.
`
`Statutory Ground for Challenges ................................................... 10
`
`3. Redundancy .................................................................................... 12
`
`C. Claim Construction ................................................................................. 14
`
`i.
`
`ii.
`
`“decoder” ................................................................................ 15
`
`“encoder” ................................................................................ 16
`
`iii. “real time” ............................................................................... 16
`
`iv. “variable bandwidth” .............................................................. 17
`
`
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`

`

`
`
`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
`1.
`
`Identification of How the Claims Are Unpatentable ..................... 19
`
`i.
`
`Challenge #1: Claims 1-5 and 12-14 are obvious under 35
`U.S.C § 103 over Bowes in view of TMS and Thomas ......... 19
`
`ii. Challenge #2: Claims 6 and 8 are obvious under 35 U.S.C §
`103 over Bowes in view of TMS and Thomas, further in view
`of Gove .................................................................................... 54
`
`iii. Challenge #3: Claim 7 is obvious under 35 U.S.C § 103 over
`Bowes in view of TMS and Thomas, further in view of Ran . 59
`
`iv. Challenge #4: Claim 11 is obvious under 35 U.S.C § 103 over
`Bowes in view of TMS and Thomas, further in view of Celi 62
`
`VI. Conclusion .......................................................................................................69
`
`
`
`
`
`

`

`
`I.
`
`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
`INTRODUCTION
`U.S. Patent No. 5,812,789 (“the ’789 Patent,” APPL1001) is generally
`
`directed to a system where a video decoder and another device share memory. See
`
`APPL1001, Abstract, 3:62-4:11, 5:15-22.
`
`The ’789 Patent alleges that, conventionally, a video decoder would have its
`
`own dedicated memory. APPL1001, 2:25-33, 3:52-59. The ’789 Patent suggests
`
`that this dedicated memory would “significantly increase the cost of adding a
`
`decoder … to the computer.” APPL1001, 3:57-59. However, before the priority
`
`date of the ’789 Patent, others had already recognized the same cost concerns of
`
`using a dedicated memory, had proposed to use a shared memory in lieu of a
`
`dedicated memory, and had developed arbitration schemes for sharing this
`
`memory.
`
`For example, Bowes (APPL1005) recognized the benefits of allowing its
`
`digital signal processor (DSP) 20 to use a shared memory (main memory
`
`subsystem 14) by arbitrating access to the shared memory among the DSP 20 and
`
`other devices, including a CPU 10, all while allowing the DSP to still operate in
`
`real time. See APPL1005, APPL1006.
`
`The evidence in this petition demonstrates that claims 1-8 and 11-14 of the
`
`’789 Patent are unpatentable under pre-AIA 35 U.S.C. § 103. Accordingly, Apple
`
`Inc. (“Petitioner”) respectfully requests that claims 1-8 and 11-14 of the ’789
`
`
`
`1
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
`
`Patent be held invalid and cancelled.
`
`II. MANDATORY NOTICES
`A. Real Party-in-Interest
`The real party-in-interest is Apple Inc.
`
`B. Related Matters
`As of the filing date of this petition, the ’789 Patent has been asserted in:
`
` STMicroelectronics v. Motorola Inc., 4:03-CV-00276 (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. Apple Inc., 2-15-CV-00621
`
`(E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. Huawei Tech. Co., Ltd. et
`
`al., 2:14-CV-00687 (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. Motorola Mobility, Inc.,
`
`2:14-CV-00689 (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. HTC Corp. et al., 2:14-CV-
`
`00690 (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. LG Elec., Inc. et al., 2:14-
`
`CV-00691 (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. Samsung Elecs. Co. Ltd. et
`
`al., No. 2:14-CV-00902 (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. Qualcomm Inc. et al., No.
`
`2:14-CV-00930 (E.D. Tex.);
`
`2
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
` Parthenon Unified Memory Architecture LLC v. ZTE Corp. et al., No. 2:15-
`
`CV-00225 (E.D. Tex.); and
`
` Parthenon Unified Memory Architecture LLC v. LG Electronics
`
`MobileComm, USA, 2-15-CV-01950 (E.D. Tex.);
`
`Additionally, the ’789 Patent has been challenged in inter partes review
`
`proceedings:
`
` IPR2015-01944 filed by Samsung Elecs. Co., Ltd. and Samsung Elecs. Am.,
`
`Inc.;
`
` IPR2016-00664 filed by ZTE Corporation, ZTE (TX) Inc., and ZTE USA,
`
`Inc.;
`
` IPR2016-00847 filed by HTC Corporation, HTC America, Inc., LG
`
`Electronics, Inc., LG Electronics U.S.A., Inc., and LG Electronics
`
`MobileComm U.S.A., Inc.; and
`
` IPR2016-00923 filed by Apple Inc.
`
`Apple Inc. is not a real party-in-interest in IPR2015-01944, IPR2016-00664, or
`
`IPR2016-00847.
`
`C. Lead and Back-up Counsel and Service Information
`Lead Counsel
`
`Andrew S. Ehmke
`Phone: (214) 651-5116
`HAYNES AND BOONE, LLP
`Fax: (214) 200-0853
`2323 Victory Ave. Suite 700
`andy.ehmke.ipr@haynesboone.com
`Dallas, TX 75219
`USPTO Reg. No. 50,271
`
`
`
`
`
`3
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`

`

`
`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
`Back-up Counsel
`David W O’Brien
`HAYNES AND BOONE, LLP
`2323 Victory Ave. Suite 700
`Dallas, TX 75219
`
`
`Phone: (512) 867-8457
`Fax: (214) 200-0853
`david.obrien.ipr@haynesboone.com
`USPTO Reg. No. 40,107
`
`Please address all correspondence to lead and back-up counsel. Petitioner
`
`consents to electronic service by email.
`
`III. GROUNDS FOR STANDING
`Petitioner certifies that the ’789 Patent is eligible for inter partes review and
`
`that Petitioner is not barred or estopped from requesting inter partes review
`
`challenging the patent claims on the grounds identified in this petition. Petitioner
`
`was served with a complaint asserting infringement of the ’789 Patent on June 5,
`
`2015 (see APPL1018, p. 3), which is not more than one year before the filing of
`
`this Petition. Petitioner has not filed a civil action challenging the validity of any
`
`claim of the ’789 Patent.
`
`IV. RELIEF REQUESTED
`Petitioner asks that the Patent Trial and Appeal Board (“Board”) review the
`
`accompanying prior art and analysis, institute a trial for inter partes review of
`
`claims 1-8 and 11-14 of the ’789 Patent, and cancel those claims as invalid.
`
`V. THE REASONS FOR THE REQUESTED RELIEF
`As explained below and in the declaration of Petitioner’s expert, Robert
`
`Colwell, Ph.D. (APPL1003), the concepts described and claimed in the ’789 Patent
`
`were not novel. This petition explains where each element of claims 1-8 and 11-14
`
`
`
`4
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`

`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
`
`is found in the prior art and why the claims would have been obvious to a person of
`
`ordinary skill in the art before the earliest claimed priority date of the ’789 Patent.
`
`The full statement of the reasons for the relief requested is as follows.
`
`A. The ’789 Patent
`1. Overview
`The ’789 Patent was filed on August 26, 1996. The ’789 Patent has 33
`
`claims in total, including independent claims 1, 15, and 29, of which independent
`
`claim 1 is challenged by the present petition.
`
`The ’789 Patent describes an electronic system with a first device and a
`
`“video and/or audio decompression and/or compression device” that share a
`
`memory interface in a manner that permits the device to operate in real time.
`
`APPL1001, Abstract. In order to fit digital media, such as movies, onto
`
`“conventional recording medium, such as a CD,” it was already known to
`
`“compress video and audio sequences before they are transmitted or stored.” Id. at
`
`1:25-34. For compression/decompression, “[t]he MPEG standards are currently
`
`well accepted standards for one way communication. H.261, and H.263 are
`
`currently well accepted standards for video telephony.” Id. at 1:56-59; APPL1003,
`
`¶ 23.
`
`The ’789 Patent further states that electronic systems added decoders to
`
`these systems in order to “allow them to display compressed sequences” and
`
`encoders “to allow the system to compress video and/or audio sequences to be
`5
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`

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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
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`transmitted or stored.” APPL1001, 1:64-2:2. The ’789 Patent continued that a
`
`decoder for MPEG sequences “typically … requires a 2 Mbyte memory,” and that
`
`such memory was “dedicated to the MPEG decoder 10 and increases the price of
`
`adding a decoder 10 to the electronic system.” Id. at 2:28-31; APPL1003, ¶ 24.
`
`The ’789 Patent allegedly addresses these problems by having the “video
`
`and/or audio decompression and/or compression device share[] a memory interface
`
`and the memory with the first device.” APPL1001, 3:67-4:2. An arbiter is used “to
`
`arbitrate between the two devices when one of them is requesting access to the
`
`memory.” Id. at 4:4-8. The ’789 Patent explains that its proposed solution results in
`
`cost reduction “due to the fact that the video and/or audio decompression and/or
`
`compression device does not need its own dedicated memory but can share a
`
`memory with another device and still operate in real time.” Id. at 4:30-34. Figure 2
`
`illustrates an electronic system containing a device having a memory interface and
`
`an encoder and decoder:
`
`
`
`6
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`

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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
`APPL1001, Fig. 2
`
`
`
`APPL1003, ¶¶ 25, 26.
`
`
`
`The ’789 Patent further explains that its real time operation is made possible
`
`through an arbiter, where requests obtain access to the memory through the arbiter
`
`based on the priority scheme, which “can be any priority scheme that ensures that
`
`the decoder/encoder 45 gets access to the memory 50 often enough and for enough
`
`of a burst length to operate properly, yet not starve the other devices sharing the
`
`memory.” APPL1001, 10:9-24; APPL1003, ¶ 27.
`
`
`
`7
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`

`

`
`
`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
`In claim 1 of the ’789 Patent, a “first device” and a “decoder” both require
`
`access to a memory. As explained by the ’789 Patent, the “first device” “can be a
`
`processor, a core logic chipset, a graphics accelerator, or any other device that
`
`requires access to the memory 50, and either contains or is coupled to a memory
`
`interface.” APPL1001, 5:19-22. Further, the ’789 Patent defines “decoder” as “a
`
`video and/or audio decompression device.” Id. at 1:48-51; APPL1003, ¶ 30.
`
`
`
` The “first device” and the “decoder” are coupled to a memory and an
`
`arbiter, all of which are coupled to a “shared bus.” The “shared bus” is claimed as
`
`having a “sufficient bandwidth” to enable the “decoder” to operate in real time
`
`“when the first device simultaneously accesses the bus.” According to the ’789
`
`Patent, “[a] goal is to have the decoder/encoder 45 operate in real time without
`
`dropping so many frames that it becomes noticeable to the human viewer of the
`
`movie. To operate in real time the decoder/encoder 45 should decoder and/or
`
`encode images fast enough so that any delay in decoding and/or encoding cannot
`
`be detected by a human viewer.” APPL1001, 6:41-46. The ’789 Patent continues
`
`that “[t]o operate in real time the required bandwidth should be lower than the
`
`bandwidth of the bus.” Id. at 6:52-53; APPL1003, ¶¶ 31-32.
`
`As discussed below in more detail, the system presented in the ’789 Patent—
`
`sharing a memory between multiple devices and arbitrating access thereto between
`
`
`
`8
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`

`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
`
`the devices—was well known to persons of ordinary skill in the art before the
`
`earliest alleged priority date of the ’789 Patent. APPL1003, ¶¶ 28-29, 33-34.
`
`Prosecution History
`2.
`The ’789 Patent issued on September 22, 1998 from Application No.
`
`08/702,911 filed on Aug. 26, 1996.
`
`The claims of Application No. 08/702,911, which issued as the ’789 Patent,
`
`were rejected just once during prosecution. In response, the Applicants deleted a
`
`recitation of “a fast bus coupled to the first device and the decoder” in independent
`
`claim 1 and added the limitation “and a shared bus coupled to the memory, the first
`
`device, and the decoder, the bus having a sufficient bandwidth to enable the
`
`decoder to access the memory and operate in real time when the first device
`
`simultaneously accesses the bus.” APPL1002, p. 106.
`
`In arguing against the rejection, the Applicants asserted that the references
`
`either did not disclose arbitration “for accomplishing real time operation of the
`
`decoder” or were “not concerned with real time operation.” Id. at pp. 108-109. The
`
`Examiner allowed the application in response to the amendment and arguments
`
`filed. APPL1002, pp. 112-115.
`
`As illustrated herein, the prior art teaches a memory bus and an arbiter
`
`circuit that perform these functions in support of real time operation of a DSP
`
`while other devices are simultaneously accessing the memory bus.
`
`
`
`9
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`

`

`
`B.
`
`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
`Identification of Challenges
`Challenged Claims
`1.
`Claims 1-8 and 11-14 of the ’789 Patent are challenged in this petition.
`
`Statutory Ground for Challenges
`2.
`Challenge #1: Claims 1-5 and 12-14 are obvious under 35 U.S.C. § 103
`
`over U.S. Patent No. 5,546,547 to Bowes et al. (“Bowes”) in view of TMS320C8x
`
`System-Level Synopsis (“TMS”).
`
`Bowes was filed January 28, 1994 and issued August 13, 1996, and for
`
`purposes of this Petition is prior art to the ’789 Patent at least under (pre-AIA) 35
`
`U.S.C. §§ 102(a) and (e).
`
`TMS is an official Texas Instruments (TI) publication that was obtained
`
`from TI’s website. APPL1020, ¶ 3. TMS has a copyright date of 1995 and is
`
`identified as being printed in September 1995. See APPL1006, cover page. Further,
`
`a contemporaneous TI manual (APPL1019, “Software Guide”) indicates that TMS
`
`and other TI documents describing the TMS320C8x could have been obtained in
`
`November 1995 by calling the Texas Instruments Literature Response Center.
`
`APPL1019, p. iv (“[t]o obtain a copy of any of these TI documents [including
`
`TMS, APPL1006], call the Texas Instruments Literature Response Center at (800)
`
`477–8924.”). The Software Guide is also an official TI publication obtained from
`
`TI’s website with a copyright date of 1995 and is identified as being printed in
`
`November 1995. APPL1020, ¶ 4.
`
`
`
`10
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`

`

`
`
`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
`Accordingly, TMS was a printed, ancient document that could be ordered by
`
`the public at least as of November 1995 and thus was publicly available at least by
`
`November 1995. TMS is thus, for purposes of this Petition, prior art to the ’789
`
`Patent at least under (pre-AIA) 35 U.S.C. § 102(a).
`
`Challenge #2: Claims 6 and 8 are invalid under 35 U.S.C § 103 over Bowes
`
`in view of TMS, further in view of “The MVP: A Highly-Integrated Video
`
`Compression Chip,” R.J. Gove, Proceedings of the IEEE Data Compression
`
`Conference (DCC ’94), pp. 215-224 (“Gove”).
`
`Gove was included in the proceedings of the Data Compression Conference
`
`held March 29-31, 1994. Moreover, the copyright registration filed with the
`
`Copyright Office indicates Gove was published March 29, 1994. See APPL1008;
`
`APPL1020; see also APPL1003, ¶ 96. Gove is thus, for purposes of this Petition,
`
`prior art to the ’789 Patent at least under (pre-AIA) 35 U.S.C. § 102(b).
`
`Challenge #3: Claim 7 is invalid under 35 U.S.C § 103 over Bowes in view
`
`of TMS, further in view of U.S. Patent No. 5,768,533 to Ran (“Ran”). Ran was
`
`filed on September 1, 1995 and issued June 16, 1998, and for purposes of this
`
`Petition is prior art to the ’789 Patent at least under (pre-AIA) 35 U.S.C. § 102(e).
`
`Challenge #4: Claim 11 is invalid under 35 U.S.C § 103 over Bowes in
`
`view of TMS, further in view of U.S. Patent No. 5,742,797 to Celi et al. (“Celi”).
`
`Celi was filed on August 11, 1995 and issued April 21, 1998, and for purposes of
`
`
`
`11
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
`
`this Petition is prior art to the ’789 Patent at least under (pre-AIA) 35 U.S.C. §
`
`102(e).
`
`Redundancy
`3.
`The ’789 Patent is currently the subject of additional inter partes review
`
`proceedings, IPR2015-01944 (instituted/settled), IPR2016-00664 (pre-institution),
`
`and IPR2016-00847 (pre-institution). Petitioner is not a real party-in-interest in any
`
`of these inter partes review proceedings and has no control over the filings.
`
`Moreover, Petitioner’s interests and burdens are different than those of the
`
`IPR2015-01944, IPR2016-00664, or IPR2016-00847 petitioners. See Sony Mobile
`
`Comm. (USA) Inc., v. E-Watch, Inc., IPR2015-00401, Paper 13 at 9 (PTAB 2015)
`
`(dismissing Patent Owner’s § 325(d) arguments citing the “need to be cognizant of
`
`the interests of other petitioners”). Petitioner filed IPR2016-00923 with a motion to
`
`join with IPR2015-01944 and therefore mirrors the challenges raised in the other
`
`pending inter partes review proceedings.
`
`The challenges presented in the instant petition rely on different prior art
`
`combinations, different arguments regarding the asserted prior art, and different
`
`expert declaration testimony than those relied upon in IPR2015-01944, IPR2016-
`
`00664, IPR2016-00847, or IPR2016-00923. See, e.g., Nestle USA, Inc., v. Steuben
`
`Foods, Inc., IPR2014-01235, Paper 12 at 7 (PTAB 2014) (declining to deny
`
`petition under § 325(d) where petition relied on “combination of references
`
`
`
`12
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
`
`previously not considered and [was] supported by a declaration previously not
`
`considered”); see also Tandus Flooring, Inc. v. Interface, Inc., IPR2013-00333,
`
`Paper 16 at 6 (PTAB 2013) (declining to deny petition under § 325(d) where
`
`petitioner presented new declaration evidence).
`
`The arguments presented in the present petition could not have been
`
`presented in IPR2016-00923 because that filing sought joinder with already-
`
`instituted IPR2015-01944. When filing a petition with a motion to join, the
`
`conditions for joinder can be satisfied by filing substantively identical grounds. See
`
`Sony Corp. v. Memory Integrity, LLC, IPR2015-01353, Paper 11 at 4-6
`
`(determining that conditions for joinder were satisfied because grounds asserted
`
`were substantively identical to those instituted with same prior art, arguments, and
`
`evidence). Accordingly, Petitioner filed IPR2016-00923 on April 20, 2016 as a
`
`“copycat” petition. Because Petitioner sought a motion to join, Petitioner limited
`
`the grounds therein so that such petition maintained substantively identical grounds
`
`to the petition filed in IPR2015-01944 by Samsung.
`
`Moreover, the art and arguments in the present petition are not substantially
`
`the same as the IPR2016-00923. The IPR2016-00923 copycat petition relies upon
`
`Lambrecht, while the present petition is based on Bowes which is technology
`
`developed by Petitioner. Bowes aligns with the technology space alleged by Patent
`
`Owner to be infringed in the corresponding district court litigation (No. 2:15-cv-
`
`
`
`13
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`

`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
`
`00621-JRG-RSP (E.D. Tex.)).
`
`The prior art, combinations, arguments, and expert declaration testimony in
`
`the present petition are therefore different from that relied upon in IPR2016-00923
`
`filed previously by Petitioner. See, e.g., Valeo N. Am., Inc. v. Magna Elecs., Inc.,
`
`IPR2014-01206, Paper 13 at 11 (declining under § 325(d) to find the petitioners’
`
`art and arguments to be the same or substantially the same where the same
`
`petitioner had filed a prior petition against the same patent that was instituted and
`
`the present petition presented different combinations of prior art and arguments).
`
`Accordingly, because the instant petition presents new prior art and
`
`arguments, it falls outside of the scope of § 325(d).
`
`C. Claim Construction
`
`In inter partes review, the Board applies the broadest reasonable
`
`construction (BRI) in light of the specification to claims of an unexpired patent.
`
`See 37 C.F.R. § 42.100(b). Under BRI, claim terms are given their ordinary and
`
`accustomed meaning as would be understood by one of ordinary skill in the art in
`
`the context of the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249,
`
`1257 (Fed. Cir. 2007). However, patent claims, if expiring prior to a final decision
`
`by the Board, are typically construed by the standard applied in the district courts
`
`by applying the principles set forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed.
`
`Cir. 2005). See, e.g., 37 C.F.R. § 42.108(c). Under this standard, the claim terms
`
`
`
`14
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
`
`
`are given their ordinary and accustomed meanings as understood by one having
`
`ordinary skill in the art at the time of the invention in the context of the entire
`
`patent, considering intrinsic evidence, and extrinsic evidence to a lesser extent.
`
`Petitioner believes that the ’789 Patent would expire during pendency of the
`
`requested inter partes review proceeding. Nevertheless, the constructions proposed
`
`herein are consistent with both standards.
`
`i.
`
`“decoder”
`
`This claim term is found in claims 1-4, 6, 8, and 12-14, as well as in the
`
`detailed description.
`
`The ’789 Patent sets forth a special meaning for “decoder” as follows: “[t]he
`
`resulting bitstream is decoded by a video and/or audio decompression device
`
`(hereinafter decoder) ….” APPL1001, 1:48-51 (emphasis added). The ’789 Patent
`
`continues: “For ease of reference, a video and/or audio decompression and/or
`
`compression device 45 will hereinafter be referred to as decoder/encoder 45.” Id. at
`
`5:28-31. The decoder/encoder 45 is illustrated in FIG. 2 as including decoder 44
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`and encoder 46.
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`Based on the above, for the purposes of the invalidity analysis found in this
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`Petition, “decoder” means a video and/or audio decompression device. APPL1003,
`
`¶¶ 40-42.
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`ii.
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`“encoder”
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`This claim term is found in claims 5-7, as well as in the detailed description.
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`Similar to the “decoder” term, the ’789 Patent sets forth a special meaning for
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`“encoder” as follows: “[v]ideo and/or audio compression devices (hereinafter
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`encoders) ….” APPL1001, 1:46-48 (emphasis added). “For ease of reference, a
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`video and/or audio decompression and/or compression device 45 will hereinafter
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`be referred to as decoder/encoder 45.” Id. at 5:28-31. The decoder/encoder 45 is
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`illustrated in FIG. 2 as including decoder 44 and encoder 46.
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`Based on the above, for the purposes of the invalidity analysis found in this
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`Petition, “encoder” means a video and/or audio compression device. APPL1003,
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`¶¶ 43-45.
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`iii.
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`“real time”
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`This claim term is found in claims 1 and 13 and is also used in the detailed
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`description. The ’789 Patent does not define the term “real time” in the detailed
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`description. And, while the ’789 Patent describes conditions that it identifies as
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`important in supporting “real time” operation, these conditions do not provide
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`sufficient definiteness to articulate how “real time” should be construed. For
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`example: “[t]he decoder/encoder 45 is coupled to the memory 50 through devices,
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`typically a bus 70, that have a bandwidth greater than the bandwidth required for
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`the decoder/encoder 45 to operate in real time.” APPL1001, 6:29-32. “To operate
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`in real time the decoder/encoder 45 should decode[] … images fast enough so that
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`any delay in decoding … cannot be detected by a human viewer. … To operate in
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`real time the required bandwidth should be lower than the bandwidth of the bus.”
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`Id. at 6:41-53.
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`Despite the lack of definiteness in the specification, the Board previously
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`construed “real time” to mean pertaining to a data-processing system that controls
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`an ongoing process and delivers its outputs (or controls its inputs) not later than
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`the time when these are needed for effective control. APPL1012, p. 11. In related
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`district court proceedings, “real time” has been construed as “fast enough to keep
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`up with an input data stream.” APPL1013, pp. 20-24; APPL1014, pp. 18-25;
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`APPL1015, pp. 17-23.
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`Accordingly, for the purposes of the invalidity analysis found in this
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`petition, “real time” means pertaining to a data-processing system that controls an
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`ongoing process and delivers its outputs (or controls its inputs) not later than the
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`time when these are needed for effective control. APPL1003, ¶¶ 46-52.
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`iv.
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` “variable bandwidth”
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`This claim term is found in claim 2, but the detailed description does not
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`explicitly use this term. The ’789 Patent discusses a bus that has a sufficient
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`bandwidth to meet the decoder’s demands: “The decoder/encoder 45 is coupled to
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`the memory 50 through devices, typically a bus 70, that have a bandwidth greater
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`than the bandwidth required for the decoder/encoder 45 to operate in real time.”
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`APPL1001, 6:29-32 (emphasis added). The ’789 Patent continues: “A fast bus 70
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`is any bus whose bandwidth is equal to or greater tha[n] the required bandwidth.”
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`Id. at 6:58-60.
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`The ’789 Patent also mentions that the decoder does not always need access
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`to the memory, and when it does, the decoder does not always need the full
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`bandwidth of the bus:
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`[t]he decoder/encoder 45 only requires access to the memory during
`operation. Therefore, when there is no need to decode or encode, the
`first device 42, and any other devices sharing the memory 50 have
`exclusive access to the memory and can use the entire bandwidth of
`the fast bus 70. In the preferred embodiment, even during decoding
`and encoding the decoder/encoder 45 does not always use the entire
`required bandwidth.
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`Id. at 7:5-12. Thus, this term relates to a varying amount of need by one or more
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`devices (coupled to a shared bus) for placing data on, or receiving data from, the
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`bus. APPL1003, ¶ 56.
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`Accordingly, for the purposes of the invalidity analysis found in this
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`petition, “variable bandwidth” means a variable amount of data needed to be put
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`on, or received from, the shared bus by a device over periods of time. APPL1003,
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`¶¶ 53-57.
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`1.
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`Identification of How the Claims Are Unpatentable
`i. Challenge #1: Claims 1-5 and 12-14 are obvious under 35
`U.S.C § 103 over Bowes in view of TMS and Thomas
`Summary of Bowes
`(a)
`
`Bowes describes the components and operation of an arbitration scheme “for
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`
`
`
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`a computer system in which a digital signal processor resides on the computer
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`system’s memory bus without requiring a block of dedicated static random access
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`memory,” thereby reducing “system costs by eliminating the need for an expensive
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`block of SRAM.” APPL1005, Abstract; 6:22-25. Bowes teaches that the computer
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`system includes multiple “bus masters” coupled to a common memory bus. Id. at
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`2:52-3:2, 4:15-17.
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`
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`The examples given in Bowes of “bus masters” include “the CPU, the DSP,
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`the I/O interface and the NuBus controller.” Id. at 7:66-67. These devices are
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`illustrated in the computer system architecture of FIG. 2:
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`APPL1005, Fig. 2
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`
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`“[T]he present invention provides for the DSP 20 to reside on the system’s
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`memory bus and operate from the computer system’s main memory subsystem
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`14.” Id. at 6:22-25 (emphasis added).
`
`
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`Each bus master may, at some point, access the main memory subsystem 14
`
`illustrated in FIG. 2. A person having ordinary skill in the art (POSITA) would
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`recognize that any of the bus masters would have access to the shared main
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`memory subsystem 14 because of their respective access and control of the
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`common memory bus 110. APPL1003, ¶ 62.
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`A memory controller and arbiter (MCA) 200 arbitrates access for the bus
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`
`
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`masters according to a priority scheme. APPL1005, 7:64-8:10. According to
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`Bowes, “[t]he memory bus 110 provides the signal paths for the exchanging of
`
`data between the various elements on the memory bus. Further provided by the
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`memory bus are control lines for such things as bus requests and bus granting
`
`signals and other system level control signals” such as that are handled by the
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`memory controller and arbiter (MCA). Id. at 5:13-18.
`
`Bowes teaches that the arbitration is an adaptive scheme “that varies access
`
`to the memory bus as a function of time and depends upon what operations the
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`various bus masters are requesting.” Id. at 3:15-18. The scheme provides the DSP
`
`“with sufficient bandwidth to perform real-time digital signal processing using the
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`system’s dynamic random access memory (DRAM).” Id. at 4:55-58. Bowes
`
`teaches that to support the DSP’s real-time operations, the DSP may be “assigned 5
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`time slots among a total of 10 in the arbitration loop.” Id. at 8:44-45.
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`Bowes teaches that the DSP used for real-time operations (e.g., including
`
`image processing) can be a general-purpose DSP. Id. at 2:22-30. An example of a
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`general-purpose DSP is the TMS320C80 MVP that was produced by Texas
`
`Instruments, Inc., as described below. See APPL1003, ¶¶ 59-66.
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`Petition for Inter Partes Review of U.S. Patent No. 5,812,789
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`Summary of TMS320C8x System-Level Synopsis
`(b)
`TMS describes general-purpose DSP devices that perform video and audio
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`encoding/decoding, namely the “TMS320C8x,” which is a “generation of single-
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`chip multiprocessor digital signal processor (DSP) devices.” APPL1006, p. iii.
`
`This generation of single-chip multiprocessor DSPs includes the multimedia video
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`processor, or “MVP.” See id. at pp. iv-v. TMS teaches that the DSP device has a
`
`“high degree of on-chip integration” so that multiple devices (e.g., ASICs, RISC
`
`processors, DSPs, etc.) may be replaced by the ‘C8x device. Id. at p. SL:1-1.
`
`TMS teaches that the single-chip multiprocessor DSP may be used to
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`accelerate applications “such as video compression and decompression, image
`
`processing, and graphics manipulation.” Id. at p. A-6.1 Specifically, TMS teaches
`
`that the single-chip multiprocessor DSP may be used for moving picture experts
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`group (“MPEG”) video compression/decompression. Id. at p. A-5.
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`The single-chip multiprocessor DSP includes a small 50 KB on-board data
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`cache, divided into multiple dedicated caches. Id. at pp. SL:1-4, SL:2-4, SL:3-7-
`
`SL: