United States Patent [19]
`Thomas et al.
`
`[11] Patent Number:
`[45] Date of Patent:
`
`5,001,625
`Mar. 19, 1991
`
`364/ 200
`364/200
`
`‘
`
`3,810, l 14
`4,040,028
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`4,085,448
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`4,204,208
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`4,286,321
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`US. PATENT DOCUMENTS
`5/1974
`8/1977
`l/1978
`4/1978
`6/1978
`5/1980
`7/1980
`6/1981
`8/1981
`
`.
`
`[$4] BUS STRUCTURE FOR ()VERLAPPED DATA
`4,547,845 10/1985 Ross .......... ..
`TRANSFER
`4,554,627 11/1985 Holland et a1. .
`[75] Inventors: James H. Thomas; Roystou L. Smith, mm”? Ex4mi'1e"-Da"'id Y- Eng
`both of plantation, Fla‘; wmim p_
`Attorney, Agent. or Firm-Fleit, Jacobson, Cohn, Price,
`Ward, Poway, Calif.
`Holman 8‘ Stem
`ABSTRACT
`[73] Assignee: Gould lnc., Ft. Lauderdale, Fla.
`[57]
`[211 App], NO“. 173,212
`An improved system bus structure for versatile use in
`_
`various digital computer architecture con?gurations,
`Mu’ 24’ 1988
`[22] ?led:
`particularly those of mini-supercomputers, and, de
`[51] Int. (31.5 ............................................ .. G06F 13/40
`signed to support high speed. high reliability, Parallel
`[52] US. Cl. .................................. .. 364/200; 364/240;
`processing of bi-directional signal transfers in a multi
`364/240.2; 364/242.92
`port and multiple central processor unit (CPU) commu
`364/200 MS File, 900 MS File
`nication environment as between system bus units or
`[58] Field of Search
`[56]
`References and
`devices. The system bus structure may be sized for a
`compact encasement and may carry as many as 129
`simultaneous signals to and from various units’ con
`nected to it. The system'bus structure includes enabling
`structure for a centralized arbitration system, a central
`ized clock and synchronized transfer system, a central
`ized transfer monitor, a centralized parity error assessor
`and signalling system including transfer termination,
`and, a memory/inter-system inhibit system.
`
`Derchak .... ..
`
`Yamadat et al. _. ................. .. 364/200
`Pauker et a1.
`364/200
`364/200
`364/900
`Kogge
`364/200
`Mey ....... ..
`364/900
`McCarthy
`364/200
`.
`.
`Schmidt
`.. 364/200
`Yamamoto et a1.
`Baker ................................ ., 364/200
`
`11 Claims, 34 Drawing Sheets
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`Ex. 1007 / Page 26 of 51
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`Mar. 19, 1991
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`Mar. 19, 1991
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`Ex. 1007 / Page 29 of 51
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`

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`U.S. Patent
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`Mar. 19, 1991
`
`Sheet 29 of 34
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`Ex. 1007 / Page 30 of 51
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`

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`U.S. Patent
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`Mar. 19, 1991
`
`Sheet so of 34
`
`5,001,625
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`Ex. 1007 / Page 31 of 51
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`

`
`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 31 of 34
`
`5,001,625
`
`FIG. 23A
`
`Ex. 1007 / Page 32 of 51
`
`

`
`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 32 of 34
`
`5,001,625
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`Ex. 1007 / Page 33 of 51
`
`

`
`U.S. Patent
`
`Mar. 19,1991
`
`Sheet 33 of 34
`
`5,001,625
`
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`
`Ex. 1007 / Page 34 of 51
`
`

`
`U.S. Patent
`
`Mar. 19, 1991
`
`Sheet 34 of 34
`
`5,001,625
`
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`Ex. 1007 / Page 35 of 51
`
`

`
`1
`
`5,001,625
`
`BUS STRUCTURE FOR OVERLAPPED DATA
`TRANSFER
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`This application is related to applications for:
`"System For Monitoring and Capturing Bus Data In
`A Computer” to Smith et al. Ser. No. 173,222 filed on
`the same day as this application and assigned to the
`assignee of this application. The disclosure of the Smith
`et al. application is incorporated by reference herein;
`“Cache Memory with Interleaved Storage” to Ward
`et al. Ser. No. 173,405 filed on the same day as this
`application and assigned to the assignee of this applica-
`tion;
`“Advance Polling Bus, Arbiter for Use In Multiple
`Bus System" to Ward Ser. No. 173,211 filed on the same
`day as this application and assigned to the assignee of
`this application; and
`“Cache Memory Address Modifier For Dynamic
`Alteration of Cache Block Fetch Sequence” to Ward et
`al. Ser. No. 173,406 filed on the same day as this applica-
`tion and assigned to the assignee of this application.
`BACKGROUND OF THE INVENTION
`
`This improved system bus structure relates generally
`to computers, and more particularly,
`to system bus
`structures for parallel signal transfers between devices
`as in multi-application mini-supercomputer systems of
`the type including at least one general purpose system
`bus structure for carrying as many as 128 simultaneous
`signals to and from various units connected to the sys-
`tem bus.
`In the past those skilled in the art have achieved high
`performance parallel computational power, by using
`one or more architectural classes of supercomputers:
`pipelined computers, array processors, vector proces-
`sors and multiprocessor systems. A pipelined computer
`performs overlapped computations to exploit temporal
`parallelism, while an array processor uses multiple
`arithmetic/logic units to achieve spatial parallelism. A
`vector processor uses large vector registers to facilitate
`repetitive arithmetic operations on groups or vectors of
`numeric operands. A multiprocessor system has multi-
`ple instruction streams over a set of interactive proces-
`sors with shared raources (memories. databases. etc.).
`Each of the systems is designed to offer improved per-
`formance for particular applications over a non-pipe-
`lined single processor digital computer. but not in other
`applications. Furthermore, the expense of supercomput-
`ers is very high in terms of initial cost, maintenance. and
`space.
`There is a need for a lower cost computer having
`supercomputer capabilities and there is a further need
`for such a computer with a substantial capability to be
`utilized in many diverse applications.
`One of the most crucial impediments to improved
`performance of the super minicomputer has been the
`system bus structure design and methods for transfer-
`ring signals over the system bus structure. During the
`past few years, there have been a number of attempts to
`solve the problems associated with the methods of com-
`municating in rnulti-unit and multi-processor environ-
`ments, but, generally speaking, they have only solved
`limited problems in limited applications.
`For instance, U.S. Pat. No. 4,233,366 to Levy teaches
`a synchronous system bus structure that requires each
`
`20
`
`30
`
`45
`
`2
`of the system bus units connected to the system bus to
`sample each of the request signals and to conduct its
`own arbitration, rather than to have a centralized arbi-
`tration and control unit. and further does not discuss
`any enablement for a system network.
`The instant assignee and its predecessor in interest
`have produced and sold a digital computer having a
`system bus structure with a two-board design, referred
`to as the Concept series, which transferred data as 32-bit
`words but lacked the capability of transferring 64 or
`I28-bit words at one time. The prior Concept comput-
`ers also employed independent unit arbitration rather
`than centralized arbitration.
`Accordingly, there is a need for a system bus struc-
`ture for use in a variety of inexpensive mini-supercom-
`puter architectures including diverse applications and
`that is designed to support high speed, high reliability,
`parallel processing of bi-directional 64 and 128-bit sig-
`nal transfers in a multi-port and multiple central proces-
`sor unit (CPU) environment.
`SUMMARY OF THE INVENTION -
`
`A system bus structure includes up to seven ports for
`each of a pair of CPUs; a controller port including lines
`for centralized clock distribution and centralized arbi-
`tration or access to the bus lines; three inter-system bus
`link (ISBL) ports for linking up to four system bus
`structures into a system network; a' snapshot port for
`including a means for monitoring bus transfers, testing
`transfers for parity, and issuing parity error signals; a
`substantial number of general ports for connection of
`various bus units, such as a System Integrated Memory
`(SIM) unit, a Universal
`Input/Output Microengine
`(UIOM) unit, and, an Intelligent Peripheral Interface
`(IPI) unit, depending on the desired computer architec-
`ture.
`The system bus is organized into a total of forty-two
`general ports or bus ports. Each general port is com-
`prised of a primary port and a secondary port. Two of
`the ports are dedicated to the bus controller unit and’
`bus snapshot unit, and 14 others are reserved for the
`CPU board sets. The rest of the ports, referred to as
`general ports and comprising a primary port and a sec-
`ondary port pair, are for the memory boards, ISBLs,
`and Ul0Ms.
`The bus structure is organized into several major
`fields of multiple lines which carry message and data
`transfers, and control signals for intra and inter-system
`control. These fields include the memory address bus,
`data bus, expanded data bus, and individual control
`signals bus. Parity bits are associated with address and
`data bus fields.
`A primary object of the present invention is to pro-
`vide a system bus structure which can support a high
`speed, low cost mini-supercomputer with supercom-
`puter capabilities.
`A further object of the present invention is to provide
`a system bus structure which can support a high speed,
`low cost mini-supercomputer capable of being utilized
`on many diverse applications.
`A further object of the instant invention is to provide
`a system bus structure that supports high speed, high
`reliability. parallel processing of bi-directional signal
`transfers in a rnulti-port and multiple central processor
`unit (CPU) communication environment.
`A further object of the present invention is to provide
`a system bus structure that may carry as many as 128
`
`Ex. 1007 / Page 36 of 51
`
`

`
`3
`simultaneous word signals to and from various units
`connected to it.
`A further object of the present invention is to provide
`a system bus structure that is operable with a central-
`ized arbitration system.
`A further object of the present invention is to provide
`‘a system bus structure that is operable with a central-
`ized clock and synchronized transfer system
`A further object of the present invention is to provide
`a system bus structure that is operable with a central-
`ized transfer monitor and a centralized parity error
`assessor and signalling system.
`A further object of the present invention is to provide
`a system bus structure that is operable with a memory-
`/inter-system inhibit system.
`A further object of the present invention is to provide
`a method for transferring information between a pair of
`system units connected to the system bus structure.
`Other objects and uses of the present invention will
`become obvious to one skilled in the art upon a perusal
`of the specification and claims in light of the accompa-
`nying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a plan view of a system bus structure em-
`bodying the present invention and including a plurality
`of signal processing lines and a preferred digital com-
`puter architecture;
`FIG. 2 is a block diagram View of the preferred multi- _
`processor digital computer architecture of FIG. 1 in-
`cluding the system bus tructure;
`FIG. 3 is an isolation view, in partial cutaway, of a
`port side of a backplane incorporated as part of the
`system bus structure of FIG. 1 and displaying a primary
`port, a secondary port, and, a CPU port including a slot
`and a pin configuration;
`FIG. 4 is a timing diagram displaying a latch signal
`and a trigger clock signal, a plurality of related signals,
`and corresponding clock signal cycles over which bus
`transfer operations are distributed.
`FIG. 5 is a more detailed timing diagram of the latch
`signals and trigger clock signals of FIG. 4;
`FIG. 6 is a broad plan View showing the location of
`the system bus structure of FIG. 6 in a rearward loca-
`tion of a mini-supercomputer housing or casing having
`a width of less than thirty inches and showing in block
`form a plurality of power connections for the system
`bus structure from the casing;
`FIG. ‘I is a representation of a plurality of serial bus
`signals including a plurality of fields into which the
`plurality of serial bus signals are organized for a serial
`bus transfer;
`FIG. 8 is a representation of the main and expanded
`data bus transfer fields including the addressable fields;
`FIG. 9 is a representation of the various bus fields for
`bus transfers on the system bus structure.
`FIG. 10 is a block diagram of the logic of the bus
`arbiter on the bus control board shown in FIG. 1;
`FIG. 11A and 11B are logic diagrams of a portion of
`a request in logic module of the bus arbiter of FIG. 10;
`FIG. 12A and 12B are logic diagrams of a portion of
`the request in logic of the bus arbiter of FIG. 11;
`FIG. 13A and 13B are logic diagrams of portion of
`the request in logic;
`FIG. MA and 14B are logic diagrams of a portion of
`the request comparator logic of FIG. 10,
`FIG. ISA and 15B are logic diagrams of a portion of
`the logic of the request comparator;
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`5,001,625
`
`4
`FIG. 16A and 16B are logic diagrams of a portion of
`the logic of the request comparator;
`FIG. 17A and 17B are logic diagrams of a portion of
`the logic of the request comparator;
`_
`FIG. 18A and 18B are logic diagrams of a portion of
`the logic of the bus select unit of FIG. 10;
`FIG. 19A and 19B are logic diagrams of a portion of
`the logic of the bus select logic;
`FIG. 20A and 20B are logic diagrams of a portion of
`the bus select logic;
`FIG. 21A and 21B are logic diagrams of a portion of
`the bus select logic.
`FIG. 22A and 22B are logic diagrams of a portion of
`the bus select logic;
`FIG. 23A and 23B are logic diagrams of a portion of
`the bus select logic; and
`FIG. 24A and 2413 are logic diagrams of the bus link
`priority unit of FIG. 10.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`
`Referring now to the drawings and especially to FIG.
`1, a mini-supercomputer 10 includes a high speed sys-
`tem bus stnicture embodying the present invention is
`shown therein and is generally identified by numeral
`101. As may best be seen in FIGS. 1 and 2, a plurality of
`system bus units generally referenced by numeral 215 is
`connected to the system bus structure 101 by attach-
`ment of said units 215 to respective desired ports. and,
`particularly designed to support high speed, high reli-
`ability, parallel processing of bi—directional signal trans-
`fers in a multi-port and multiple central processor unit
`(CPU) environment communication as between system
`bus units or devices 215. One embodiment of a system
`bus architecture 100 utilizing the system bus structure
`101 as contemplated is shown in FIGS. 1 and 2. This
`embodiment comprises a first Vector Processing Cen-
`tral Processing Unit (CPU) 201 connected to up to
`seven ports respectively numbered 01-07, three Inter-
`System Bus Link Units (ISBLs) respectively numbered
`221, 231 and 241 connected to ports, respectively num-
`bered 19. 23 and 25, a bus controller unit 251 connected
`to a port 20, a snapshot unit 261 connected to a port, and
`a second Vector Processing Central Processing Unit
`(CPU) 211 connecting to up to seven ports respectively
`numbered 36-42. A number of additional general ports
`08-17 and 26-35 are provided for connection of other
`system bus units 215. such as a System Integrated Mem-
`ory (SIM) unit, a Universal Input/Output Microengine
`(UIOM) unit. and an Intelligent Peripheral Interface
`(IPI) unit.
`Up to three Intu-System Bus Link Units 221, 231 and
`241 may be connected to a given system bus structure
`101 in order to provide a means for developing a system
`network. A system network is created by connecting a
`given ISBL from a first system bus structure 101 to a
`second ISBL from a second system bus structure 101.
`By creating this interconnection of system bus struc-
`tures 101, the various system bus units 215 from the first
`system bus stnrcture 101 may communicate with vari-
`ous system bus units 215 from the second system bus
`structure 101. The result is that the overall memory
`space of one system bus architecture 100 utilizing the
`system bus structure I01 may be doubled, tripled, or
`increased four-fold with up to four system bus struc-
`tures 101 inter-connected into a system network.
`The system bus structure 101 includes several sets of
`multiple lines, buses or bus lines, referred to generally
`
`Ex. 1007 / Page 37 of 51
`
`

`
`5
`by numeral 121, which may be implemented onto a
`backplane 119 as with external layer printed wiring
`having an unloaded characteristic impedance of approx-
`imately 50 ohms. The major buses 121 include a main
`system bis 141, a main data bus 103, an expanded data
`bus 145, a serial bus 147. and, a plurality of intraport
`busses 149.
`The main system bus 141 is comprised of one hundred
`eleven lines organized into several major fields of multi-
`ple lines, the signals of which are separately interpret-
`able for providing desired message transfer characteris-
`tics under which the syst bus structure 101 operates
`and is discussed more particularly hereinafter. The main
`system bus 141 also includes a number of control signal
`lines which carry individual control signals used for
`general system control including global stop request,
`power fail, and stop clock lines.
`The main data and expanded data busses 14-3 and 145
`are comprised, respectively, of seventy-two indepen-
`dent lines and include various fields which are sepa-
`rately interpretable for providing data information to
`the various system bus units 215.
`The serial bus 147 is comprised of two independent
`lines. Information carried on the serial bus is organized
`serially into a plurality of control and data fields which
`are separately interpretable for soft loading system bus
`units 215 as with control store information in the form
`of firmware and control or parameter settings.
`Each intraport bus 149 is comprised of one hundred
`independent lines connecting a pair of primary and
`secondary ports respectively numbered 161 and 171.
`Each intraport bus 149 is device dependent and pro-
`vides a data/control transmission path between each
`pair of primary and secondary ports 161 and 171.
`Referring particularly to FIG. 3,
`the system bus
`structure 101 includes a series of 42 ports, referred to
`generally by numeral 151, which are physically located
`in parallel along the baclrplane 119 and are selectively
`connected in parallel to the various bus lines 121 in
`order to provide a means for interconnection of system
`bus units 215 to the system bus structure 101 and en-
`abling inter-communication of system bus units 215 by
`means of the bus lines 121. The ports 151 include a
`plurality of general bus ports 153, a controller port 155,
`a snapshot port 157, and two groups of CPU ports 159 45
`as may best be seen in FIG. 1. It should be noted that the
`controller port 155 and the snapshot port 157 are not
`identical to the general bus ports 153 or the CPU ports
`159.
`Each of the general bus ports 15 is comprised of a pair
`of ports. previously referred to as the primary port 161
`and the secondary port 171, and is used as a general
`purpose location for peripheral bus units 215, such as
`memories, Inter-System Bus Links, and Universal In-
`put/Output Microengines. The primary and secondary
`ports 161 and 171 of a given general port 153 are to be
`connected to a primary board and a secondary board of
`the selected system bus unit 215. A primary board of a
`selected system bus unit 215 mates with a selected pri-
`mary port 161 in perpendicular relation to the back-
`plane 119 and is thereby connected to the main system
`bus 141. The secondary board of the same system bus
`unit 215, if there is one, mates with the secondary port
`171, corresponding to the selected primary port 161. in
`perpendicular relation to the bacltplane 119 and is
`thereby connected to the main and expanded data bus-
`ses 143 and 145. The intraport bus 149 associated with
`the selected general port connects the primary board
`
`55
`
`5,001,625
`
`6
`and the secondary board of the system bus unit 215 in
`parallel and series relation at each of the one hundred
`independent lines of the intraport bus 149. and provides
`a communication path by which data and system infor-
`mation may be transferred freely within a particular
`system bus unit 215.
`From the foregoing. it can be seen that the system bus
`structure 101 comprises the system bus units 215 attach-
`ing to the general ports as comprising sets of two
`boards: a primary board for receipt and processing of
`system and control information from the main system
`bus, and, a secondary board for receipt of data informa-
`tion from the main and expanded data buses and cooper-
`ating with the primary board in the processing of data
`information in accordance with the system and control
`information.
`The controller port 155 is used for connecting other
`system units to a bus controller and clock signal genera-
`tor unit or bus arbiter 251, also known as a K-board,
`which arbitrates transfers over the system bus structure
`101. The bus controller and clock signal generator unit
`251 has timing means, such as clock distribution cir-
`cuitry by which transfers are synchronized. and pro-
`vides bus request/select or priority arbitration logic
`means, such as circuitry for determining priority of
`other system bus units asserting bus access requests.
`A snapshot port 157 is used for connecting a snapshot
`unit 261 which affords a means of monitoring process-
`ing activity.
`Each of the primary, secondary, controller, and snap-
`shot ports. 161, 171, 155 and 157, are comprised of four
`(4) slots 173, 175, 177 and 179 with three (3) rows A, B,
`C of 32 pins per slot, otherwise known as 96 DIN pin
`and socket connectors. While each of the CPU ports
`159 are comprised of two (2) slots 183, 185, with four (4)
`rows A, B. C. D of 96 pins, however, the specific con-
`nectors used for the CPU slots may vary according to
`the processor type. For all slots and configurations. a
`plurality of male pins 181 are installed in the backplane
`to facilitate ease of repair should a given pin 181 become
`damaged.
`The pins 181 are connected to mating portions of
`various system bus units 215, or printed circuit boards.
`for purposes of accommodating transfers of bits of in-
`formation or instructions. A corresponding pin 181 of
`each primary, secondary, snapshot, and series of CPU
`ports 16], 171, 157. and 159 is connected in parallel with
`each of the one hundred eleven lines of the main system
`bus 141, facilitating the transfer of control information
`and instructions. Several of the pins 181 of the control-
`ler port 155 are connected to a corresponding number
`of lines of the main system bus 141, controlling system
`bus transfers
`'
`A corresponding pin 181 of each secondary port 171
`is connected in parallel with each of the seventy-two
`lines of the main data bus 143 and the seventy-two lines
`of the expanded data bus 145, facilitating the transfer of
`standard 64-bit or expanded 128-bit data transfers.
`A corresponding pin 181 of each primary port, snap-
`shot, controller, and the CPU port for the micros-
`tore/instmmentation unit 157, 155 and 159 is connected
`in parallel with each of the two lines of the serial bus
`147, facilitating the transfer of serial data, instructions,
`and information.
`A corresponding pin 181 of each pair of primary and
`secondary ports 161 and 171 is connected in parallel
`with each of the one hundred lines of a corresponding
`set of the intraport bus 149, facilitating the intra-system
`
`Ex. 1007 / Page 38 of 51
`
`

`
`7
`bus unit communication of the primary and secondary
`boards of a system bus unit 215.
`A number of pins 181 are provided for supplying the
`necessary power requirements of the system bus units
`215. Each type of port 151 and 159 has its power/-
`ground pins uniquely distributed.
`A numerical breakdown of the pin 181 assignments of
`' each general port 153 is provided in the following table:
`
` —.j.1:
`PIN BREAKDOWN OF GENERAL PORTS:
`
`PRIMARY SLOT PINS
`4 Each 96 Pin Connectors
`384
`Ground
`145
`—-5.2 V
`23
`-2.0 V
`+ 5.0 VA
`+5.0 VB
`Clock Pins
`System Bus & Controls
`Serial Bus
`lntraport Bus
`Space Pins (not bussed)
`Space Pins (bussai)
`SECONDARY SLOT
`4- Ech 96 Pin Connectors
`Ground
`— 5.2 V
`- 2.0 V
`+ 5.0 VA
`+ 5.0 VB
`Clock Pins
`Main Data Bus
`Expanded Data Bus
`lntrnport Bus
`Space Pins (not busted)
`
`35
`
`In addition to the pins associated with the bus lines 121
`as previously discussed, the table fiirther reflects vari-
`ous power pins necessary for providing power to the
`various circuit elements on a given system bus unit 215.
`FIG. 6 further shows a backplane in schematic form as
`integrating into a mini-supercomputer cabinet with
`corresponding power outlets from the cabinet to supply
`to the backplane pins as designated.
`The system bus structu