TMS320C8x
`System-Level
`Synopsis
`
`SPRU113B
`September 1995
`
`Printed on Recycled Paper
`
`Apple Inc. v. Parthenon
`Ex. 1006 / Page 1 of 75
`
`

`
`IMPORTANT NOTICE
`
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`
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`applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality
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`Specific testing of all parameters of each device is not necessarily performed, except those
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`
`Certain applications using semiconductor products may involve potential risks of death,
`personal injury, or severe property or environmental damage (“Critical Applications”).
`
`TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
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`OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
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`
`Copyright  1995, Texas Instruments Incorporated
`
`Ex. 1006 / Page 2 of 75
`
`

`
` About This Manual
`
`Preface
`
`Read This First
`
`About This Manual
`
`The TMS320C8x is Texas Instruments’ first generation of single-
`chip multiprocessor digital signal processor (DSP) devices. A
`single ’C8x contains up to five powerful, fully programmable pro-
`cessors: a master processor (MP) and up to four parallel proces-
`sors (PPs). The MP is a 32-bit RISC (reduced instruction set
`computer) processor with an
`integral, high-performance
`IEEE-754 floating-point unit. Each PP is a 32-bit advanced DSP
`that combines capabilities similar to those of conventional DSPs
`with advanced features to accelerate operation on a variety of
`data types.
`
`The ’C8x supports a variety of parallel-processing configura-
`tions, which facilitate a wide range of multimedia and other
`applications that require high processing speeds. Applications
`include image processing, two-dimensional, three-dimensional,
`and virtual reality graphics, digital audio and video compression,
`and telecommunications.
`
`This manual describes the ’C8x’s features, architecture, and de-
`velopment environment.
`
` Read This First
`
`iii
`
`Ex. 1006 / Page 3 of 75
`
`

`
`Related Documentation From Texas Instruments
`
`Related Documentation From Texas Instruments
`
`The following books describe the TMS320C8x and related sup-
`port tools. To obtain a copy of any of these TI documents, call the
`Texas
`Instruments
`Literature Response Center
`at
`(800) 477–8924. When ordering, please identify the book by its
`title and literature number.
`TMS320C80 Multimedia Video Processor Data Sheet
`(literature number SPRS023) describes the features of the
`’C80 device and provides pinouts, electrical specifications,
`and timings for the device.
`
`TMS320C80 (MVP) C Source Debugger User’s Guide (litera-
`ture number SPRU107) describes the ’C8x master proces-
`sor and parallel processor C source debuggers. This manual
`provides information about the features and operation of the
`debuggers and the parallel debug manager; it also includes
`basic information about C expressions and a description of
`progress and error messages.
`
`TMS320C80 (MVP) Code Generation Tools User’s Guide (lit-
`erature number SPRU108) describes the ’C8x code genera-
`tion tools. This manual provides information about the
`features and operation of the linker and the master proces-
`sor (MP) and parallel processor (PP) C compilers and
`assemblers. It also includes a description of the common
`object file format (COFF) and shows you how to link MP and
`PP code.
`
`TMS320C80 (MVP) Master Processor User’s Guide (literature
`number SPRU109) describes the ’C8x master processor
`(MP). This manual provides information about the MP
`features, architecture, operation, and assembly language
`instruction set; it also includes sample applications that
`illustrate various MP operations.
`
`TMS320C80 (MVP) Multitasking Executive User’s Guide
`(literature number SPRU112) describes the ’C8x multitask-
`ing executive software. This manual provides information
`about the multitasking executive software features, opera-
`tion, and interprocessor communications; it also includes a
`list of task error codes.
`
`iv
`
`TMS320C8x System-Level Synopsis
`
`Ex. 1006 / Page 4 of 75
`
`

`
` Related Documentation From Texas Instruments / If You Need Assistance
`
`TMS320C80 (MVP) Parallel Processor User’s Guide (litera-
`ture number SPRU110) describes the ’C8x parallel proces-
`sor (PP). This manual provides information about the PP
`features, architecture, operation, and assembly language
`instruction set; it also includes software applications and op-
`timizations.
`
`TMS320C80 (MVP) Transfer Controller User’s Guide (litera-
`ture number SPRU105) describes the ’C80 transfer control-
`ler (TC).This manual provides information about the TC
`features, functional blocks, and operation; it also includes
`examples of block write operations for big- and little-endian
`modes.
`
`TMS320C80 (MVP) Video Controller User’s Guide (literature
`number SPRU111) describes the ’C80 video controller (VC).
`This manual provides information about the VC features,
`architecture, and operation; it also includes procedures and
`examples for programming the serial register transfer (SRT)
`controller and the frame timer registers.
`
`TMS320C80 to TMS320C82 Software Compatibility User’s
`Guide (literature number SPRU154) describes program-
`ming differences in the ’C80 and the ’C82.
`
`If You Need Assistance...
`
`If you want to. ..
`Request more
`information about Texas
`Instruments Digital
`Signal Processing
`(DSP) products
`Order Texas Instruments
`documentation
`Ask questions about
`product operation or
`report suspected
`problems
`Report mistakes in this
`document or any other TI
`documentation
`
`Do this. . .
`Write to:
`Texas Instruments Incorporated
`Market Communications Manager, MS 736
`P.O. Box 1443
`Houston, Texas 77251–1443
`Call the TI Literature Response Center:
`(800) 477–8924
`Call the DSP hotline:
`(713) 274–2320
`FAX: (713) 274–2324
`
`Fill out and return the reader response card at
`the end of this book, or send your comments to:
`Texas Instruments Incorporated
`Technical Publications Manager, MS 702
`P.O. Box 1443
`Houston, Texas 77251–1443
`Electronic mail: comments@books.sc.ti.com
`
` Read This First
`
`v
`
`Ex. 1006 / Page 5 of 75
`
`

`
`Trademarks
`
`Trademarks
`
`Windows NT is a trademark of Microsoft Corporation.
`
`EPIC is a trademark of Texas Instruments Corporation.
`
`vi
`
`TMS320C8x System-Level Synopsis
`
`Ex. 1006 / Page 6 of 75
`
`

`
` Running Title—Attribute Reference
`
`Contents
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:1-1
`1 Overview of the TMS320C8x
`Provides an overview of the TMS320C8x and the TMS320 family and de-
`scribes the TMS320C8x development environment.
`1.1 What Is the TMS320C8x?
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`1.1.1
`The TMS320 Family
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`1.1.2 Key features of the TMS320C8x
`. . . . . . . . . . . . . . . . . . . . . .
`1.2 Why Should I Use the TMS320C8x?
`. . . . . . . . . . . . . . . . . . . . . . . . .
`1.3
`Typical Applications
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`1.4
`The TMS320C8x Development Environment
`. . . . . . . . . . . . . . . . . .
`
`SL:1-2
`SL:1-3
`SL:1-4
`SL:1-6
`SL:1-8
`SL:1-9
`
`. . . . . . . . . . . . . . . . . . . . . . .
`SL:2-1
`2 Multiprocessing and System Architecture
`Describes the TMS320C8x architecture, including the TMS320C8x processors
`and controllers.
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`2.1
`Architecture Overview
`SL:2-2
`2.2
`The Master Processor (MP)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:2-5
`2.3
`The Parallel Processors (PPs)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:2-7
`2.4
`The Transfer Controller (TC)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:2-9
`2.4.1 Memory Interfacing
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:2-10
`2.4.2 Dynamic Bus Sizing
`SL:2-10
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`2.4.3 Memory Configuration Caching (TMS320C82 only)
`SL:2-10
`. . . .
`2.4.4 Packet Transfers
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:2-11
`2.4.5 Externally-Initiated Packet Transfers (XPTs)
`SL:2-11
`. . . . . . . . . .
`The Video Controller (VC) (TMS320C80 only)
`. . . . . . . . . . . . . . . .
`SL:2-12
`The Multitasking Executive Software
`. . . . . . . . . . . . . . . . . . . . . . . .
`SL:2-14
`
`2.5
`2.6
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`3 The TMS320C8x Memory Organization
`Describes the TMS320C8x’s 4-GB memory space.
`. . . . . . . . . . . .
`3.1
`Overview of the TMS320C8x Memory Organization
`3.2
`On-Chip Memory Organization
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`3.2.1 MP Data Caches
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`3.2.2 MP Instruction Cache
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`3.2.3 PP Instruction Caches
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`3.2.4 Data and Parameter RAM Organization
`. . . . . . . . . . . . . . .
`
`SL:3-1
`
`SL:3-2
`SL:3-7
`SL:3-8
`SL:3-8
`SL:3-9
`SL:3-9
`
` Chapter Title—Attribute Reference
`
`vii
`
`Ex. 1006 / Page 7 of 75
`
`

`
`Contents
`
`3.3
`
`3.4
`
`3.5
`
`. . . . . . . . . . . . . . . . . . . . . . . . .
`Accessing Memories and Registers
`3.3.1 On-Chip RAM Accesses
`. . . . . . . . . . . . . . . . . . . . . . . . . . . .
`3.3.2 Other On-Chip Accesses
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`3.3.3 Accessing External Memory
`. . . . . . . . . . . . . . . . . . . . . . . .
`Direct External Memory Access (DEA)
`. . . . . . . . . . . . . . . . . . . . . .
`3.4.1 Master Processor DEAs
`. . . . . . . . . . . . . . . . . . . . . . . . . . . .
`3.4.2 Parallel Processor DEAs
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`Endian Mode
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`SL:3-10
`SL:3-10
`SL:3-10
`SL:3-11
`SL:3-12
`SL:3-12
`SL:3-13
`SL:3-14
`
`SL:4-1
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`4 The Crossbar
`Describes the crossbar and how messages are sent and prioritized.
`4.1
`Overview of the Crossbar
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:4-2
`4.2
`Crossbar Connections
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:4-3
`4.3
`Crossbar Operation
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:4-5
`4.4
`Crossbar Access Decisions
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:4-7
`4.5
`Resolving Crossbar Contention
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:4-9
`4.6
`Interprocessor Communication
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:4-10
`4.6.1 Processor/Controller Select Bits
`SL:4-12
`. . . . . . . . . . . . . . . . . . . . .
`4.6.2 Command Select Bits
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:4-13
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`A Glossary
`Defines acronyms and key terms used in this book.
`
`A-1
`
`viii
`
`TMS320C8x System-Level Synopsis
`
`Ex. 1006 / Page 8 of 75
`
`

`
` Running Title—Attribute Reference
`
`Figures
`
`. . . . . . . . . . . . . . . . . . . . . .
`TMS320 Family of Programmable Devices
`1–1
`SL:1-3
`Typical TMS320C8x Applications
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`1–2
`SL:1-8
`The TMS320C8x Development Tools
`. . . . . . . . . . . . . . . . . . . . . . . . . . .
`1–3
`SL:1-9
`TMS320C80 Block Diagram
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`2–1
`SL:2-2
`TMS320C82 Block Diagram
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`2–2
`SL:2-3
`2–3 Master Processor Block Diagram
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:2-6
`2–4 Parallel Processor Block Diagram
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:2-8
`2–5
`TMS320C8x Transfer Controller Block Diagram
`. . . . . . . . . . . . . . . . . .
`SL:2-9
`2–6 Video Controller Block Diagram
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:2-13
`3–1
`TMS320C80 Memory Map
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:3-3
`3–2
`TMS320C82 Memory Map
`SL:3-5
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`3–3 Data Order in Big-Endian Mode
`SL:3-14
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`3–4 Data Order in Little-Endian Mode
`SL:3-15
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`4–1 Pipeline Operation for RAM Write Accesses Over the Crossbar
`SL:4-5
`. . . .
`4–2 Pipeline Operation for RAM Read Accesses Over the Crossbar
`SL:4-6
`. . . .
`4–3 Crossbar Access Priority
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`SL:4-7
`4–4 Round-Robin Token Passing Order
`SL:4-8
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`4–5 Command Word for Interprocessor Communication (’C8x)
`SL:4-10
`. . . . . . . .
`
` Contents
`
`ix
`
`Ex. 1006 / Page 9 of 75
`
`

`
`
`
`Chapter 1
`
`Overview of the TMS320C8x
`
`The TMS320C8x digital signal processor (DSP) is a single-chip,
`multiprocessor device for use in image processing, two-dimen-
`sional, three-dimensional/virtual-reality graphics, audio/video
`digital compression, and many other applications. The ’C8x of-
`fers the power to support applications in the security, image rec-
`ognition, digital telecommunications, and other markets.
`
`The ’C8x architecture’s high degree of on-chip integration allows
`you to replace multiple ASICs, RISC processors, DSPs, and their
`corresponding SRAM and interface chips with one or more ’C8x
`devices.
`
`Topics
`
`1.1
`1.2
`1.3
`1.4
`
`. . . . . . . . . . . . . . . . . . . . . .
`What Is the TMS320C8x?
`Why Should I Use the TMS320C8x?
`. . . . . . . . . . . .
`Typical Applications
`. . . . . . . . . . . . . . . . . . . . . . . . . .
`The TMS320C8x Development Environment
`. . . .
`
`SL:1-2
`SL:1-6
`SL:1-8
`SL:1-9
`
` Chapter Title—Attribute Reference
`
`SL:1-1
`
`Ex. 1006 / Page 10 of 75
`
`

`
`What Is the TMS320C8x?
`
`1.1 What Is the TMS320C8x?
`The TMS320C8x integrates several components onto a single chip:
`- Up to five powerful, fully programmable processors
`
`- Up to 50 KB of SRAM
`- An intelligent DMA (direct memory access) controller with a di-
`rect external interface to DRAM, SDRAM, SRAM, and VRAM
`
`Versions of the ’C8x are capable of performing the equivalent of
`over two billion RISC-like operations per second (BOPS). In
`some applications, one ’C8x can do the job of over ten of the most
`powerful DSPs or general-purpose processors. During each se-
`cond of processing, the ’C80 can move up to 2.4 GB of on-chip
`data, up to 1.8 GB of on-chip instructions, and up to 400 MB of
`data to off-chip memory.
`
`The ’C8x architecture contains up to four parallel processors and
`one master processor. The master processor (MP) is a 32-bit
`RISC (reduced instruction set computer) with an integral
`IEEE-754 floating-point unit. The MP’s general-purpose proces-
`sing capabilities make it ideal for coordinating on-chip processing
`activities and for communicating with external devices.
`
`Each parallel processor (PP) is an advanced 32-bit DSP. In addi-
`tion to having the processing capabilities of conventional DSPs,
`a PP has special features to speed up operations on image data
`and to accelerate applications that manipulate data organized
`into bit fields. A PP’s wide instruction word, three-operand arith-
`metic logic unit (ALU), and single-cycle multiplier enable it to per-
`form a number of RISC-like operations in a single clock cycle.
`
`Communication between the MP and PPs takes place over a
`high-speed crossbar network that provides simultaneous access
`to multiple banks of on-chip RAM. Software tools allow you to
`write programs in C and assembly language for the MP and PPs.
`
`In addition to the fully programmable processors, the chip con-
`tains an intelligent DMA controller, called the transfer controller
`(TC). The TC manages all memory traffic by performing several
`services. One service takes the form of packet transfers that
`move data between two memory regions. Some packet transfers
`are complex programmable byte-aligned array transfers that in-
`volve XY or linear addressing of a source or destination array.
`
`To provide on-chip storage, the ’C80 offers 50 KB of SRAM and
`the ’C82 offers 44 KB of SRAM. On-chip RAM, with the exception
`of the caches, is shared among the processors to support a vari-
`ety of parallel-processing configurations.
`
`SL:1-2
`
`TMS320C8x System-Level Synopsis
`
`Ex. 1006 / Page 11 of 75
`
`

`
` What Is the TMS320C8x?
`
`This unique combination of processing hardware facilitates a
`wide range of DSP applications that demand high processing
`speeds.
`
`1.1.1 The TMS320 Family
`
`The TMS320C8x generation is the flagship in the TMS320 family
`of DSPs. The family’s scalable architecture allows Texas Instru-
`ments to offer a variety of devices at various cost and perfor-
`mance points. Eight generations make up the TMS320 family:
`
`- The ’C1x, ’C2x, ’C2xx, C5x, and ’C54x generations offer a
`complete line of general-purpose and application-specific fix-
`ed-point DSPs.
`
`- The ’C3x and ’C4x generations provide an ensemble of floa-
`ting-point DSPs.
`
`- The ’C8x generation offers multiprocessing capabilities.
`
`Figure 1–1 illustrates the TMS320 family of devices.
`
`Figure 1–1. TMS320 Family of Programmable Devices
`
` Overview of the TMS320C8x
`
`SL:1-3
`
`Ex. 1006 / Page 12 of 75
`
`

`
`What Is the TMS320C8x?
`
`The TMS320 family has grown from a single device introduced
`in 1982, the TMS32010, to over thirty different products across
`six CPU architectures. On-chip hardware multipliers, register
`files, barrel shifters, ALUs, ROMs, RAMs, caches, and I/O pe-
`ripherals, along with massive internal buses, all within a product
`as programmable as a general-purpose microprocessor, make
`TMS320 devices ideal for a broad range of computation-inten-
`sive applications.
`
`1.1.2 Key features of the TMS320C8x
`
`The high-performance ’C8x architecture offers several key fea-
`tures:
`
`- Versions capable of over two billion operations per second
`(BOPS)
`
`- 40 or 50 MHz performance
`
`- A 32-bit RISC master processor with an integrated IEEE-754
`floating-point unit
`
`- Multiple 32-bit parallel processors (advanced DSPs) with
`64-bit instruction words
`J Four parallel processors in the ’C80
`J Two parallel processors in the ’C82
`
`- 50 KB of on-chip RAM on the ’C80 and 44 KB of on-chip RAM
`on the ’C82
`
`- An on-chip crossbar that allows multiple instruction fetches and
`parallel data accesses during each cycle to support high trans-
`fer rates:
`J up to 4.2 GB/s transfer rates on the ’C80
`J up to 2.6 GB/s on the ’C82
`
`- Big-endian and little-endian byte-ordering modes
`
`- A 4-Gbyte memory address space
`
`- A 64-bit transfer controller capable of up to 400 MB/s in on-
`chip and off-chip memory transfers
`J Dynamic sizing of bus width for 64, 32, 16, or 8 bits
`J Access to 64-bit VRAM/DRAM/SDRAM/SRAM memory
`
`- A video controller that contains dual frame timers for simulta-
`neous image capture and display (TMS320C80 only)
`
`- Four external interrupts (three edge-triggered and one level-
`triggered)
`
`SL:1-4
`
`TMS320C8x System-Level Synopsis
`
`Ex. 1006 / Page 13 of 75
`
`

`
` What Is the TMS320C8x?
`
`- A full-scan design (plus boundary scan), accessed via an
`IEEE1149.1-compliant test port that provides emulation sup-
`port
`
`- A 3.3-volt design
`
`- TI EPICt 0.5/0.6-mm CMOS technology
`
`- Efficient packaging
`J 305-pin ceramic PGA (TMS320C80)
`J 240-pin plastic QFP (TMS320C82)
`
` Overview of the TMS320C8x
`
`SL:1-5
`
`Ex. 1006 / Page 14 of 75
`
`

`
`Why Should I Use the TMS320C8x?
`
`1.2 Why Should I Use the TMS320C8x?
`The ’C8x provides flexible support for evolving industry stan-
`dards and readily adapts to the computational requirements of
`proprietary algorithms by combining exceptional processing
`speed with full programmability. This allows the ’C8x to support
`a multitude of video, graphics, audio, and telecommunications
`applications. In addition, the flexible ’C8x architecture, its fully
`scannable design, and its in-circuit emulation capability permit
`you to design a system that meets your specific needs and that
`can replace multiple boards and multiple processors.
`
`- The TMS320C8x fulfills multiply-intensive, pixel, and bit-
`field processing needs.
`Image-processing applications require two main types of pro-
`cessing: multiply-intensive transforms and pixel/bitfield ma-
`nipulations. Most DSPs are designed to perform only multi-
`ply-intensive operations, but are not designed for pixel and bit
`manipulations. The ’C8x, however, meets the needs of both
`types of processing; the hardware and instruction set of the
`’C8x PPs differ greatly from those of traditional DSPs in their
`ability to manipulate bit fields and to process multiple pixels in
`parallel through the data path.
`
`- The TMS320C8x allows you to perform high-precision
`operations and floating-point computations.
`Two-dimensional and three-dimensional graphics, audio pro-
`cessing, and general-purpose processing can require high-
`precision operations (such as 32×32 bit multiplies) and
`floating-point computations. The ’C8x master processor (MP)
`offers a special set of floating-point instructions to support
`graphics transforms and DSP-like floating-point operations.
`
`- The TMS320C8x provides the processing power to sup-
`port telecommunications applications such as digital
`switches in telephone networks and cellular base sta-
`tions.
`The ’C8x is also ideal for applications in the telecommunica-
`tions industry. Telephone networks and cellular base stations,
`for example, require tremendous processing power. A typical
`cellular base station today employs over 4000 DSPs in a
`single station. The ’C8x can reduce this number by an order of
`magnitude.
`
`SL:1-6
`
`TMS320C8x System-Level Synopsis
`
`Ex. 1006 / Page 15 of 75
`
`

`
` Why Should I Use the TMS320C8x?
`
`- The TMS320C8x offers high data bandwidth and effective
`interprocessor communication.
`Common to most applications is the need for high data band-
`width. A related necessity is the need for effective interpro-
`cessor communication. Through a combination of special-
`ized features, including numerous shared 64-bit wide RAMs,
`a crossbar network, and an intelligent DMA controller, the
`’C8x achieves high bandwidth, reducing the time that its pro-
`cessors spend waiting on data and ensuring that interproces-
`sor communication does not bottleneck.
`
`- The TMS320C8x provides you with in-circuit emulation,
`allowing you to control and monitor the execution of
`each of the processors.
`The ’C8x includes on-chip features that facilitate in-circuit
`emulation. These features allow you to control execution of
`the processors and to monitor each of the processor’s regis-
`ters. You can control the execution of each processor inde-
`pendently of the other processors, or you can synchronize
`processor execution. The control and observation require-
`ments for emulation take advantage of scan paths provided
`for testability. Communication with the on-chip emulation
`hardware is provided through an IEEE1149.1-compliant test
`access port.
`
`- The TMS320C8x allows you to test all registers and
`latches.
`The ’C8x is a fully scannable design that permits you to test
`the status of all registers and latches. The device uses the TI
`modular port scan design for the internal core logic. The I/O
`ports are on a boundary scan path that conforms to the
`IEEE1149.1 standard for boundary scan architecture. Both
`the internal scan paths and the boundary scan paths are ac-
`cessed through an IEEE1149.1-compliant test access port.
`
` Overview of the TMS320C8x
`
`SL:1-7
`
`Ex. 1006 / Page 16 of 75
`
`

`
`Typical Applications
`
`1.3 Typical Applications
`The ’C8x is ideal for applications in the computer, telecommu-
`nications, industrial, video, graphics, and military markets. Typi-
`cal applications are shown in Figure 1–2.
`
`In the past, if you wanted to create a system that combined video,
`audio, and telecommunication functions, for example, you need-
`ed to have a separate processor and board for each application
`of the system. The ’C8x is unlike any other DSP in that you can
`combine multiple applications on a single board.
`
`Figure 1–2. Typical TMS320C8x Applications
`
`Computer
`- Desktop Video confer-
`encing
`- Image processing
`- Real-time MPEG 1, 2,
`or 4 compression
`- PC/workstation 3D
`graphics and imaging
`- Multimedia computers
`- Video servers
`- X-terminals
`
`Telecommunications
`- Phone and ATM
`network processing
`- Cellular and satellite
`base station
`- Video conferencing
`- Video telephony
`- Voice/dial security
`- Cable TV real-time
`video compression
`
`Industrial/Military
`- 2D, 3D, and virtual
`reality graphics
`- Diagnostic imaging
`- Copiers/printers/scan-
`ners/FAX systems
`- Image tracking
`- Security image
`systems
`- JPEG image compres-
`sion/decompression
`
`SL:1-8
`
`TMS320C8x System-Level Synopsis
`
`Ex. 1006 / Page 17 of 75
`
`

`
` The TMS320C8x Development Environment
`
`1.4 The TMS320C8x Development Environment
`The ’C8x supports code development for parallel-processing ap-
`plications by offering a wide range of development tools for SUNs
`and PCs. These tools include optimizing C compilers and assem-
`blers for the MP and the PPs and debugging tools such as an in-
`circuit emulator and a software simulator.
`
`Figure 1–3 shows the major parts of the ’C8x development envi-
`ronment.
`
`Figure 1–3. The TMS320C8x Development Tools
`
`TMS320C8x Simulator
`
`C Compilers
`Algebraic Assemblers
`Device Executive
`
`TMS320 Debugger
`(Windowed)
`
`ÁÁ
`ÁÁ
`
`ÁÁ
`ÁÁ
`ÁÁ
`ÁÁ
`ÁÁ
`
`XDS510 and XDS510WS
`Hardware Emulators
`
`Software Development Board
`
` Overview of the TMS320C8x
`
`SL:1-9
`
`Ex. 1006 / Page 18 of 75
`
`

`
`The TMS320C8x Development Environment
`
`There are eight primary ’C8x software development tools:
`
`- Optimizing ANSI C compilers, which include several key fea-
`tures:
`J Separate compilers for the MP and PPs
`J Easy implementation of data and message-passing
`between tasks (or processors) in parallel-processing
`systems
`J C-source and target-specific optimizations
`J Plum-Hall validation to ANSI standard for code portability
`For more information about the C compilers, see the
`TMS320C80 Code Generation Tools User’s Guide.
`
`- Algebraic assemblers and a linker, including:
`J Separate assemblers that support the MP and PP assem-
`bly languages, and a linker that links assembled code in
`common object file format (COFF) into common memory
`J Directives to map program and data code on specific pro-
`cessors for fast integration and debugging of parallel-pro-
`cessing code
`J Support for creating relocatable modules for maximum
`code flexibility
`For more information about the assemblers and the linker,
`see the TMS320C80 Code Generation Tools User’s Guide.
`
`- Register allocator that:
`J Streamlines code development by efficiently managing
`usage of registers
`J Reduces the time designers normally spend on register
`management, which is generally a time-consuming task
`
`- Code compactor that:
`J Examines serially-written code to identify instructions that
`can run in parallel
`J Maximizes system performance and simplifies develop-
`ment of efficient parallelized code
`
`- Multitasking executive that:
`J Executes on the MP
`J Simplifies the synchronization and execution of multiple
`DSP tasks
`J Supports C8x-to-host processor communications and
`provides local control of on-chip parallel-processing tasks
`
`SL:1-10
`
`TMS320C8x System-Level Synopsis
`
`Ex. 1006 / Page 19 of 75
`
`

`
` The TMS320C8x Development Environment
`
`- Software development board (SDB) with:
`J Full-featured PC add-in card that includes hook-ups for
`acquiring audio and video input and for developing,
`benchmarking, and debugging ’C8x code
`J Board includes:
`H A 40 MHz TMS320C80
`H A PCI bus master interface
`H A 16-bit stereo audio subsystem that supports a sam-
`pling rate of up to 48kHz
`H A 16-bit video acquisition/display subsystem
`H 2 MB of display VRAM to support 16-bit 1024x768 vid-
`eo applications
`J SDB device driver for Windows NTt, including a simple
`applications-programming interface to control data flow
`across the host bus
`J Full concurrent emulation support provided through a
`real-time debugger interface that allows for downloading,
`debugging, and benchmarking code on a ’C8x device
`
`- Parallel-processing in-circuit emulator (XDS510/XDS510WS)
`that allows you to:
`J Debug C and assembly code simultaneously using the
`graphical source-level debugger
`J Debug any number of ’C8xs in a system with a single
`XDS510 or XDS510WS controller
`J Globally stop, start, and single-step all or any combination
`of ’C8x devices in a system
`For more information about the emulator and the debugger,
`see the TMS320C80 C Source Debugger User’s Guide.
`
`- SUN-based Software simulator that provides:
`J Cycle-by-cycle simulation of the ’C8x
`J Effective tool to simulate key software kernels
`
`For more information about the simulator, see the TMS320C80
`C Source Debugger User’s Guide.
`
` Overview of the TMS320C8x
`
`SL:1-11
`
`Ex. 1006 / Page 20 of 75
`
`

`
`
`
`Chapter 2
`
`Multiprocessing
`and System Architecture
`
`This chapter describes the ’C8x architecture. The TMS320C8x
`architecture combines RISC processing and the processing
`power of multiple advanced DSPs (parallel processors), giving
`you the flexibility to design systems that support video, audio,
`graphics, imaging, and other processor-intensive applications.
`The TMS320C80, for example, provides you with the processing
`power to perform over two billion operations per second (BOPS).
`
`Topics
`
`2.1
`2.2
`2.3
`2.4
`2.5
`2.6
`
`. . . . . . . . . . . . . . . . . . . . . . . .
`Architecture Overview
`SL:2-2
`The Master Processor (MP)
`. . . . . . . . . . . . . . . . . . . .
`SL:2-5
`The Parallel Processors (PPs)
`. . . . . . . . . . . . . . . . .
`SL:2-7
`The Transfer Controller (TC)
`. . . . . . . . . . . . . . . . . . .
`SL:2-9
`The Video Controller (VC) (TMS320C80 only)
`SL:2-12
`.
`The Multitasking Executive Software
`. . . . . . . . .
`SL:2-14
`
` Chapter Title—Attribute Reference
`
`SL:2-1
`
`Ex. 1006 / Page 21 of 75
`
`

`
`Architecture Overview
`
`2.1 Architecture Overview
`The ’C8x provides software flexibility and system adaptability
`with its fully programmable parallel-processing platform that inte-
`grates both advanced DSP and RISC architectures. The proces-
`sors on the ’C8x can be configured for a variety of multiple-
`instruction, multiple-data (MIMD) operations and are connected
`by a crossbar network to on-chip SRAMs and to the external
`memory via the transfer controller. This allows you to use shared
`memory efficiently and to eliminate processing delays resulting
`from contention.
`
`Figure 2–1 and Figure 2–2 illustrate the components of the ’C80
`and the ’C82.
`
`Figure 2–1. TMS320C80 Block Diagram
`
`FPU
`
`VC
`
`MP
`
`OCR
`
`C/D
`
`I
`
`32
`
`TAP
`
`64
`
`32
`
`64
`
`PP3
`
`PP2
`
`PP1
`
`PP0
`
`L G
`
`I
`
`L G
`
`I
`
`L G
`
`I
`
`L G
`
`32
`
`64
`
`32
`
`64
`
`32
`
`64
`
`32
`
`32
`
`32
`
`32
`
`32
`
`I
`
`64
`
`Crossbar
`
`64
`
`TC
`
`Instruction Cache
`Instruction Cache
`
`Data Cache
`Data Cache
`
`Parameter RAM
`
`Instruction Cache
`
`Data RAM0
`Data RAM1
`Data RAM2
`
`Parameter RAM
`
`Instruction Cache
`
`Data RAM0
`Data RAM1
`Data RAM2
`
`Parameter RAM
`
`Instruction Cache
`
`Data RAM0
`Data RAM1
`Data RAM2
`
`Parameter RAM
`
`Instruction Cache
`
`Data RAM0
`Data RAM1
`Data RAM2
`
`Parameter RAM
`
`Legend:
`
`Local port
`L
`Instruction port
`I
`OCR On-chip register port
`TAP
`Test access port
`VC
`Video controller
`PP0–3 Parallel processors 0–3
`
`G
`FPU
`C/D
`TC
`MP
`
`Global port
`Floating-point unit
`Cache/data port
`Transfer controller
`Master processo