`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`Apple, Inc.
`PETITIONERS
`
`V.
`Parthenon Unified Memory Architecture LLC
`PATENT OWNER
`___________
`
`Case IPR No: 2016-01134
`Patent No. 7,542,045
`Title: ELECTRONIC SYSTEM AND METHOD FOR DISPLAY USING A
`DECODER AND ARBITER TO SELECTIVELY ALLOW ACCESS TO A
`SHARED MEMORY
`____________
`PATENT OWNER’S PRELIMINARY RESPONSE
`UNDER 37 C.F.R. §42.107
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
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`TABLE OF CONTENTS
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`
`I. INTRODUCTION ............................................................................................. 1
`II. THE ‘045 PATENT ........................................................................................ 2
`III. CLAIM CONSTRUCTION ........................................................................... 3
`IV. PETITIONER DOES NOT ESTABLISH A REASONABLE
`LIKELIHOOD THAT ANY CHALLENGED CLAIM IS INVALID ............... 6
`A. Ground 1: Bowes, Datasheet and Artieri (claims 1, 4, 5, 7, 10, 12, 16, and
`17) ……………………………………………………………………………….6
`1. The MPEG Standard Was Considered During the Prosecution of the
`‘045 Patent ............................................................................................................. 7
`2. Artieri Mirrors the Implementation Identified as Prior Art by the ‘045
`Patent ..................................................................................................................... 7
`3. The Combination of Bowes, Artieri and Datasheet Does Not Disclose
`Every Element of the Challenged Claims ......................................................... 11
`a. The proposed combination does not disclose the video decoder
`receiving a previously decoded image from the [main]/[system] memory . 11
`b. The proposed combination does not disclose an arbiter that controls
`access to the main/system memory................................................................. 27
`4. No Motivation to Combine Bowes and Artieri. ......................................... 33
`B. Ground 2: Bowes, Datasheet and Artieri in view of Gove (claims 17 and
`23) ………………………………………………………………………………47
`V. CONCLUSION ................................................................................................ 48
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`TABLE OF AUTHORITIES
`
`
`Cases
`C.R Bard, Inc. v. M3 Sys., Inc.,
` 157 F.3d 1350, 1352 (Fed. Cir. 1998) ........................................................... 33, 35
`
`In re Fine,
` 837 F.2d 1071, 1076 (Fed. Cir. 1988) .................................................................. 47
`
`In re Rambus Inc.,
`
` 694 F.3d 42, 46 (Fed. Cir. 2012) ........................................................................... 3
`
`In re Wilson,
` 424 F.2d 1382 1385 (CCPA 1970) ....................................................................... 11
`
`Karlin Tech., Inc. v. Surgical Dynamics, Inc.,
` 177 F.3d 968, 971 (Fed. Cir. 1999) ...................................................................... 32
`
`Kinetic Tech., Inc. v. Skyworks Solutions, Inc.,
` IPR2014-00530, 2014 WL 4925282, (Patent Tr. & App. Bd. Sep. 29, 2014) ..... 34
`
`KSR Int’l Co. v. Teleflex Inc.,
` 550 U.S. 398 (2007) ....................................................................................... 33, 35
`
`Phillips v. AWH Corp.,
` 415 F.3d 1303 (Fed. Cir. 2005) .............................................................................. 4
`
`Teleflex, Inc. v. Ficos N. America Corp.,
` 299 F.3d 1313 (Fed. Cir. 2002) ..................................................................... 33, 34
`
`Toyota Motor Corp. v. Cellport Sys., Inc.,
` Case IPR2015-00633, (PTAB Aug. 14, 2015) (Paper 11) ..................................... 3
`
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
` 200 F.3d 795 (Fed. Cir. 1999) ................................................................................ 6
`
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`
`Rules
`35 U.S.C. § 314(a) ..................................................................................................... 1
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`37 C.F.R. § 42.5(b) .................................................................................................... 3
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`TABLE OF EXHIBITS
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`Exhibit Description
`
`Claim Construction Memorandum Opinion and Order, Parthenon
`Unified Memory Architecture, LLC v. Apple, Inc., Case No. 2:15-cv-
`00225 (E.D. Tex.), Dkt No. 162
`Brad Hansen, The Dictionary of Multimedia, 1997
`Excerpts from Stone, H.S., High-Performance Computer Architecture,
`Addison-Wesley Publishing Company, Reading, Massachusetts, 1993,
`ISBN 0-201-52688-3.
`Developer Note – Macintosh Quadra 840AV and Macintosh Centris
`660AV Computers (“Quadra Developer Notes”)
`Institution Decision, IPR2015-01500 (U.S. Pat. No. 7,321,368)
`Parthenon Unified Memory Architecture, LLC v. ZTE Corp., et al., Case
`No. 2:15-cv-00225, Dkt No. 80
`Parthenon Unified Memory Architecture, LLC v. Samsung Electronics
`Co., Ltd., et al., Case No. 2:14-cv-00902, Dkt. No. 155
`Parthenon Unified Memory Architecture, LLC v. HTC Corp., et al., Case
`No. 2:14-cv-00690, Dkt. No. 155
`Institution Decision, IPR2015-01502 (U.S. Pat. No. 7,542,045)
`
`
`Exhibit
`No.
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`2001
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`2002
`2003
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`2004
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`2005
`2006
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`2007
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`2008
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`2009
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`
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`v
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`I.
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`INTRODUCTION
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
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`The patent owner Parthenon Unified Memory Architecture LLC (“Patent
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`Owner”) respectfully requests that the Board deny the Petition for Inter Partes
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`review (“Petition”) filed by Apple, Inc. (“Apple” or “Petitioner”) regarding
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`certain claims of U.S. Patent No. 7,542,045 (“`045 Patent”) because the Petition
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`fails to demonstrate a reasonable likelihood that the Petitioner would prevail as
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`to at least one of the challenged claims, as required under 35 U.S.C. § 314(a).
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`The Petition proposes two grounds challenging claims 1, 4, 5, 7, 9, 10, 12,
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`15, 16, and 17. Specifically, the Petitioner contends that the challenged
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`independent claims and certain dependent claims are invalid as obvious over
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`Bowes, Datasheet, and Artieri (Ground 1). The Petitioner also contends that
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`certain challenged dependent claims are obvious in view of Bowes, Datasheet,
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`and Artieri, further in view of Gove (Ground 2).
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`Ground 1 fails at least because Bowes, Datasheet, and Artieri do not
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`render all limitations of independent claims 1, 4, 5, and 12 obvious. By
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`extension, the challenged dependent claims are also not obvious for at least the
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`same reasons. Therefore, there is no reasonable likelihood that the Petitioner
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`would prevail with respect to any of the claims challenged in Ground 1.
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`1
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`U.S. Patent No. 7,542,045
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`Claims 9 and 15 depend on independent claims 5 and 12, respectively.
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`The Petition does not identify anything in Gove that teaches that which Bowes,
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`Datasheet, and Artieri lack. Therefore, Ground 2 fails at least for the same
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`reasons.
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`The Petition should be denied because there is no reasonable likelihood
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`that the Petitioner would prevail as to any of the challenged claims.
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`II. THE ‘045 PATENT
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`The `045 Patent is generally directed to sharing a memory interface
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`between a video decoder and another device contained in an electronic system.
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`[`045 Pat., Ex. 1001], Abstract; independent claims 1, 4, 5, 12. Accordingly, the
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`electronic system includes a bus coupleable to a main memory. Id. at claim 1.
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`The main memory has stored therein data corresponding to video images to be
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`decoded as well as decoded data corresponding to video images that have
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`previously been decoded. Id. A video decoder is coupled to the bus for receiving
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`encoded video images and for outputting data for displaying the decoded video
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`images on a display device. Id. The decoder is configured to receive data from
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`the main memory corresponding to at least one previously decoded video image
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`and to a current video image to be decoded and output decoded data
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`2
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`corresponding to a current video image to be displayed. Id. The current video
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`image to be displayed is adapted to be stored in the main memory. Id.
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`In addition to the video decoder, the electronic system includes another
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`device configured to access the main memory. Id. An arbiter circuit is coupled
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`to both the video decoder and the other device for controlling access to the main
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`memory. Id.
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`III. CLAIM CONSTRUCTION
`Pursuant to 37 C.F.R. § 42.100(b), “[a] claim in an unexpired patent shall be
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`given its broadest reasonable construction in light of the specification of the patent
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`in which it appears.” The `045 Patent will likely expire before the Board is likely
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`to issue a final written decision as to the patentability of the challenged claims.
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`Therefore, the claim terms are to be construed in accordance with the standard set
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`forth in Phillips.1 37 C.F.R. § 42.5(b); see Toyota Motor Corp. v. Cellport Sys.,
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`Inc., Case IPR2015-00633, slip op. at 8-10 (PTAB Aug. 14, 2015) (Paper 11); cf.
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`In re Rambus Inc., 694 F.3d 42, 46 (Fed. Cir. 2012) (“While claims are generally
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`given their broadest possible scope during prosecution, the Board’s review of the
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`1 The construction of the terms and the analysis of the claims set forth herein
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`would have remained the same even if the broadest reasonable interpretation
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`standard was applied.
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`3
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`claims of an expired patent is similar to that of a district court’s review.”) (internal
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`citation omitted). Under this standard, the claim terms are given their ordinary and
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`accustomed meaning as understood by one having ordinary skill in the art at the
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`time of the invention in the context of the entire patent, considering intrinsic
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`evidence (the claims, the specification, and the prosecution history), and extrinsic
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`evidence (technical dictionaries, treatises, etc.) to a lesser extent. Phillips v. AWH
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`Corp., 415 F.3d 1303, 1313, 1316-17 (Fed. Cir. 2005).
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`A. “decoder” (claims 12 and 15-17); “video decoder” (claims 1, 4, 5,
`7, 9, 10)
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`Patent Owner disagrees with Petitioner’s proposed construction for the term
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`“decoder.” Patent Owner requests that to the extent the Board deems a construction
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`necessary, it construe this term consistent with the term’s construction in parallel
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`proceedings. Specifically, Patent Owner requests that the term “decoder” be
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`construed to mean “hardware and/or software that translates data streams into
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`video or audio information.” See [Ex. 2005 IPR2015-01500, Institution Dec. at 8-
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`9]. This construction is consistent the specification as well as the dictionary
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`definition of the term “decoder”. [`045 Pat., Ex. 1001, 1:66-67 (“a video and/or
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`audio decompression device (hereinafter ‘decoder’)”)]; [Ex. 2002, at 56 (“decoder
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`(n). Any hardware or software system that translates data streams into video or
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`audio information”)]. Similarly, to the extent the Board deems a construction
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`4
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`necessary, the term “video decoder” should be construed consistent with parallel
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`proceeding to mean “hardware and/or software that translates data streams into
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`video information.” See [Ex. 2009 IPR2015-01502, Institution Dec. at 10].
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`B. “fast bus” (claim 7)
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`In parallel litigation, on four separate occasions, the Court construed the
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`term “fast bus” to mean “bus with a bandwidth equal to or greater than the
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`bandwidth required to operate in real time.” See Ex. 2001 at 31; Ex. 2006 at 25;
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`Ex. 2007 at 26; Ex. 2008 at 24. The Petitioner now proposes a different
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`construction for this term – “any bus having a bandwidth sufficient to allow the
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`system to operate in real time.” [Pet. at 12-13]. Applying the same standard applied
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`by the district court, the construction of the term “fast bus” in this proceeding
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`should be the same as that adopted by the District Court. Accordingly, to the extent
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`the Board determines a constructions is necessary, the term “fast bus” should be
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`construed to mean “bus with a bandwidth equal to or greater than the bandwidth
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`required to operate in real time.”2
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`C. Other Claim Terms
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`2 The Patent Owner’s arguments and analysis in this response remains unchanged
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`should the Board adopt Petitioner’s proposed construction for the “decoder”/”video
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`decoder”/”fast bus” terms.
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`5
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`Only terms which are in controversy in this proceeding need to be
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`construed, and then only to the extent necessary to resolve the controversy.
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`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
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`With respect to the claim terms “bus,” “display device,” “arbiter,” “arbiter
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`circuit,” and “memory arbiter,” unless otherwise noted, the analysis below
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`applies the constructions agreed to by the parties in the parallel litigation. Ex.
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`1014, pp. 1-2. Those agreed constructions are consistent with the Phillips
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`standard. Moreover, unless explicitly noted below, the validity analysis below
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`remains unchanged even under a broadest reasonable interpretation of these
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`terms.
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`IV. PETITIONER DOES NOT ESTABLISH A REASONABLE
`LIKELIHOOD THAT ANY CHALLENGED CLAIM IS INVALID
`
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`A. Ground 1: Bowes, Datasheet and Artieri (claims 1, 4, 5, 7, 10,
`12, 16, and 17)
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`The Petition does not establish a reasonable likelihood that any
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`challenged claim is invalid as obvious in view of Bowes, the Datasheet and
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`Artieri for at least three reasons: (1) the proposed combination relies on
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`disclosure or teaching that was already before the Office during prosecution of
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`the `045 Patent; (2) Artieri discloses what the `045 Patent identifies as prior art
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`and suffers from the same shortcomings; (3) Bowes, Datasheet and Artieri,
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`alone or in combination, fail to disclose all limitations of the challenged claims;
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`and (4) one of ordinary skill would not have been motivated to combine Bowes
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`and Datasheet with Artieri as suggested by the Petitioner.
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`1. The MPEG Standard Was Considered During
`Prosecution of the `045 Patent
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`Artieri is directed to “a system for decoding an image encoded according
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`the
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`to an MPEG Standard.” [Ex. 1007, at 2]. The Petitioner relies on Figure 3 of
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`Artieri for the proposition that it would have been obvious to replace the DSP
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`(20) of Bowes with “video decoder circuits specialized for computations
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`dictated by industry-accepted MPEG Standards.” Pet. at 19. However, the
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`Examiner was well aware of the MPEG Standard during prosecution of the `045
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`Patent. More than 30 references considered by the Examiner during prosecution
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`of the `045 Patent were directed to the MPEG Standard. `045 Pat. [Ex. 1001],
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`pp. 1-4. In fact, the MPEG Standard was incorporated by reference into the
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`specification of the `045 Patent. Id. at 15:1-7. Accordingly, this petition presents
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`substantially the same prior art that was already considered by the Examiner
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`during prosecution of the `045 Patent.
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`2. Artieri Mirrors the Implementation Identified as Prior Art
`by the `045 Patent
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`Artieri discloses nothing more than the very same system identified in the
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``045 Patent as prior art. In describing the background of the invention, the `045
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`Patent notes that a typical decoder such as an MPEG decoder (10) contained a
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`video/audio decoding circuit (12/14), a microcontroller (16), and a memory
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`interface (18) coupled to a dedicated memory (22). `045 Pat. [Ex. 1001], 2:21-
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`43. The `045 Patent then highlights the disadvantages of this prior art system:
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`A typical MPEG decoder 10 requires 16 Mbits of memory to
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`operate in the Main Profile at Main Level mode (MP at ML). This
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`typically means that the decoder requires a 2 Mbyte memory.
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`Memory 22 is dedicated to the MPEG decoder 10 and increases the
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`price of adding a decoder 10 to the electronic system. In current
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`technology, the cost of this additional dedicated memory 22 can be
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`a significant percentage of the cost of the decoder.
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`Id. at 2:43-51. Figure 1c of the `045 Patent depicts this prior art
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`configuration and is reproduced below side by side with Figure 3 of
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`Artieri.
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`8
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`Like the prior art system discussed in the `045 Patent, Figure 3 of Artieri depicts
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`an implementation where the decoder is coupled to and utilizes, a dedicated
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`“image memory 15.” Ex. 1007 at 2 (e.g., “Any MPEG decoder, in particular for
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`standard MPEG 2, generally includes … a memory 15.”); 7 (“According to an
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`embodiment of the present invention, elements that have to exchange data with
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`the image memory are connected to the memory bus by respective write or read
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`buffer memories via the memory bus.”); 12 (“In Figure 3, the elements already
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`included in Figure 1 are designated by the same references.”; “A bus, hereafter
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`memory bus MBUS, connects the image memory 15 to the compressed data input
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`bus CDIn, to the input of the variable length word decoder (VLD) 10, to the input
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`of the half-pixel filter 14, and to the input of a display controller 18.”).
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`In fact, the Artieri image memory (15) cannot be a main/system memory at
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`least because it cannot contain non-image data that may be accessed by a computer
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`system, microprocessor, or first device. The Artieri image memory (15), like other
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`prior art dedicated memory components, contained only image data (CD, IM1,
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`IM2, and IM3). [Artieri, Ex. 1007, Fig. 3, p. 14]. Because the Artieri image
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`memory (15) is an internal local memory to the video decoder and is accessed only
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`via the internal MBUS, it would not be operable to serve as the system memory.
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`Accordingly, Artieri discloses the very same configuration identified in
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`the `045 Patent as prior art and suffers from the same drawbacks. In fact, the
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``045 Patent is directed to eliminating the “image memory 15” of Artieri – i.e.,
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`the decoder’s dedicated memory. See `045 Pat., 5:47-51 (“An advantage of the
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`present invention is the significant cost reduction due to the fact that the video
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`and/or audio decompression and/or compression device does not need its own
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`10
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`dedicated memory but can share a memory with another device and still operate
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`in real time”).
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`3. The Combination of Bowes, Artieri and Datasheet Does Not
`Disclose Every Element of the Challenged Claims
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`The proposed combination does not disclose “each and every” claim
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`limitation. See, e.g., In re Wilson, 424 F.2d 1382 1385 (CCPA 1970) (“All
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`words in a claim must be considered in judging the patentability of that claim
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`against the prior art”).
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`a. The proposed combination does not disclose the video decoder
`receiving a previously decoded image from the [main]/[system]
`memory
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`Figure 1c of the `045 Patent depicts a system having a decoder in
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`accordance with the prior art.
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`11
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`The system includes a number of components that are connected to a
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`peripheral bus (170) via interfaces. [`045 Pat., 2:56-63]. A Central Processing Unit
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`(“CPU”) (152) communicates with the peripheral bus (170) through an interface
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`circuit (146) enabling the main memory (168) of the system to be shared between
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`the CPU (152) and other peripherals that may require it. [`045 Pat., 2:64-67].
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`Typically, one of the peripherals connected to the peripheral bus (170) as a master
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`is a decoder (10). [`045 Pat., 3:1-3]. The decoder (10) receives encoded or
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`compressed data from a source peripheral (22) and decodes that data. For instance,
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`if the data to be decoded is video image data, the decoder then directs the decoded
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`video images to a video controller (120) for display. [`045 Pat., 3:3-14].
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`12
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`Traditionally, the decoder (10) included its own dedicated memory (22)
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`which was divided into three image area buffers (M1, M2, M3) and a Compressed
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`Data Buffer (CDB) where the compressed image to be decoded is stored before it
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`is decoded. [`045 Pat., 3:14-19]. Typically, the decoding of images under the
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`MPEG Standard involves processing of “I”, “P” and “B” frames. “I” frames are so
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`called “intra” image frames whose compressed data directly corresponds to an
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`actual image. [`045 Pat., 3:22-23]. “P” frames are so called “predicted” image
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`frames the construction of which uses pixel blocks of a previously decoded image
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`frame. [`045 Pat., 3:23-25]. Finally, “B” frames are so called “bidirectional” image
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`frames the construction of which uses pixel blocks from two previously decoded
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`images. [`045 Pat., 3:26-28]. Accordingly, the “I” and “P” image frames are
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`required to be used to reconstruct subsequent “P” and “B” frames while “B”
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`frames are not used to decode subsequent image frames. [`045 Pat., 3:28-30].
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`Figure 1c depicts how a prior art decoder (10) uses the buffers M1, M2, and
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`M3 of its dedicated memory (22) during the decoding process. [`045 Pat., 3:28-30;
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`3:40-60]. Accordingly, in prior art systems, although the system included a main
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`memory (168) which the decoder (10) could access via the peripheral bus (170),
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`the decoder (10) utilized its local dedicated memory (22) not the main memory
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`(168) when decoding an image. Specifically, an image to be decoded was stored in
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`the CDB of the dedicated memory (22). The decoder (10) then received the image
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`to be decoded from the CDB in its dedicated memory (22). The decoder (10) also
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`received a previously decoded image (i.e., an “I” image frame or a “P” image
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`frame) from the buffers (M1, M2, M3) in its dedicated memory (22). The decoder
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`(10) then used the previously decoded image (i.e., the “I” or “P” image frame) to
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`decode the image to be decoded using, for example, the MPEG decoding standard.
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`The use of this dedicated memory (22) allowed the decoder (10) to decode a
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`compressed image without having to access the main memory and avoided
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`dropping image frames while preserving the available bandwidth on the peripheral
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`bus (170). [`045 Pat., 3:60-4:48].
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`The `045 Patent discloses an improved system which allows the decoder and
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`a first device (e.g., a CPU) to share the main system memory when decoding an
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`image and eliminates the need for a dedicated memory for the decoder.
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`Figure 4 of the `045 Patent depicts an embodiment of the claimed invention
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`where the decoder/encoder (80) shares the main memory (168) with other
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`peripheral devices (e.g., the CPU (152)). [`045 Pat., 10:14-17]. As shown in Figure
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`4, the decoder/encoder (80) does not have a dedicated memory and instead uses a
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`region (22’) of the main memory (168) of the system for the decoding process.
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`[`045 Pat., 10:24-26]. The region (22’) of the main memory (168) includes a
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`14
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`Compressed Data Buffer (CDB) into which the image source (122) writes a
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`compressed image (i.e., an image to be decoded) and two image buffers M1, and
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`M2 associated with “I” and “P” image frames (i.e., previously decoded images).
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`[`045 Pat., 10:27-30]. The third buffer (M3) used in dedicated memory of prior art
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`decoders has been eliminated and the “B” frames which are not used to decode
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`other images are directly supplied to the display adapter (120) as they are being
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`decoded. [`045 Pat., 10:30-33].
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`
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`Accordingly, in the improved system of the `045 Patent an image to be
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`decoded is directed from the source (122) to the CDB in the main memory (168).
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`[`045 Pat., 10:34-36]. This image to be decoded is transferred from the CDB in the
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`main memory (168) to the decoder/encoder (80) over the peripheral bus (170) and
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`is decoded by the decoder. [`045 Pat., 10:36-39]. If the decoded image is an “I”
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`image frame or a “P” image frame, the decoder/encoder (80) retransmits the
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`decoded image to buffers M1 and M2 in the main memory (168). [`045 Pat., 10:36-
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`39]. These “I” and “P” image frames may then be transmitted from the buffers M1
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`and M2 in the main memory (168) back to the decoder and used in decoding of
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`subsequent “P” or “B” image frames or may be transmitted to the display adapter
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`(120) for display. [`045 Pat., 10:44-47]. If an image to be decoded corresponds to a
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`“B” image frame, the decoder/encoder (80) decodes the image and directly
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`supplies it to the display adapter (120) without storing it in the main memory (168)
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`if it is ready for display in the display sequence time frame. [`045 Pat., 10:39-44].
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`Accordingly, in the improved system disclosed in the `045 Patent, the
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`decoder’s dedicated memory is eliminated and instead, the decoder receives an
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`image to be decoded (i.e., compressed image stored in CDB) and a previously
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`decoded image (i.e., “I” image frames or “P” image frames stored in M1 and M2)
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`from a region 22’ in the main memory (168). [Ex. 2009, Thornton Decl. ¶42].
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`These “I” and “P” image frames may then be utilized in decoding of subsequent
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`“P” or “B” image frames by the decoder. [`045 Pat., 10:61-64].
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`Consistent with this improvement, independent claims 1, 4, 5 and 12 recite a
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`[video] decoder configured to receive data from the [main]/[system] memory
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`corresponding to at least one previously decoded [video] image.
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`Accordingly, all independent claims require that the decoder receive a
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`previously decoded image from the main/system memory. As discussed in
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`Section IV.A.2, supra, Artieri does not disclose this limitation and instead,
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`discloses a decoder with a dedicated memory. Similarly, Bowes and Datasheet
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`do not disclose this limitation as discussed below. Therefore, Bowes, Artieri,
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`and Datasheet, alone or in combination, do not disclose this limitation.
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`First, as discussed below, a POSA would not have been motivated to
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`combine Bowes and Artieri. Moreover, even if a POSA were to combine Bowes
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`with Artieri, such a combination would not disclose a video decoder that receives a
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`previously decoded video image from the main memory for at least three reasons:
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`(1) Bowes’ DSP is not a video decoder and a POSA would not have been
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`motivated to replace the Bowes DSP with a video decoder; (2) if such a
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`combination was made, a POSA would have stored a previously decoded image in
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`the dedicated memory of the DSP in accordance with the teachings of Artieri; and
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`(3) Bowes, Datasheet and Artieri do not disclose the DSP writing data into the
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`main memory and then reading the same data from the main memory.
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`Bowes’ DSP is Not a Video Decoder
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`Petitioner has identified the DSP (20) of Bowes as being analogous to the
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`video decoder recited in the `045 Patent. [e.g., Petition at 22-23]. The word
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`“video” is only mentioned four times in Bowes. [Bowes, 1:34; 1:37; 1:41; 6:16].
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`The first three times the term “video” is used in conjunction with a description of
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`related art and the fourth time, the term “video” is used in reference to a NuBus
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`peripheral bus video controller and not in reference to a processing application.
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`The words “decode” or “decoding” never appear in Bowes.
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`Instead, Bowes specifically teaches that the DSP in the preferred
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`embodiment is suitable for audio processing, image signal processing, speech
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`processing, and modem emulation. [Bowes, 1:48-49; 6:32-37]. Bowes does not
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`state that the DSP is suitable for video compression and decompression
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`applications such as the implementations of the MPEG Standard. A POSA would
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`recognize that audio processing, speech processing and modem emulation are
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`clearly distinct from video compression and decompression. The same is true with
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`respect to “image processing.” Therefore, a POSA would understand that the
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`“image processing” referenced in Bowes is distinct from the video decoding
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`implementations disclosed in the `045 Patent.
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`In the 1993 time frame, “image processing” was defined as “a computation
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`performed on a digitized representation of an image whose purpose is to enhance
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`the image or to extract information about the image.” [Ex. 2003 at 499]. In
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`contrast, the MPEG Standard is directed to compressing and decompressing video
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`sequences. [Ex. 1008, p. 4]. Such a compression and decompression of video
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`sequences is wholly different from image processing. For example, video
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`compression and decompression requires maintaining the temporal relationship
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`between consecutive image frames, an important concept that is absent when
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`processing a single image.
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`There are additional reasons why a POSA would recognize that a DSP used
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`for image processing is not suitable for video compression and decompression.
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`Specifically, image processing requires precision and involves a host of arithmetic
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`operations. In contrast,
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`the primary concern
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`in video compression and
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`decompression is speed to ensure that video is delivered to viewer in real time.
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`Therefore, video compression and decompression processes typically do not
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`require the same level of precision and arithmetic operations as image processing.
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`As a result, a POSA would typically use a different type of DSP for image
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`processing as compared to video compression and decompression. Specifically, the
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`internal architecture of a DSP may be categorized according to the type of
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`numerical format it utilizes. A “floating point” DSP utilizes a format wherein a
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`single value is specified with three fields, a sign field indicating whether the value
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`is positive or negative; a mantissa or significand field indicating the precision of
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`the value; and a signed exponent field indicating the magnitude. In contrast, a
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`“fixed point” DSP utilizes a format wherein a single value represents the signed
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`value using an appropriate signed value encoding such as 2’s complement and
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`where the binary- or radix point is in a “fixed” position.
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`That the DSP (20) of Bowes is not suitable for video compression and
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`decompression is further evident from the fact that Bowes states that in a preferred
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`embodiment, the DSP (20) of Bowes is the AT&T DSP3210. [Bowes, 6:28-30].
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`Such a DSP is not suitable for MPEG video decoding because it is a floating point
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`DSP. [Ex. 1006, at 1]. Specifically, the AT&T DSP3210 utilizes a floating-point
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`Data Arithmetic Unit (DAU) that “is the primary execution unit for signal
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`processing algorithms.” [Ex. 1006, at 5].
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`Due to its use of a more complex format, a floating point DSP generally
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`incurs increased latency but provides increased accuracy and dynamic range (i.e., it
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`can represent a wider range of numerical values). In contrast, a fixed point DSP
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`allows higher performance but at the expense of decreased accuracy and dynamic
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`range. Therefore, a POSA would appreciate that a floating point DSP is not well-
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`suited for video compression and decompression.
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`A POSA would appreciate that MPEG decoding is a high throughput
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`operation consisting in part, of repeated inverse discrete cosine transforms (IDCT),
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`VLD, de-quantization, and o