throbber
IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045 
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`Apple, Inc.
`PETITIONERS
`
`V.
`Parthenon Unified Memory Architecture LLC
`PATENT OWNER
`___________
`
`Case IPR No: 2016-01134
`Patent No. 7,542,045
`Title: ELECTRONIC SYSTEM AND METHOD FOR DISPLAY USING A
`DECODER AND ARBITER TO SELECTIVELY ALLOW ACCESS TO A
`SHARED MEMORY
`____________
`PATENT OWNER’S PRELIMINARY RESPONSE
`UNDER 37 C.F.R. §42.107
`
`
`
` 
`
`
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`

`
`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`
`TABLE OF CONTENTS
`
`
`I. INTRODUCTION ............................................................................................. 1
`II. THE ‘045 PATENT ........................................................................................ 2
`III. CLAIM CONSTRUCTION ........................................................................... 3
`IV. PETITIONER DOES NOT ESTABLISH A REASONABLE
`LIKELIHOOD THAT ANY CHALLENGED CLAIM IS INVALID ............... 6
`A. Ground 1: Bowes, Datasheet and Artieri (claims 1, 4, 5, 7, 10, 12, 16, and
`17) ……………………………………………………………………………….6
`1. The MPEG Standard Was Considered During the Prosecution of the
`‘045 Patent ............................................................................................................. 7
`2. Artieri Mirrors the Implementation Identified as Prior Art by the ‘045
`Patent ..................................................................................................................... 7
`3. The Combination of Bowes, Artieri and Datasheet Does Not Disclose
`Every Element of the Challenged Claims ......................................................... 11
`a. The proposed combination does not disclose the video decoder
`receiving a previously decoded image from the [main]/[system] memory . 11
`b. The proposed combination does not disclose an arbiter that controls
`access to the main/system memory................................................................. 27
`4. No Motivation to Combine Bowes and Artieri. ......................................... 33
`B. Ground 2: Bowes, Datasheet and Artieri in view of Gove (claims 17 and
`23) ………………………………………………………………………………47
`V. CONCLUSION ................................................................................................ 48
`
`
`
`ii
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`
`TABLE OF AUTHORITIES
`
`
`Cases
`C.R Bard, Inc. v. M3 Sys., Inc.,
` 157 F.3d 1350, 1352 (Fed. Cir. 1998) ........................................................... 33, 35
` 
`In re Fine,
` 837 F.2d 1071, 1076 (Fed. Cir. 1988) .................................................................. 47
` 
`In re Rambus Inc.,
`
` 694 F.3d 42, 46 (Fed. Cir. 2012) ........................................................................... 3
` 
`In re Wilson,
` 424 F.2d 1382 1385 (CCPA 1970) ....................................................................... 11
` 
`Karlin Tech., Inc. v. Surgical Dynamics, Inc.,
` 177 F.3d 968, 971 (Fed. Cir. 1999) ...................................................................... 32
` 
`Kinetic Tech., Inc. v. Skyworks Solutions, Inc.,
` IPR2014-00530, 2014 WL 4925282, (Patent Tr. & App. Bd. Sep. 29, 2014) ..... 34
` 
`KSR Int’l Co. v. Teleflex Inc.,
` 550 U.S. 398 (2007) ....................................................................................... 33, 35
` 
`Phillips v. AWH Corp.,
` 415 F.3d 1303 (Fed. Cir. 2005) .............................................................................. 4
` 
`Teleflex, Inc. v. Ficos N. America Corp.,
` 299 F.3d 1313 (Fed. Cir. 2002) ..................................................................... 33, 34
` 
`Toyota Motor Corp. v. Cellport Sys., Inc.,
` Case IPR2015-00633, (PTAB Aug. 14, 2015) (Paper 11) ..................................... 3
` 
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
` 200 F.3d 795 (Fed. Cir. 1999) ................................................................................ 6
`
`
` 
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`iii
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`
`Rules
`35 U.S.C. § 314(a) ..................................................................................................... 1
` 
`37 C.F.R. § 42.5(b) .................................................................................................... 3
`
`
`
` 
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`
`TABLE OF EXHIBITS
`
`Exhibit Description
`
`Claim Construction Memorandum Opinion and Order, Parthenon
`Unified Memory Architecture, LLC v. Apple, Inc., Case No. 2:15-cv-
`00225 (E.D. Tex.), Dkt No. 162
`Brad Hansen, The Dictionary of Multimedia, 1997
`Excerpts from Stone, H.S., High-Performance Computer Architecture,
`Addison-Wesley Publishing Company, Reading, Massachusetts, 1993,
`ISBN 0-201-52688-3.
`Developer Note – Macintosh Quadra 840AV and Macintosh Centris
`660AV Computers (“Quadra Developer Notes”)
`Institution Decision, IPR2015-01500 (U.S. Pat. No. 7,321,368)
`Parthenon Unified Memory Architecture, LLC v. ZTE Corp., et al., Case
`No. 2:15-cv-00225, Dkt No. 80
`Parthenon Unified Memory Architecture, LLC v. Samsung Electronics
`Co., Ltd., et al., Case No. 2:14-cv-00902, Dkt. No. 155
`Parthenon Unified Memory Architecture, LLC v. HTC Corp., et al., Case
`No. 2:14-cv-00690, Dkt. No. 155
`Institution Decision, IPR2015-01502 (U.S. Pat. No. 7,542,045)
`
`
`Exhibit
`No.
`
`2001
`
`2002
`2003
`
`2004
`
`2005
`2006
`
`2007
`
`2008
`
`2009
`
` 
`
`v
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`I.
`
`INTRODUCTION
`
`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`
`The patent owner Parthenon Unified Memory Architecture LLC (“Patent
`
`Owner”) respectfully requests that the Board deny the Petition for Inter Partes
`
`review (“Petition”) filed by Apple, Inc. (“Apple” or “Petitioner”) regarding
`
`certain claims of U.S. Patent No. 7,542,045 (“`045 Patent”) because the Petition
`
`fails to demonstrate a reasonable likelihood that the Petitioner would prevail as
`
`to at least one of the challenged claims, as required under 35 U.S.C. § 314(a).
`
`The Petition proposes two grounds challenging claims 1, 4, 5, 7, 9, 10, 12,
`
`15, 16, and 17. Specifically, the Petitioner contends that the challenged
`
`independent claims and certain dependent claims are invalid as obvious over
`
`Bowes, Datasheet, and Artieri (Ground 1). The Petitioner also contends that
`
`certain challenged dependent claims are obvious in view of Bowes, Datasheet,
`
`and Artieri, further in view of Gove (Ground 2).
`
`Ground 1 fails at least because Bowes, Datasheet, and Artieri do not
`
`render all limitations of independent claims 1, 4, 5, and 12 obvious. By
`
`extension, the challenged dependent claims are also not obvious for at least the
`
`same reasons. Therefore, there is no reasonable likelihood that the Petitioner
`
`would prevail with respect to any of the claims challenged in Ground 1.
`
` 
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`1
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`Claims 9 and 15 depend on independent claims 5 and 12, respectively.
`
`The Petition does not identify anything in Gove that teaches that which Bowes,
`
`Datasheet, and Artieri lack. Therefore, Ground 2 fails at least for the same
`
`reasons.
`
`The Petition should be denied because there is no reasonable likelihood
`
`that the Petitioner would prevail as to any of the challenged claims.
`
`II. THE ‘045 PATENT
`
`The `045 Patent is generally directed to sharing a memory interface
`
`between a video decoder and another device contained in an electronic system.
`
`[`045 Pat., Ex. 1001], Abstract; independent claims 1, 4, 5, 12. Accordingly, the
`
`electronic system includes a bus coupleable to a main memory. Id. at claim 1.
`
`The main memory has stored therein data corresponding to video images to be
`
`decoded as well as decoded data corresponding to video images that have
`
`previously been decoded. Id. A video decoder is coupled to the bus for receiving
`
`encoded video images and for outputting data for displaying the decoded video
`
`images on a display device. Id. The decoder is configured to receive data from
`
`the main memory corresponding to at least one previously decoded video image
`
`and to a current video image to be decoded and output decoded data
`
` 
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`2
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`corresponding to a current video image to be displayed. Id. The current video
`
`image to be displayed is adapted to be stored in the main memory. Id.
`
`In addition to the video decoder, the electronic system includes another
`
`device configured to access the main memory. Id. An arbiter circuit is coupled
`
`to both the video decoder and the other device for controlling access to the main
`
`memory. Id.
`
`III. CLAIM CONSTRUCTION
`Pursuant to 37 C.F.R. § 42.100(b), “[a] claim in an unexpired patent shall be
`
`given its broadest reasonable construction in light of the specification of the patent
`
`in which it appears.” The `045 Patent will likely expire before the Board is likely
`
`to issue a final written decision as to the patentability of the challenged claims.
`
`Therefore, the claim terms are to be construed in accordance with the standard set
`
`forth in Phillips.1 37 C.F.R. § 42.5(b); see Toyota Motor Corp. v. Cellport Sys.,
`
`Inc., Case IPR2015-00633, slip op. at 8-10 (PTAB Aug. 14, 2015) (Paper 11); cf.
`
`In re Rambus Inc., 694 F.3d 42, 46 (Fed. Cir. 2012) (“While claims are generally
`
`given their broadest possible scope during prosecution, the Board’s review of the
`
`                                                            
`1 The construction of the terms and the analysis of the claims set forth herein
`
`would have remained the same even if the broadest reasonable interpretation
`
`standard was applied. 
`
` 
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`3
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
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`claims of an expired patent is similar to that of a district court’s review.”) (internal
`
`citation omitted). Under this standard, the claim terms are given their ordinary and
`
`accustomed meaning as understood by one having ordinary skill in the art at the
`
`time of the invention in the context of the entire patent, considering intrinsic
`
`evidence (the claims, the specification, and the prosecution history), and extrinsic
`
`evidence (technical dictionaries, treatises, etc.) to a lesser extent. Phillips v. AWH
`
`Corp., 415 F.3d 1303, 1313, 1316-17 (Fed. Cir. 2005).
`
`A. “decoder” (claims 12 and 15-17); “video decoder” (claims 1, 4, 5,
`7, 9, 10)
`
`Patent Owner disagrees with Petitioner’s proposed construction for the term
`
`“decoder.” Patent Owner requests that to the extent the Board deems a construction
`
`necessary, it construe this term consistent with the term’s construction in parallel
`
`proceedings. Specifically, Patent Owner requests that the term “decoder” be
`
`construed to mean “hardware and/or software that translates data streams into
`
`video or audio information.” See [Ex. 2005 IPR2015-01500, Institution Dec. at 8-
`
`9]. This construction is consistent the specification as well as the dictionary
`
`definition of the term “decoder”. [`045 Pat., Ex. 1001, 1:66-67 (“a video and/or
`
`audio decompression device (hereinafter ‘decoder’)”)]; [Ex. 2002, at 56 (“decoder
`
`(n). Any hardware or software system that translates data streams into video or
`
`audio information”)]. Similarly, to the extent the Board deems a construction
`
` 
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
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`necessary, the term “video decoder” should be construed consistent with parallel
`
`proceeding to mean “hardware and/or software that translates data streams into
`
`video information.” See [Ex. 2009 IPR2015-01502, Institution Dec. at 10].
`
`B. “fast bus” (claim 7)
`
`In parallel litigation, on four separate occasions, the Court construed the
`
`term “fast bus” to mean “bus with a bandwidth equal to or greater than the
`
`bandwidth required to operate in real time.” See Ex. 2001 at 31; Ex. 2006 at 25;
`
`Ex. 2007 at 26; Ex. 2008 at 24. The Petitioner now proposes a different
`
`construction for this term – “any bus having a bandwidth sufficient to allow the
`
`system to operate in real time.” [Pet. at 12-13]. Applying the same standard applied
`
`by the district court, the construction of the term “fast bus” in this proceeding
`
`should be the same as that adopted by the District Court. Accordingly, to the extent
`
`the Board determines a constructions is necessary, the term “fast bus” should be
`
`construed to mean “bus with a bandwidth equal to or greater than the bandwidth
`
`required to operate in real time.”2
`
`C. Other Claim Terms
`
`                                                            
`2 The Patent Owner’s arguments and analysis in this response remains unchanged
`
`should the Board adopt Petitioner’s proposed construction for the “decoder”/”video
`
`decoder”/”fast bus” terms.
`
` 
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`5
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`Only terms which are in controversy in this proceeding need to be
`
`construed, and then only to the extent necessary to resolve the controversy.
`
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`
`With respect to the claim terms “bus,” “display device,” “arbiter,” “arbiter
`
`circuit,” and “memory arbiter,” unless otherwise noted, the analysis below
`
`applies the constructions agreed to by the parties in the parallel litigation. Ex.
`
`1014, pp. 1-2. Those agreed constructions are consistent with the Phillips
`
`standard. Moreover, unless explicitly noted below, the validity analysis below
`
`remains unchanged even under a broadest reasonable interpretation of these
`
`terms.
`
`IV. PETITIONER DOES NOT ESTABLISH A REASONABLE
`LIKELIHOOD THAT ANY CHALLENGED CLAIM IS INVALID
`
`
`A. Ground 1: Bowes, Datasheet and Artieri (claims 1, 4, 5, 7, 10,
`12, 16, and 17)
`
`The Petition does not establish a reasonable likelihood that any
`
`challenged claim is invalid as obvious in view of Bowes, the Datasheet and
`
`Artieri for at least three reasons: (1) the proposed combination relies on
`
`disclosure or teaching that was already before the Office during prosecution of
`
`the `045 Patent; (2) Artieri discloses what the `045 Patent identifies as prior art
`
`and suffers from the same shortcomings; (3) Bowes, Datasheet and Artieri,
`6
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`alone or in combination, fail to disclose all limitations of the challenged claims;
`
`and (4) one of ordinary skill would not have been motivated to combine Bowes
`
`and Datasheet with Artieri as suggested by the Petitioner.
`
`1. The MPEG Standard Was Considered During
`Prosecution of the `045 Patent
`
`Artieri is directed to “a system for decoding an image encoded according
`
`the
`
`to an MPEG Standard.” [Ex. 1007, at 2]. The Petitioner relies on Figure 3 of
`
`Artieri for the proposition that it would have been obvious to replace the DSP
`
`(20) of Bowes with “video decoder circuits specialized for computations
`
`dictated by industry-accepted MPEG Standards.” Pet. at 19. However, the
`
`Examiner was well aware of the MPEG Standard during prosecution of the `045
`
`Patent. More than 30 references considered by the Examiner during prosecution
`
`of the `045 Patent were directed to the MPEG Standard. `045 Pat. [Ex. 1001],
`
`pp. 1-4. In fact, the MPEG Standard was incorporated by reference into the
`
`specification of the `045 Patent. Id. at 15:1-7. Accordingly, this petition presents
`
`substantially the same prior art that was already considered by the Examiner
`
`during prosecution of the `045 Patent.
`
`2. Artieri Mirrors the Implementation Identified as Prior Art
`by the `045 Patent
`
`
` 
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`7
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`Artieri discloses nothing more than the very same system identified in the
`
``045 Patent as prior art. In describing the background of the invention, the `045
`
`Patent notes that a typical decoder such as an MPEG decoder (10) contained a
`
`video/audio decoding circuit (12/14), a microcontroller (16), and a memory
`
`interface (18) coupled to a dedicated memory (22). `045 Pat. [Ex. 1001], 2:21-
`
`43. The `045 Patent then highlights the disadvantages of this prior art system:
`
`A typical MPEG decoder 10 requires 16 Mbits of memory to
`
`operate in the Main Profile at Main Level mode (MP at ML). This
`
`typically means that the decoder requires a 2 Mbyte memory.
`
`Memory 22 is dedicated to the MPEG decoder 10 and increases the
`
`price of adding a decoder 10 to the electronic system. In current
`
`technology, the cost of this additional dedicated memory 22 can be
`
`a significant percentage of the cost of the decoder.
`
`Id. at 2:43-51. Figure 1c of the `045 Patent depicts this prior art
`
`configuration and is reproduced below side by side with Figure 3 of
`
`Artieri.
`
` 
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`
`
`
`Like the prior art system discussed in the `045 Patent, Figure 3 of Artieri depicts
`
`an implementation where the decoder is coupled to and utilizes, a dedicated
`
`“image memory 15.” Ex. 1007 at 2 (e.g., “Any MPEG decoder, in particular for
`
`standard MPEG 2, generally includes … a memory 15.”); 7 (“According to an
`
`embodiment of the present invention, elements that have to exchange data with
`
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
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`the image memory are connected to the memory bus by respective write or read
`
`buffer memories via the memory bus.”); 12 (“In Figure 3, the elements already
`
`included in Figure 1 are designated by the same references.”; “A bus, hereafter
`
`memory bus MBUS, connects the image memory 15 to the compressed data input
`
`bus CDIn, to the input of the variable length word decoder (VLD) 10, to the input
`
`of the half-pixel filter 14, and to the input of a display controller 18.”).
`
`In fact, the Artieri image memory (15) cannot be a main/system memory at
`
`least because it cannot contain non-image data that may be accessed by a computer
`
`system, microprocessor, or first device. The Artieri image memory (15), like other
`
`prior art dedicated memory components, contained only image data (CD, IM1,
`
`IM2, and IM3). [Artieri, Ex. 1007, Fig. 3, p. 14]. Because the Artieri image
`
`memory (15) is an internal local memory to the video decoder and is accessed only
`
`via the internal MBUS, it would not be operable to serve as the system memory.
`
`Accordingly, Artieri discloses the very same configuration identified in
`
`the `045 Patent as prior art and suffers from the same drawbacks. In fact, the
`
``045 Patent is directed to eliminating the “image memory 15” of Artieri – i.e.,
`
`the decoder’s dedicated memory. See `045 Pat., 5:47-51 (“An advantage of the
`
`present invention is the significant cost reduction due to the fact that the video
`
`and/or audio decompression and/or compression device does not need its own
`
` 
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`10
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
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`dedicated memory but can share a memory with another device and still operate
`
`in real time”).
`
`3. The Combination of Bowes, Artieri and Datasheet Does Not
`Disclose Every Element of the Challenged Claims
`
`The proposed combination does not disclose “each and every” claim
`
`limitation. See, e.g., In re Wilson, 424 F.2d 1382 1385 (CCPA 1970) (“All
`
`words in a claim must be considered in judging the patentability of that claim
`
`against the prior art”).
`
`a. The proposed combination does not disclose the video decoder
`receiving a previously decoded image from the [main]/[system]
`memory
`
`
`Figure 1c of the `045 Patent depicts a system having a decoder in
`
`accordance with the prior art.
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`11
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
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`
`
`
`The system includes a number of components that are connected to a
`
`peripheral bus (170) via interfaces. [`045 Pat., 2:56-63]. A Central Processing Unit
`
`(“CPU”) (152) communicates with the peripheral bus (170) through an interface
`
`circuit (146) enabling the main memory (168) of the system to be shared between
`
`the CPU (152) and other peripherals that may require it. [`045 Pat., 2:64-67].
`
`Typically, one of the peripherals connected to the peripheral bus (170) as a master
`
`is a decoder (10). [`045 Pat., 3:1-3]. The decoder (10) receives encoded or
`
`compressed data from a source peripheral (22) and decodes that data. For instance,
`
`if the data to be decoded is video image data, the decoder then directs the decoded
`
`video images to a video controller (120) for display. [`045 Pat., 3:3-14].
`
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`12
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`Traditionally, the decoder (10) included its own dedicated memory (22)
`
`which was divided into three image area buffers (M1, M2, M3) and a Compressed
`
`Data Buffer (CDB) where the compressed image to be decoded is stored before it
`
`is decoded. [`045 Pat., 3:14-19]. Typically, the decoding of images under the
`
`MPEG Standard involves processing of “I”, “P” and “B” frames. “I” frames are so
`
`called “intra” image frames whose compressed data directly corresponds to an
`
`actual image. [`045 Pat., 3:22-23]. “P” frames are so called “predicted” image
`
`frames the construction of which uses pixel blocks of a previously decoded image
`
`frame. [`045 Pat., 3:23-25]. Finally, “B” frames are so called “bidirectional” image
`
`frames the construction of which uses pixel blocks from two previously decoded
`
`images. [`045 Pat., 3:26-28]. Accordingly, the “I” and “P” image frames are
`
`required to be used to reconstruct subsequent “P” and “B” frames while “B”
`
`frames are not used to decode subsequent image frames. [`045 Pat., 3:28-30].
`
`Figure 1c depicts how a prior art decoder (10) uses the buffers M1, M2, and
`
`M3 of its dedicated memory (22) during the decoding process. [`045 Pat., 3:28-30;
`
`3:40-60]. Accordingly, in prior art systems, although the system included a main
`
`memory (168) which the decoder (10) could access via the peripheral bus (170),
`
`the decoder (10) utilized its local dedicated memory (22) not the main memory
`
`(168) when decoding an image. Specifically, an image to be decoded was stored in
`
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
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`the CDB of the dedicated memory (22). The decoder (10) then received the image
`
`to be decoded from the CDB in its dedicated memory (22). The decoder (10) also
`
`received a previously decoded image (i.e., an “I” image frame or a “P” image
`
`frame) from the buffers (M1, M2, M3) in its dedicated memory (22). The decoder
`
`(10) then used the previously decoded image (i.e., the “I” or “P” image frame) to
`
`decode the image to be decoded using, for example, the MPEG decoding standard.
`
`The use of this dedicated memory (22) allowed the decoder (10) to decode a
`
`compressed image without having to access the main memory and avoided
`
`dropping image frames while preserving the available bandwidth on the peripheral
`
`bus (170). [`045 Pat., 3:60-4:48].
`
`The `045 Patent discloses an improved system which allows the decoder and
`
`a first device (e.g., a CPU) to share the main system memory when decoding an
`
`image and eliminates the need for a dedicated memory for the decoder.
`
`Figure 4 of the `045 Patent depicts an embodiment of the claimed invention
`
`where the decoder/encoder (80) shares the main memory (168) with other
`
`peripheral devices (e.g., the CPU (152)). [`045 Pat., 10:14-17]. As shown in Figure
`
`4, the decoder/encoder (80) does not have a dedicated memory and instead uses a
`
`region (22’) of the main memory (168) of the system for the decoding process.
`
`[`045 Pat., 10:24-26]. The region (22’) of the main memory (168) includes a
`
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`14
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
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`Compressed Data Buffer (CDB) into which the image source (122) writes a
`
`compressed image (i.e., an image to be decoded) and two image buffers M1, and
`
`M2 associated with “I” and “P” image frames (i.e., previously decoded images).
`
`[`045 Pat., 10:27-30]. The third buffer (M3) used in dedicated memory of prior art
`
`decoders has been eliminated and the “B” frames which are not used to decode
`
`other images are directly supplied to the display adapter (120) as they are being
`
`decoded. [`045 Pat., 10:30-33].
`
`
`
`Accordingly, in the improved system of the `045 Patent an image to be
`
`decoded is directed from the source (122) to the CDB in the main memory (168).
`
`[`045 Pat., 10:34-36]. This image to be decoded is transferred from the CDB in the
`
`main memory (168) to the decoder/encoder (80) over the peripheral bus (170) and
`
`is decoded by the decoder. [`045 Pat., 10:36-39]. If the decoded image is an “I”
`
`image frame or a “P” image frame, the decoder/encoder (80) retransmits the
`
`decoded image to buffers M1 and M2 in the main memory (168). [`045 Pat., 10:36-
`
` 
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`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
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`39]. These “I” and “P” image frames may then be transmitted from the buffers M1
`
`and M2 in the main memory (168) back to the decoder and used in decoding of
`
`subsequent “P” or “B” image frames or may be transmitted to the display adapter
`
`(120) for display. [`045 Pat., 10:44-47]. If an image to be decoded corresponds to a
`
`“B” image frame, the decoder/encoder (80) decodes the image and directly
`
`supplies it to the display adapter (120) without storing it in the main memory (168)
`
`if it is ready for display in the display sequence time frame. [`045 Pat., 10:39-44].
`
`Accordingly, in the improved system disclosed in the `045 Patent, the
`
`decoder’s dedicated memory is eliminated and instead, the decoder receives an
`
`image to be decoded (i.e., compressed image stored in CDB) and a previously
`
`decoded image (i.e., “I” image frames or “P” image frames stored in M1 and M2)
`
`from a region 22’ in the main memory (168). [Ex. 2009, Thornton Decl. ¶42].
`
`These “I” and “P” image frames may then be utilized in decoding of subsequent
`
`“P” or “B” image frames by the decoder. [`045 Pat., 10:61-64].
`
`Consistent with this improvement, independent claims 1, 4, 5 and 12 recite a
`
`[video] decoder configured to receive data from the [main]/[system] memory
`
`corresponding to at least one previously decoded [video] image.
`
`Accordingly, all independent claims require that the decoder receive a
`
`previously decoded image from the main/system memory. As discussed in
`
` 
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`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`Section IV.A.2, supra, Artieri does not disclose this limitation and instead,
`
`discloses a decoder with a dedicated memory. Similarly, Bowes and Datasheet
`
`do not disclose this limitation as discussed below. Therefore, Bowes, Artieri,
`
`and Datasheet, alone or in combination, do not disclose this limitation.
`
`First, as discussed below, a POSA would not have been motivated to
`
`combine Bowes and Artieri. Moreover, even if a POSA were to combine Bowes
`
`with Artieri, such a combination would not disclose a video decoder that receives a
`
`previously decoded video image from the main memory for at least three reasons:
`
`(1) Bowes’ DSP is not a video decoder and a POSA would not have been
`
`motivated to replace the Bowes DSP with a video decoder; (2) if such a
`
`combination was made, a POSA would have stored a previously decoded image in
`
`the dedicated memory of the DSP in accordance with the teachings of Artieri; and
`
`(3) Bowes, Datasheet and Artieri do not disclose the DSP writing data into the
`
`main memory and then reading the same data from the main memory.
`
`Bowes’ DSP is Not a Video Decoder
`
`Petitioner has identified the DSP (20) of Bowes as being analogous to the
`
`video decoder recited in the `045 Patent. [e.g., Petition at 22-23]. The word
`
`“video” is only mentioned four times in Bowes. [Bowes, 1:34; 1:37; 1:41; 6:16].
`
`The first three times the term “video” is used in conjunction with a description of
`
` 
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`17
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`related art and the fourth time, the term “video” is used in reference to a NuBus
`
`peripheral bus video controller and not in reference to a processing application.
`
`The words “decode” or “decoding” never appear in Bowes.
`
`Instead, Bowes specifically teaches that the DSP in the preferred
`
`embodiment is suitable for audio processing, image signal processing, speech
`
`processing, and modem emulation. [Bowes, 1:48-49; 6:32-37]. Bowes does not
`
`state that the DSP is suitable for video compression and decompression
`
`applications such as the implementations of the MPEG Standard. A POSA would
`
`recognize that audio processing, speech processing and modem emulation are
`
`clearly distinct from video compression and decompression. The same is true with
`
`respect to “image processing.” Therefore, a POSA would understand that the
`
`“image processing” referenced in Bowes is distinct from the video decoding
`
`implementations disclosed in the `045 Patent.
`
`In the 1993 time frame, “image processing” was defined as “a computation
`
`performed on a digitized representation of an image whose purpose is to enhance
`
`the image or to extract information about the image.” [Ex. 2003 at 499]. In
`
`contrast, the MPEG Standard is directed to compressing and decompressing video
`
`sequences. [Ex. 1008, p. 4]. Such a compression and decompression of video
`
`sequences is wholly different from image processing. For example, video
`
` 
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`18
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`compression and decompression requires maintaining the temporal relationship
`
`between consecutive image frames, an important concept that is absent when
`
`processing a single image.
`
`There are additional reasons why a POSA would recognize that a DSP used
`
`for image processing is not suitable for video compression and decompression.
`
`Specifically, image processing requires precision and involves a host of arithmetic
`
`operations. In contrast,
`
`the primary concern
`
`in video compression and
`
`decompression is speed to ensure that video is delivered to viewer in real time.
`
`Therefore, video compression and decompression processes typically do not
`
`require the same level of precision and arithmetic operations as image processing.
`
`As a result, a POSA would typically use a different type of DSP for image
`
`processing as compared to video compression and decompression. Specifically, the
`
`internal architecture of a DSP may be categorized according to the type of
`
`numerical format it utilizes. A “floating point” DSP utilizes a format wherein a
`
`single value is specified with three fields, a sign field indicating whether the value
`
`is positive or negative; a mantissa or significand field indicating the precision of
`
`the value; and a signed exponent field indicating the magnitude. In contrast, a
`
`“fixed point” DSP utilizes a format wherein a single value represents the signed
`
` 
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`IPR2016-01134
`Patent Owner Preliminary Response
`U.S. Patent No. 7,542,045
` 
`value using an appropriate signed value encoding such as 2’s complement and
`
`where the binary- or radix point is in a “fixed” position.
`
`That the DSP (20) of Bowes is not suitable for video compression and
`
`decompression is further evident from the fact that Bowes states that in a preferred
`
`embodiment, the DSP (20) of Bowes is the AT&T DSP3210. [Bowes, 6:28-30].
`
`Such a DSP is not suitable for MPEG video decoding because it is a floating point
`
`DSP. [Ex. 1006, at 1]. Specifically, the AT&T DSP3210 utilizes a floating-point
`
`Data Arithmetic Unit (DAU) that “is the primary execution unit for signal
`
`processing algorithms.” [Ex. 1006, at 5].
`
`Due to its use of a more complex format, a floating point DSP generally
`
`incurs increased latency but provides increased accuracy and dynamic range (i.e., it
`
`can represent a wider range of numerical values). In contrast, a fixed point DSP
`
`allows higher performance but at the expense of decreased accuracy and dynamic
`
`range. Therefore, a POSA would appreciate that a floating point DSP is not well-
`
`suited for video compression and decompression.
`
`A POSA would appreciate that MPEG decoding is a high throughput
`
`operation consisting in part, of repeated inverse discrete cosine transforms (IDCT),
`
`VLD, de-quantization, and o

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