Case 2:15-cv-00621-JRG-RSP Document 162 Filed 06/17/16 Page 1 of 50 PageID #: 7035
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`UNITED STATES DISTRICT COURT
`EASTERN DISTRICT OF TEXAS
`MARSHALL DIVISION
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`Case No. 2:15-cv-00621-JRG-RSP
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`PARTHENON UNIFIED MEMORY
`ARCHITECTURE LLC,
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`Plaintiff,
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`v.
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`APPLE INC.,
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`
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`Defendant.
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`
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`MEMORANDUM OPINION AND ORDER
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` On April 19, 2016, the Court held a hearing to determine the proper construction of the
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`disputed terms in five Asserted Patents. The Court has considered the briefs and arguments.
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`(Dkt. Nos. 106, 110, and 111.) Based on the intrinsic and extrinsic evidence, the Court construes
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`the disputed terms in this Memorandum Opinion and Order. See Phillips v. AWH Corp., 415 F.3d
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`1303 (Fed. Cir. 2005); Teva Pharm. USA, Inc. v. Sandoz, Inc., 135 S. Ct. 831 (2015).
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`BACKGROUND AND THE ASSERTED PATENTS
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`Parthenon Unified Memory Architecture LLC (“PUMA”) brought this action against
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`Apple Inc. (“Apple”) alleging that Apple infringes U.S. Patent Nos. 5,812,789 (“the ’789
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`Patent”), 7,321,368 (“the ’368 Patent”), 7,542,045 (“the ’045 Patent”), 7,777,753 (“the ’753
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`Patent”), and 5,960,464 (“the ’464 Patent”) (collectively, “the Asserted Patents”). The ’789 and
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`another patent, U.S. Patent No. 6,058,459 (“the ’459 Patent”), were filed on the same day, have
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`similar specifications, and incorporate each other by reference. A number of patents resulted
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`from continuation applications of the ’459 Patent, including the’368 Patent, the ’045 Patent, and
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`1
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`the ’753 Patent.1 All five Asserted Patents were subject to claim construction orders issued by
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`this Court in (1) Parthenon Unified Memory Architecture, LLC v. HTC Corp., 2:14-cv-0690-
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`JRG-RSP, Dkt. No. 155 (E.D. Tex. July 30, 2015) (the “Parthenon I Order”), (2) Parthenon
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`Unified Memory Architecture, LLC v. Samsung Elecs. Co., Ltd., 2:14-cv-902-JRG-RSP, Dkt. No.
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`155 (E.D. Tex. Jan. 24, 2016) (the “Parthenon II Order”), and (3) Parthenon Unified Memory
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`Architecture, LLC v. ZTE Corp., 2:15-cv-0225-JRG-RSP, Dkt. No. 80 (E.D. Tex. Jan. 25, 2016)
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`(the “Parthenon III Order”) Furthermore, one additional Eastern District of Texas claim
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`construction order involved the ’789 Patent. STMicroelectronics, Inc. v. Motorola, Inc., 327 F.
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`Supp. 2d 687 (E.D. Tex. 2004).
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`In general, the ’789 Patent, the ’368 Patent, the ’045 Patent, and the ’753 Patent relate to
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`systems in which a first device (for example a processor) and a decoder/encoder share a common
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`memory. The ’789 Patent abstract recites:
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`An electronic system that contains a first device that requires a memory interface
`and video and/or audio decompression and/or compression device that shares a
`memory interface and memory with the first device while still permitting the
`video and/or audio decompression and/or compression device to operate in real
`time is disclosed.
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`’789 Patent Abstract. The ’368 Patent abstract recites:
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`An electronic system, an integrated circuit and a method for display are disclosed.
`The electronic system contains a first device, a memory and a video/audio
`compression/decompression device such as a decoder/encoder. The electronic
`system
`is configured
`to allow
`the
`first device and
`the video/audio
`compression/decompression device to share the memory. The electronic system
`may be included in a computer in which case the memory is a main memory.
`Memory access is accomplished by one or more memory interfaces, direct
`coupling of the memory to a bus, or direct coupling of the first device and
`decoder/encoder to a bus. An arbiter selectively provides access for the first
`device and/or the decoder/encoder to the memory. The arbiter may be
`monolithically integrated into a memory interface. The decoder may be a video
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`1 The specification of the ’464 Patent is not shared by the other Asserted Patents.
`2
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`decoder configured to comply with the MPEG-2 standard. The memory may store
`predicted images obtained from a preceding image.
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`’368 Patent Abstract.
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`
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`The ’464 Patent relates, generally, to a system whereby a decoder, which requires
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`contiguous blocks of memory, can utilize noncontiguous blocks of the system’s memory. The
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`’464 patent abstract recites:
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`A method and apparatus employing a memory management system that can be
`used with applications requiring a large contiguous block of memory, such as
`video decompression techniques (e.g., MPEG 2 decoding). The system operates
`with a computer and the computer's operating system to request and employ
`approximately 500 4-kilobyte pages in two or more noncontiguous blocks of the
`main memory to construct a contiguous 2-megabyte block of memory. The
`system can employ, on a single chip, a direct memory access engine, a
`microcontroller, a small block of optional memory, and a video decoder circuit.
`The microcontroller retains the blocks of multiple pages of the main memory, and
`the page descriptors of these blocks, so as to lock down these blocks of memory
`and prohibit the operating system or other applications from using them. The
`microcontroller requests the page descriptors for each of the blocks, and programs
`a lookup table or memory mapping system in the on-chip memory to form a
`contiguous block of memory. As a result, the video decoder circuit can perform
`operations on a 2-megabyte contiguous block of memory, where
`the
`microcontroller employs the lookup table to translate each 2-megabyte contiguous
`address requested by the video decoder circuit to its appropriate page in the main
`memory. As soon as the video decoding operations are complete, the
`microcontroller releases the blocks of multiple pages of memory back for use by
`the computer.
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`’464 Patent Abstract.
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`APPLICABLE LAW
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`1. Claim Construction
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`“It is a ‘bedrock principle’ of patent law that ‘the claims of a patent define the invention
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`to which the patentee is entitled the right to exclude.’” Phillips v. AWH Corp., 415 F.3d 1303,
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`1312 (Fed. Cir. 2005) (en banc) (quoting Innova/Pure Water Inc. v. Safari Water Filtration Sys.,
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`Inc., 381 F.3d 1111, 1115 (Fed. Cir. 2004)). To determine the meaning of the claims, courts start
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`by considering the intrinsic evidence. Id. at 1313; C.R. Bard, Inc. v. U.S. Surgical Corp., 388
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`F.3d 858, 861 (Fed. Cir. 2004); Bell Atl. Network Servs., Inc. v. Covad Commc’ns Grp., Inc., 262
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`F.3d 1258, 1267 (Fed. Cir. 2001). The intrinsic evidence includes the claims themselves, the
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`specification, and the prosecution history. Phillips, 415 F.3d at 1314; C.R. Bard, Inc., 388 F.3d at
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`861. Courts give claim terms their ordinary and accustomed meanings as understood by one of
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`ordinary skill in the art at the time of the invention in the context of the entire patent. Phillips,
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`415 F.3d at 1312–13; Alloc, Inc. v. International Trade Comm’n, 342 F.3d 1361, 1368 (Fed. Cir.
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`2003).
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`The claims themselves provide substantial guidance in determining the meaning of
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`particular claim terms. Phillips, 415 F.3d at 1314. First, a term’s context in the asserted claim
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`can be very instructive. Id. Other asserted or unasserted claims can also aid in determining the
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`claim’s meaning, because claim terms are typically used consistently throughout the patent. Id.
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`Differences among the claim terms can also assist in understanding a term’s meaning. Id. For
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`example, when a dependent claim adds a limitation to an independent claim, it is presumed that
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`the independent claim does not include the limitation. Id. at 1314–15.
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`“[C]laims ‘must be read in view of the specification, of which they are a part.’” Id.
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`(quoting Markman v. Westview Instruments, Inc., 52 F.3d 967, 979 (Fed. Cir. 1995) (en banc)).
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`“[T]he specification ‘is always highly relevant to the claim construction analysis. Usually, it is
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`dispositive; it is the single best guide to the meaning of a disputed term.’” Id. (quoting Vitronics
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`Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996)); Teleflex, Inc. v. Ficosa N. Am.
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`Corp., 299 F.3d 1313, 1325 (Fed. Cir. 2002). This is true because a patentee may define his own
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`terms, give a claim term a different meaning than the term would otherwise possess, or disclaim
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`or disavow the claim scope. Phillips, 415 F.3d at 1316. In these situations, the inventor’s
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`lexicography governs. Id. The specification may also resolve ambiguous claim terms “where the
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`ordinary and accustomed meaning of the words used in the claims lack sufficient clarity to
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`permit the scope of the claim to be ascertained from the words alone.” Teleflex, Inc., 299 F.3d at
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`1325. But, “‘[a]lthough the specification may aid the court in interpreting the meaning of
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`disputed claim language, particular embodiments and examples appearing in the specification
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`will not generally be read into the claims.’” Comark Commc’ns, Inc. v. Harris Corp., 156 F.3d
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`1182, 1187 (Fed. Cir. 1998) (quoting Constant v. Advanced Micro-Devices, Inc., 848 F.2d 1560,
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`1571 (Fed. Cir. 1988)); see also Phillips, 415 F.3d at 1323. The prosecution history is another
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`tool to supply the proper context for claim construction because a patent applicant may also
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`define a term in prosecuting the patent. Home Diagnostics, Inc., v. Lifescan, Inc., 381 F.3d 1352,
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`1356 (Fed. Cir. 2004) (“As in the case of the specification, a patent applicant may define a term
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`in prosecuting a patent.”).
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`Although extrinsic evidence can be useful, it is “‘less significant than the intrinsic record
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`in determining the legally operative meaning of claim language.’” Phillips, 415 F.3d at 1317
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`(quoting C.R. Bard, Inc., 388 F.3d at 862). Technical dictionaries and treatises may help a court
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`understand the underlying technology and the manner in which one skilled in the art might use
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`claim terms, but technical dictionaries and treatises may provide definitions that are too broad or
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`may not be indicative of how the term is used in the patent. Id. at 1318. Similarly, expert
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`testimony may aid a court in understanding the underlying technology and determining the
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`particular meaning of a term in the pertinent field, but an expert’s conclusory, unsupported
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`assertions as to a term’s definition are entirely unhelpful to a court. Id. Generally, extrinsic
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`evidence is “less reliable than the patent and its prosecution history in determining how to read
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`claim terms.” Id.
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`2. Claim Indefiniteness
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`
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`Patent claims must particularly point out and distinctly claim the subject matter regarded
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`as the invention. 35 U.S.C. § 112, ¶ 2. “[I]ndefiniteness is a question of law and in effect part of
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`claim construction.” ePlus, Inc. v. Lawson Software, Inc., 700 F.3d 509, 517 (Fed. Cir. 2012). A
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`party challenging the definiteness of a claim must show it is invalid by clear and convincing
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`evidence. Young v. Lumenis, Inc., 492 F.3d 1336, 1345 (Fed. Cir. 2007).
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`
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`The definiteness standard of 35 U.S.C. § 112, ¶ 2 requires that:
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`[A] patent’s claims, viewed in light of the specification and prosecution history,
`inform those skilled in the art about the scope of the invention with reasonable
`certainty. The definiteness requirement, so understood, mandates clarity, while
`recognizing that absolute precision is unattainable. The standard we adopt
`accords with opinions of this Court stating that “the certainty which the law
`requires in patents is not greater than is reasonable, having regard to their subject-
`matter.”
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`Nautilus, Inc. v. Biosig Instruments, Inc., 134 S. Ct. 2120, 2129–30 (2014) (internal citations
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`omitted).
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`3. Construing Claim Terms that Have Previously Been Construed by This Court or
`Other Courts
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`This is not the first time a Court in this District has construed some of the disputed terms.
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`The Parthenon I, II, and III Orders construed a number of the presently disputed terms and in
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`STMicroelectronics, Inc. v. Motorola, Inc., 327 F. Supp. 2d 687 (E.D. Tex. 2004) the Court
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`construed the ’789 Patent. These previous constructions do not control but can be instructive and
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`will, at times, provide part of the basis for the Court’s analysis. See Burns, Morris & Stewart Ltd.
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`P’ship v. Masonite Int’l Corp., 401 F. Supp. 2d 692, 697 (E.D. Tex. 2005) (holding a previous
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`construction may be instructive and provide the basis for the analysis, but is not binding,
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`particularly when there are new parties and arguments).
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`AGREED TERMS
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`The parties agreed to the following constructions. (Dkt. No. 94 at 1–2; Dkt. No. 106 at 6).
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`
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`Agreed Construction
`“a signal line or set of associated signal lines
`to which a number of devices are coupled and
`over which information may be transferred
`between them”
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`“convert the noncontiguous addresses to the
`contiguous addresses according to at least one
`mathematical operation”
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`“screen and its circuitry”
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`“an adapter that processes images for a display
`device”
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`“circuitry that uses a priority scheme to
`determine which requesting device will gain
`access”
`
`Term
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`“bus”
`
`’789 Patent claims 1, 13
`’368 Patent claims 1, 5, 7, 13, 19, 20, 23
`’045 Patent claims 1, 4, 5, 12, 15
`’753 Patent claims 1, 7
`“algorithmically translate the noncontiguous
`addresses to the contiguous addresses”
`
`’464 Patent claims 7, 22
`“display device”
`
`’368 Patent claims 1, 7, 13, 14, 20, 21
`’045 Patent claims 1, 4-6, 12, 13
`’753 Patent claims 1, 7
`“display adapter”
`
`’368 Patent claims 2, 3
`’045 Patent claim 2
`’753 Patent claim 3
`“arbiter”
`“arbitration circuit”
`“memory arbiter”
`“arbiter circuit”
`
`’789 patent: claims 1, 19
`’368 patent: claims 1, 7, 13, 17, 19, 20, 23
`’045 patent: claims 1, 4, 5, 9, 12, 15
`’753 patent: claims 1, 7
`
`
`DISPUTED TERMS
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`
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`1. Access Terms
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`“selectively providing access for the first device and the decoder to the memory” (’789
`Patent claim 1)
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`“controlling the access to said main memory” (’368 Patent claim 1; ’045 Patent claim 1)
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`“control access to the main memory” / “control access to the memory” (’753 Patent claims
`1, 7)
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`“controlling the access to the system memory” / “control access to the system memory”
`(’368 Patent claim 13; ’045 Patent claim 5)
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`PUMA’s Construction
`No construction necessary in view of parties’
`agreed construction of “arbiter.”
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`The primary dispute between the parties relates to whether the arbiter permits only one
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`Apple’s Construction
`“allowing/allow only one device to access the
`[main/system] memory at a time”
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`device to access memory at a time.
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`Positions of the Parties
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`
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`PUMA notes that all of the disputed terms relate to functions of the “arbiter,” which the
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`parties have agreed should be construed as “circuitry that uses a priority scheme to determine
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`which requesting device will gain access.” For example, claim 1 of the ’789 Patent recites “an
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`arbiter for selectively providing access for the first device and the decoder to the memory” and
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`claim 1 of the ’368 Patent recites “an arbiter . . . for controlling the access to the system
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`memory.”
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`
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`PUMA contends the priority scheme of the “arbiter” is not restricted to allowing only one
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`device to access the memory at a time. Rather, PUMA contends that, as agreed by the parties,
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`“arbitration” is only a “priority scheme to determine which requesting device will gain access.”
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`PUMA cites to a prior art patent and contends that a dual-port memory which includes two
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`independent addresses and data paths for allowing two devices to access the memory at the same
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`time was known in the art. PUMA contends the patentee did not disclaim the use of this type of
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`memory. (See Dkt. No. 106 at 24.)
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`
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`Apple contends that the full term must be considered and points to claim 1 of the ’368
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`Patent as an example. It recites: “an arbiter circuit coupled to both the microprocessor system
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`and the decoder for controlling access to said main memory by the decoder and the
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`microprocessor.” Apple contends that, as claimed, the “arbiter” is coupled to two devices and
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`controls the access of those devices to the memory. Apple contends that the only plausible
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`reading of the claim is that both devices cannot access memory at the same time. (Dkt. No. 110
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`at 4.)
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`
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`Apple contends that in four IPR proceedings, PUMA disclaimed “arbiters” that allowed
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`more than one device at a time to access the memory to overcome the Rathnam and Bowes
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`references. As an example, Apple points to the arguments made in the ’368 Patent IPR
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`proceeding in which PUMA stated “Rathnam does not disclose an arbiter that controls access to
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`the SDRAM (i.e., the alleged main/system memory).” (Dkt. No. 110 Ex. M at 31.) Apple
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`contends PUMA specifically argued that the ’368 Patent embodiments “allow multiple devices to
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`use the bus even while only one device, e.g. the decoder, has access to main memory.” (Id. at
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`32.) The full passage in question is:
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`Controlling access to a bus that connects multiple system components is not the
`same as controlling access to the SDRAM (i.e., the alleged main/system
`memory). The distinction between accessing the bus and accessing the
`main/system memory is evident from the disclosure of the ’368 Patent which
`allows, for example, the video decoder to use part of the available bandwidth of
`the bus to access the shared memory while the remaining bus bandwidth remains
`available to other components. The ’368 patent specification recognizes benefit of
`controlling access to the memory as opposed to the memory bus. See, e.g., ’368
`Pat. [Ex. 1001], 8:47-59 (“In the preferred embodiment, even during decoding
`and encoding, the decoder/encoder 80 does not always use the entire required
`bandwidth. Since the fast bus 70 has a bandwidth a little less than twice the size
`of the required bandwidth, the decoder/encoder 80 uses at most 60% of the
`bandwidth of
`the fast bus 70
`. . . . In
`the preferred embodiment
`the
`decoder/encoder typically will be using less than 40% of the bandwidth of the fast
`bus 70. This frees up the remaining bandwidth to be used by the other devices
`with which the decoder/encoder 80 is sharing the memory 50”). By controlling
`access to the main memory, rather than the memory bus, embodiments of the ’368
`patent allow multiple devices to use the bus even while only one device, e.g. the
`decoder, has access to the main memory.
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`(Id. at 31–32 (emphasis in original).) Apple contends this statement disclaims more than one
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`device at a time from accessing the memory and contends this is what is meant by “controlling
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`access.” (Dkt. No. 110 at 5–6.)
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`
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`Apple also contends the prosecution of the ’368 Patent contains a disclaimer:
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`The arbiter 82 sends out control signals to determine which of the devices is
`permitted to access the memory via the fast bus 70, Page 20, lines 17-28. Thus
`while both of the devices are coupled to the memory 50, the control signal which
`gives them access to the memory 50 comes via the arbiter 82 which grants
`permission to any devices attempting to access the memory 50 and blocks
`permission to the other devices.
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`(Dkt. 110 Ex. X, Appellant’s Brief at 4 (emphasis added).) Apple contends this makes clear that
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`the “arbiter” determines which of the devices gets access to the memory and blocks access by the
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`other devices.
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`
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`Apple further contends that the plain language of the claims conforms to its construction
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`of the disputed terms. Apple contends that if both the microprocessor and the decoder could
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`access the memory at the same time, there would be no need for the limitation “controlling the
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`access to said main memory by the decoder and the microprocessor.” Apple contends in such a
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`case no arbitration would occur.
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`
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`Apple also asserts that in the specification, every disclosure regarding the “arbiter” only
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`allows one device to access the memory at a time. Apple cites to the ’368 Patent specification in
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`support.
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`Referring to FIG. 2, the operation of the arbiter 82 during a memory request will
`now be described. During the operation the decoder/encoder 80, the first device
`42, and the refresh logic 58, if it is present, request access to memory through the
`arbiter 82. There may be other devices that request access to the memory 50
`through the arbiter. The arbiter 82 determines which of the devices gets access
`to the memory.
`…
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`It is also determined if two requests are issued simultaneously. This can be
`performed either before or after determining the state of the arbiter. Access to the
`memory is determined according to the following chart.
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`’368 patent 13:6–3 (emphasis added). Apple also points to the ’789 Patent specification in
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`
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`support.
`
`In the preferred embodiment of the invention the shared memory interface
`contains an arbiter. The arbiter and DMA engines of the video and/or audio
`decompression and/or compression device and of the first device are configured
`to arbitrate between the two devices when one of them is requesting access to the
`memory. This allows the use of one memory interface to control the access of
`both the video and/or audio decompression and/or compression device and the
`first device to the memory.
`
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`’789 patent, 4:2–11. Apple states that PUMA fails to point to a single portion of the specification
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`that indicates that the “arbiter” permits multiple devices to access memory at the same time.
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`(Dkt. No. 110 at 8.)
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`
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`Apple finally contends that extrinsic evidence also supports its position. In particular,
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`Apple points to dictionaries which define “arbiter” as “[a] functional module that accepts bus
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`requests from requester modules and grants control of the data transfer bus (DTB) to one
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`requester at a time.” Dictionaries also define “arbitration” as “[t]he process of determining which
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`requesting device will gain access to a resource.” (Dkt. No. 110 Ex. Q at 43.)
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`Apple contends PUMA’s extrinsic evidence relating to dual-port memories is irrelevant
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`as it does not relate to “arbiters.” Furthermore, Apple states that the claims relate to a single
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`memory bus, not multiple data and address buses coupled to a dual ported memory. (Dkt. No.
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`110 at 8.)
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`
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`Apple further objects to PUMA’s contention that the agreed construction of “arbiter”
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`controls on the issue. Apple contends the issue is not what an “arbiter” is, but what the “arbiter”
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`does, specifically scope of the claim language that describes the function of the “arbiter.”
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`Furthermore, Apple contends its proposed construction of the limitations following “arbiter”
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`conforms to the parties’ agreed construction of “arbiter” as they agreed an “arbiter” includes a
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`“priority scheme to determine which requesting device will gain access.”
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`
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`In reply, PUMA contends the IPR responses do not support Apple’s position. PUMA
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`contends that in the IPR responses, the distinction made between the claimed invention and the
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`prior art was not between single devices accessing memory and multiple devices accessing
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`memory. Rather, PUMA contends the IPR responses focused on the fact that prior art “arbiter”
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`controlled access to the bus, while the claims required the “arbiter” to control access to the
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`memory. (Dkt. No. 111 at 9.)
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`As to the primary sentence relied on by Apple, the last sentence in the IPR response
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`above, PUMA contends that the language quoted by Apple just illustrates one difference between
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`accessing the bus and accessing the main memory. That is, in the claimed invention, unlike in the
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`prior art, multiple devices can access the bus while one device is accessing the memory. PUMA
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`further contends it never characterized Rathnam as allowing multiple devices to access the main
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`memory at the same time or took any position on that issue. (Dkt. No. 111 at 10.)
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`Case 2:15-cv-00621-JRG-RSP Document 162 Filed 06/17/16 Page 13 of 50 PageID #: 7047
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`As to the quote from the ’368 Patent prosecution, PUMA contends that it is not an
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`unequivocal disclaimer. PUMA contends the quote comes from a general background discussion
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`of the technology and was not made with regard to any cited reference. In addition, PUMA
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`contends none of the cited references had anything to do with whether or not multiple devices
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`could access memory at the same time. PUMA contends that, in contrast, the applicant
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`distinguished Wasserman by noting it failed to teach “a memory arbiter coupled to both a
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`microprocessor system and decoder for controlling access to the main memory.” (Dkt. No. 110
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`Ex. X at 7.)
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`Analysis
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`At the hearing, the Court proposed a construction for “selectively providing access for the
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`first device and the decoder to memory.” The Court proposed construing that term to mean
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`“allowing access for only one of the first device or the decoder to the memory.” Apple agreed
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`with the proposed construction. (Dkt. No. 120 at 6–7.) PUMA disagreed with the proposed
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`construction. For the “controlling access” terms, the Court proposed “no construction necessary.”
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`Apple disagreed with the proposed construction. (Id.)
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`Controlling access terms
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`The Court disagrees with Apple’s argument that its proposed constructions are supported
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`by the IPR responses. The IPR responses when read in context show the distinction identified by
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`Apple in its briefs is not the distinction the patent owner identified between the claimed
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`invention and the prior art.
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`For example, the Patent Owner’s Preliminary Response for the ’368 Patent (Dkt. No. 110
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`Ex. M) discusses the differences between the claimed invention and Rathnam. The IPR response
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`states that the distinction between the claimed invention and Rathnam is that “Rathnam controls
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`access to the internal bus, not access to the SDRAM (i.e., the alleged main/system memory).”
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`(Dkt. No. 110 Ex. M at 30 (emphasis in original).) Disassembled, this statement shows the patent
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`owner distinguished the claimed invention from Rathnam by pointing out that the “arbiter” in
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`Rantham “control[led] access to the internal bus” while the “arbiter” in the claimed invention
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`“control[led] . . . access to the SDRAM.”
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`The second paragraph also illustrates this distinction. The second paragraph states:
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`Therefore, Rathnam does not disclose an arbiter that controls access to the
`SDRAM (i.e., the alleged main/system memory). Instead, the central arbiter of
`Rathnam controls access to the internal bus that connects many different
`components, including peripherals and the PCI bus together.
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`(Id. at 31.)
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`Likewise, the third paragraph draws the same distinction:
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`Controlling access to a bus that connects multiple system components is not the
`same as controlling access to the SDRAM (i.e., the alleged main/system
`memory). The distinction between accessing the bus and accessing the
`main/system memory is evident from the disclosure of the ’368 Patent which
`allows, for example, the video decoder to use part of the available bandwidth of
`the bus to access the shared memory while the remaining bus bandwidth remains
`available to other components. The ’368 patent specification recognizes benefit of
`controlling access to the memory as opposed to the memory bus.
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`(Id. (emphasis in original).)
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`The fourth paragraph makes the same distinction as the three paragraphs above. It also
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`emphasizes the patent owner’s position that Rathnam does not disclose a limitation that requires
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`the arbiter to “control[] access to the main/system memory.”
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`The distinction between controlling access to the memory and controlling access
`to the bus is also evident from the claims of the ’368 Patent. Specifically,
`independent claims 1, 5, and 13 recite an arbiter that controls access to the
`“main/system memory.” In contrast, independent claims 7 and 20 recite an arbiter
`that controls access to the bus.
`. . .
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`Therefore, Rathnam’s alleged disclosure of a central arbiter that controls access to
`an internal bus does not satisfy the limitation of independent claims 1, 5, and 13
`which recite an arbiter that controls access to the main/system memory.
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`(Id. 31–31 (emphasis added).)
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`In addition to the IPR responses, Apple points to the intrinsic record to support its
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`proposed construction. The Court finds the intrinsic record does not support Apple’s narrow
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`construction.
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`The plain meaning of “arbiter” does not provide that an “arbiter” allows only one device
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`at a time to access a memory. The plain meaning provides that an “arbiter” is a device that can
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`execute “any” priority scheme for determining access. (’368 Patent 13:54–55.) The scheme must
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`ensure, however, that the “decoder/encoder 80 gets access to the memory 50 often enough and
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`for enough of a burst length to operate properly, yet not [so often as to] starve the other devices
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`sharing the memory.” (’368 Patent 13:55–60.) Based on this disclosure, the Court finds that an
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`“arbiter” falls within the plain meaning of the term if the “arbiter” possesses “any” priority
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`scheme that allows a “decoder” to gain access to a memory without “starving” the other devices
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`in the system. This plain meaning includes an “arbiter” with a scheme that allows more than one
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`device to access the memory. An “arbiter” can possess this scheme if the memory being accessed
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`can support access by more than one device.
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`Apple has not identified any definition or disclaimer that excludes an “arbiter” with a
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`priority scheme that allows more than one device at a time to access the memory. Apple notes
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`the specification discloses embodiments of “arbiters” that allow one device at a time to access
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`the memory. But Apple fails to note that the specification also teaches “arbiters” can have “any
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`priority scheme.”
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`The Court finds that its construction of the “controlling access” terms should focus on the
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`idea that an “arbiter” can have “any priority scheme” that achieves the “controlling” function.
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`The Court finds that its construction should not focus on the function of the memory and should
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`not assume that a memory only allows access by one device at a time because the specification
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`potentially discloses only this type of memory. Because the Court does not assume that a
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`memory can only allow access by one device at a time, the Court does construe the disputed
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`terms to exclude an “arbiter” with a priority scheme that can determine access to a memory that
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`allows access