UNITED STATES PATENT AND TRADEMARK OFFICE
`
`———————
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`———————
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`
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`Parthenon Unified Memory Architecture LLC,
`Patent Owner
`
`———————
`
`
`
`PETITION FOR INTER PARTES REVIEW
`
`OF
`
`U.S. PATENT NO. 7,542,045
`
`
`
`
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`
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`

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`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
`
`TABLE OF CONTENTS
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`I.  MANDATORY NOTICES ............................................................................... 1 
`
`A.  Real Party-in-Interest ................................................................................ 1 
`
`B.  Related Matters ......................................................................................... 1 
`
`C.  Lead and Back-up Counsel and Service Information .............................. 2 
`
`II.  GROUNDS FOR STANDING .......................................................................... 2 
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`III.  INTRODUCTION; RELIEF REQUESTED ..................................................... 3 
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`IV.  REASONS FOR THE REQUESTED RELIEF ................................................ 4 
`
`A.  The ’045 Patent ......................................................................................... 4 
`
`1.  Overview .......................................................................................... 4 
`
`2. 
`
`Prosecution History .......................................................................... 7 
`
`B. 
`
`Identification of Challenges ..................................................................... 8 
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`1.  Challenged Claims ........................................................................... 8 
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`2. 
`
`Statutory Ground for Challenges ..................................................... 8 
`
`3.  Note Regarding Page Citations ........................................................ 9 
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`4.  Redundancy ...................................................................................... 9 
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`C.  Claim Construction ................................................................................. 10 
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`1. 
`
`“decoder” (Claim 12 and 15-17 ) and “video decoder”
`(Claims 1, 4, 5, 7, 9, and 10 ) ......................................................... 11 
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`2. 
`
`“fast bus” (Claim 4) ....................................................................... 12 
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`3.  Other Claim Terms ......................................................................... 13 
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`D. 
`
`Identification of How the Claims Are Unpatentable .............................. 14 
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`

`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
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`1.  Challenge #1: Claims 1, 4, 5, 7, 10, 12, 16, and 17 are
`obvious over Bowes, Datasheet, and Artieri .................................. 14 
`
`i. 
`
`Reasons to Combine - Bowes, Datasheet, and Artieri ............ 16 
`
`ii.  Detailed Analysis .................................................................... 18 
`
`2.  Challenge #2: Claim 9 and 15 are obvious over Bowes,
`Datasheet, Artieri, and Gove .......................................................... 58 
`
`i. 
`
`Reasons to Further Combine Gove ......................................... 59 
`
`ii.  Detailed Analysis .................................................................... 60 
`
`V.  Conclusion ....................................................................................................... 63 
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`

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`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
`
`
`I. MANDATORY NOTICES
`A. Real Party-in-Interest
`The real party-in-interest is Apple Inc.
`
`B. Related Matters
`As of the filing date of this petition, the ’045 Patent has been asserted in:
`
` Parthenon Unified Memory Architecture LLC v. Huawei Techs. Co., Ltd. et
`
`al., No. 2:14-cv-00687-JRG-RSP (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. Motorola Mobility, Inc.,
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`No. 2:14-cv-00689-JRG-RSP (E.D. Tex.);
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` Parthenon Unified Memory Architecture LLC v. HTC Corp. et al., No.
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`2:14-cv-00690-RSP (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. LG Elecs., Inc. et al., No.
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`2:14-cv-00691-JRG-RSP (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. Samsung Elecs. Co. Ltd. et
`
`al., No. 2:14-cv-00902-JRG-RSP (E.D. Tex.);
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` Parthenon Unified Memory Architecture LLC v. Qualcomm Inc. et al., No.
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`2:14-cv-00930-JRG-RSP (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. ZTE Corp. et al., No. 2:15-
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`cv-00225-JRG-RSP (E.D. Tex.); and
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` Parthenon Unified Memory Architecture LLC v. Apple, Inc., No. 2:15-cv-
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`00621-JRG-RSP (E.D. Tex.).
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`1
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`

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`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
`
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`Additionally, the ’045 Patent has been challenged in the following inter partes
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`review proceedings:
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`
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` IPR2015-01502 and IPR2016-00667.
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`Apple Inc. is not a real party-in-interest in IPR2015-01502 or IPR2016-00667.
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`C. Lead and Back-up Counsel and Service Information
`
`Lead Counsel
`Phone: (512) 867-8457
`David W O’Brien
`Fax: (214) 200-0853
`HAYNES AND BOONE, LLP
`david.obrien.ipr@haynesboone.com
`2323 Victory Ave. Suite 700
`USPTO Reg. No. 40,107
`Dallas, TX 75219
`
`
`
`
`Phone: (214) 651-5116
`Fax: (214) 200-0853
`andy.ehmke.ipr@haynesboone.com
`USPTO Reg. No. 50,271
`
`
`Back-up Counsel
`Andrew S. Ehmke
`HAYNES AND BOONE, LLP
`2323 Victory Ave. Suite 700
`Dallas, TX 75219
`
`
`
`Please address all correspondence to lead and back-up counsel. Petitioner
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`consents to electronic service by email to the addresses listed above.
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`II. GROUNDS FOR STANDING
`Petitioner certifies that the ’045 Patent is eligible for inter partes review
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`and that Petitioner is not barred or estopped from requesting inter partes review
`
`challenging the patent claims on the grounds identified in this petition. Petitioner
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`was served with a complaint asserting infringement of the ’045 Patent on June 5,
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`2015. Petitioner has not filed a civil action challenging the validity of any claim of
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`the ’045 Patent.
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`2
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`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
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`INTRODUCTION; RELIEF REQUESTED
`
`
`III.
`
`U.S. Patent No. 7,542,045 (“the ’045 Patent,” APL1001) is generally
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`directed to a system having a memory shared between a video decoder and
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`another device, such as a central processing unit (CPU) and describes arbitrating
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`between the devices for access to the shared memory. See APL1001, Abstract,
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`4:64-5:7. The ’045 Patent alleges that conventionally a video decoder would
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`have its own dedicated memory. APL1001, 2:43-51, 3:14-15, 4:43-45. The ’045
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`Patent proposes that this dedicated memory increases costs and that the dedicated
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`memory would be “unused most of the time.” APL1001, 4:48-52. According to
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`the ’045 Patent, an advantage of its invention was cost reduction due to the fact
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`that the video decoder did not need its own dedicated memory but could share
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`memory with the other device and still operate in real time. See APL1001, 5:47-
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`51.
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`However, before the priority date of the ’045 Patent, others had recognized
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`the cost concerns in similar systems, had proposed to use a shared memory in lieu
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`of a dedicated memory, and had developed arbitration schemes for sharing this
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`memory while supporting real time operation. APL1003, ¶¶23-32. For example,
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`Bowes (APL1005) recognized the benefits of allowing its digital signal processor
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`(DSP) to use shared main memory by arbitrating access to the shared memory
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`among the DSP and other devices, including a CPU. APL1005, 6:22-37.
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`
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`3
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`

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`
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`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
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`The evidence in this petition demonstrates that claims 1, 4, 5, 7, 9, 10, 12,
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`and 15-17 of the ’045 Patent are unpatentable under pre-AIA 35 U.S.C. § 103.
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`Accordingly, Apple Inc. (“Petitioner”) respectfully requests that the Patent Trial
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`and Appeal Board (“Board”) institute trial for inter partes review of the
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`aforementioned claims and cancel each of those claims as invalid.
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`IV. REASONS FOR THE REQUESTED RELIEF
`As explained below and in the declaration of Petitioner’s expert, Robert
`
`Colwell, Ph.D., the concepts claimed in the ’045 Patent were neither new nor non-
`
`obvious. This Petition explains where each element of claims 1, 4, 5, 7, 9, 10, 12,
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`and 15-17 is found in the prior art and why the claims would have been obvious to
`
`one of skill in the art before the earliest claimed priority date of the ’045 Patent. A
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`full statement of reasons for the requested relief follows.
`
`A.
`
`’045 Patent
`1. Overview
`The ’045 Patent generally describes an electronic system with a first device
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`and a “video and/or audio decompression and/or compression device” that share a
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`memory interface in a manner that permits the decompression/compression device
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`to operate in real time. APL1001, Abstract, 4:64-66. “An arbiter selectively
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`provides access for the first device and/or the decoder/encoder to the memory.”
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`APL1001, Abstract. To fit digital media, such as movies, onto a “conventional
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`recording medium,” such as a CD, the ’045 Patent recognizes it was already
`4
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`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
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`known to “compress video and audio sequences before they are transmitted or
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`stored.” APL1001, 1:44-51. For compression/decompression, “MPEG standards
`
`are currently well accepted standards for one way communication. H.261, and
`
`H.263 are currently well accepted standards for video telephony.” APL1001, 2:6-
`
`9. The ’045 Patent indicates that electronic systems added decoders to computer
`
`systems to “allow them to display compressed sequences.” APL1001, 2:14-17.
`
`The ’045 Patent indicates that a decoder for MPEG sequences “typically…
`
`requires a 2 Mbyte memory,” and that such memory was typically “dedicated to
`
`the MPEG decoder 10 and increases the price of adding a decoder 10 to the
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`electronic system.” APL1001, 2:46-49. The ’045 Patent views this dedicated
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`memory as a problem that increased cost of the decoder. APL1001, 2:49-51. The
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`’045 Patent allegedly addressed this problem by having the “video and/or audio
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`decompression and/or compression device share[] a memory interface and the
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`memory with the first device.” APL1001, 5:2-3. Figure 2 of the ’045 Patent
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`illustrates an electronic system containing a device (“first device”) having a
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`shared memory with a decoder:
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`
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`5
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`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
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`APL1001, ’045 Patent, FIG. 2
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`
`
`The ’045 Patent explains that its proposed solution results in cost reduction “due
`
`to the fact that the video and/or audio decompression and/or compression device
`
`does not need its own dedicated memory but can share a memory with another
`
`device and still operate in real time.” APL1001, 5:48-51.
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`The ’045 Patent further explains that the system of FIG. 2 includes an
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`arbiter, whereby requests to obtain access to the memory are granted based on a
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`priority scheme, which “can be any priority scheme that ensures that the
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`decoder/encoder 80 gets access to the memory 50 often enough and for enough of
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`6
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`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
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`a burst length to operate properly, yet not starve the other devices sharing the
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`memory.” APL1001, 13:31-36.
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`
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`As discussed below in more detail, the system presented in the ’045
`
`Patent—sharing a memory between multiple devices and arbitrating access thereto
`
`between the devices—was well known in the art well before the ’045 Patent’s
`
`earliest alleged priority date.
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`Prosecution History
`
`2.
`The ’045 Patent issued on June 2, 2009, from an application which claims
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`priority through various continuations to Application No. 08/702,910, now U.S.
`
`Patent No. 6,058,459, which was filed on Aug. 26, 1996.
`
`The only rejection of the claims during the prosecution of Application No.
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`11/956,165, which led to the ’045 Patent, was a double patenting rejection
`
`overcome by terminal disclaimer. The Examiner issued a Notice of Allowance
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`stating that the prior art of record did not teach “an arbiter circuit coupled to both
`
`the microprocessor system and the video decoder for controlling access to the
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`main memory by the video decoder and the microprocessor.” APL1002, p. 251.
`
`As illustrated herein, Bowes provides an arbiter circuit that performs just this
`
`function. Bowes was not considered by the Examiner when examining the claims
`
`of the ’045 Patent.
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`
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`7
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`

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`
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`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
`
`B.
`
`Identification of Challenges
`1.
`Claims 1, 4, 5, 7, 9, 10, 12, and 15-17 of the ’045 Patent are challenged.
`
`Challenged Claims
`
`Statutory Ground for Challenges
`
`2.
`Challenge #1: Claims 1, 4, 5, 7, 10, 12, 16, and 17 are obvious under 35
`
`U.S.C. §103 over US Pat No. 5,546,547 to Bowes et al. (“Bowes”) in view of
`
`“AT&T DSP3210 Digital Signal Processor The Multimedia Solution[,]” Data
`
`Sheet March 1993 (“Datasheet”) and European Patent Application Publication EP
`
`0626653 A1 naming Artieri (“Artieri”).
`
`Bowes was filed January 28, 1994, issued August 13, 1996, and for
`
`purposes of this Petition is prior art to the ’045 Patent at least under (pre-AIA) 35
`
`U.S.C. §§102(a) and (e). Datasheet bears a date of March 1993 and a 1993
`
`copyright notice (see APL1006, pp. 1, 40) and was publicly available at least as of
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`January 17, 1994 when the document included as APL1006 was cited in a third
`
`party prior art submission to the USPTO (APL1011, p. 128). Datasheet is, for
`
`purposes of this Petition, prior art to the ’045 Patent at least under (pre-AIA) 35
`
`U.S.C. §102(b). Artieri was published November 20, 1994 in the French language
`
`and thus, for the purposes of this Petition, is prior art to the ’045 Patent at least
`
`under (pre-AIA) 35 U.S.C. §102(b). In compliance with 37 C.F.R. §42.63(b), a
`
`copy of the French-language document, an English translation, and an affidavit
`
`attesting to the accuracy of the translation are provided as Exhibit 1007.
`8
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`

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`
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`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
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`Challenge #2: Claims 9 and 15 are invalid under 35 U.S.C §103 over
`
`Bowes in view of Datasheet, Artieri and further in view of “The MVP: A Highly-
`
`Integrated Video Compression Chip,” R.J. Gove, Proceedings of the IEEE Data
`
`Compression Conference (DCC ’94), pp. 215-224 (“Gove,” APL1008).
`
`Gove was included as part of proceedings of the Data Compression
`
`Conference held March 29-31, 1994, and as such was publicly available at least as
`
`of March 29, 1994 as confirmed by the Date of the Publication indicated by the
`
`copyright registration records of the U.S. Copyright Office. See APL1015. Gove
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`is thus, for purposes of this Petition, prior art to the ’045 Patent at least under (pre-
`
`AIA) 35 U.S.C. §102(b).
`
`Note Regarding Page Citations
`
`3.
`For exhibits that include suitable page, column, or paragraph numbers in
`
`their original publication, Petitioner’s citations are to those original page, column,
`
`or paragraph numbers and not to the page numbers added for compliance with 37
`
`CFR 42.63(d)(2)(ii).
`
`4.
`Redundancy
`The ’045 Patent is currently the subject of additional inter partes review
`
`proceedings, IPR2015-01502 (instituted) and IPR2016-00667 (pre-institution
`
`stage). Apple is not a real party-in-interest in either of these proceedings and has
`
`no control over the filings. Moreover, Apple’s interests are different than those of
`
`
`
`9
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`

`
`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
`
`
`the IPR2015-01502 and IPR2016-00667 petitioners. See Sony Mobile Comm.
`
`(USA) Inc., v. E-Watch, Inc., IPR2015-00401, Paper 13 at 9 (PTAB 2015)
`
`(dismissing Patent Owner’s §325(d) arguments citing the “need to be cognizant of
`
`the interests of other petitioners”).
`
`More importantly, the challenges presented in the instant petition rely on
`
`different prior art combinations, different arguments regarding the asserted
`
`prior art, and different expert declaration testimony than those relied upon in
`
`IPR2015-01502 and IPR2016-00667. See, e.g., Nestle USA, Inc., v. Steuben
`
`Foods, Inc., IPR2014-01235, Paper 12 at 7 (PTAB 2014) (declining to deny
`
`petition under §325(d) where petition relied on “combination of references
`
`previously not considered and [was] supported by a declaration previously not
`
`considered”); see also Tandus Flooring, Inc. v. Interface, Inc., IPR2013-00333,
`
`Paper 16 at 6 (PTAB 2013) (declining to deny petition under §325(d) where
`
`petitioner presented new declaration evidence). Accordingly, because the instant
`
`petition presents different prior art and arguments, it falls outside of the scope of
`
`§325(d).
`
`C. Claim Construction
`In inter partes review, the Board applies the broadest reasonable
`
`construction in light of the specification to claims of an unexpired patent. See 37
`
`C.F.R. §42.100(b). Under the broadest reasonable construction, claim terms are
`
`
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`10
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`

`
`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
`
`
`given their ordinary and accustomed meaning as would be understood by one of
`
`ordinary skill in the art in the context of the entire disclosure. In re Translogic
`
`Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). However, patent claims, if
`
`expiring prior to a final decision by the Board, are typically construed by the
`
`standard applied in the district courts by applying the principles set forth in
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`Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005). See, e.g., 37 C.F.R.
`
`§42.108(c). Under this standard, the claim terms are given their ordinary and
`
`accustomed meanings as understood by one having ordinary skill in the art at the
`
`time of the invention in the context of the entire patent, considering intrinsic
`
`evidence (the claims, the specification, and the prosecution history), and extrinsic
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`evidence (technical dictionaries, treatises, etc.) to a lesser extent.
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`Petitioner believes that the ’045 Patent will expire during pendency of the
`
`requested inter partes review proceeding. Accordingly, the constructions
`
`proposed herein are consistent with both standards.
`
`1.
`
` “decoder” (Claim 12 and 15-17) and “video decoder”
`(Claims 1, 4, 5, 7, 9, and 10)
`
`“[D]ecoder” is found in independent claim 12 as well as in the detailed
`
`description. The ’045 Patent sets forth special meaning for “decoder” as follows:
`
`“[t]he resulting bitstream is decoded by a video and/or audio decompression
`
`device (hereinafter decoder) before the video and/or audio sequence is
`
`displayed.” APL1001, 1:65-2:1 (emphasis added). The detailed description
`
`
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`11
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`

`
`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
`
`
`continues: “[a]ny conventional decoder including a decoder complying to the
`
`MPEG-1, MPEG-2, H.261, or H.261 standards, or any combination of them, of
`
`any conventional standard can be used as the decoder/encoder.” APL1001, 15:30-
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`33. In context provided by claim 12 itself, the recited decoder is necessarily a
`
`video decoder in that, the claim recites that the decoder is coupled to a bus “for
`
`receiving encoded video images and for outputting data for displaying decoded
`
`video images ….” APL1001, 16:57-59. Independent claims 1, 4, and 5
`
`specifically recite a “video decoder.”
`
`Based on the foregoing, and as confirmed by Dr. Colwell, for the purposes
`
`of the invalidity analysis found in this Petition, “decoder” in the context of claims
`
`12 and 15-17 and “video decoder” in the context of claims 1, 4, 5, 7, 9, and 10
`
`means video decompression device. APL1003, ¶¶38-42.
`
`“fast bus” (Claim 4)
`
`2.
`The ’045 Patent identifies several known bus architectures as exemplary
`
`“fast bus[es]” – “a fast bus (such as a memory bus, a PCI– “Peripheral Component
`
`Interconnect”–bus, a VLB – “VESA (Video Electronics Standards Association)
`
`Local Bus”, or an AGP– “Advanced Graphics Port”– bus, or any bus having a
`
`bandwidth sufficient to allow the system to operate in real time)[.]” APL1001,
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`5:26-31; APL1003, ¶¶43-44. More generally, the ’045 Patent describes a “fast
`
`bus” as “any bus having a bandwidth sufficient to allow the system to operate in
`
`
`
`12
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`

`
`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
`
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`real time.” APL1001, 5:26-31 (Emphasis added); see also 7:51-58. For the
`
`purposes of invalidity analysis in this Petition only,1 “fast bus” is any bus having a
`
`bandwidth sufficient to allow the system to operate in real time. APL1003, ¶¶43-
`
`44.
`
`3. Other Claim Terms
`For completeness of the record relative to 37 CFR 42.104(b)(2), Petitioner
`
`notes the Joint Claim Construction and Prehearing Statement (APL1014), which
`
`identifies several terms to which construction has been agreed between parties.
`
`Unless otherwise noted, these agreed constructions are applied in the present
`
`invalidity analysis and include “bus,” “display device,” “arbiter,” “arbiter circuit,”
`
`and “memory arbiter.” APL1014, p. 1-2. See APL1003, ¶¶45-46. With regard to
`
`
`1 The Patent Owner has argued for a similar construction, and the Board has, in
`
`an already pending inter partes review of the ’045 Patent, adopted this
`
`construction. APL1014, p. 7; APL1012, p. 11. For avoidance of doubt, the
`
`term, “fast bus,” is susceptible to challenge in other fora as indefinite, and the
`
`’045 Patent specification’s description of “real time” arguably fails to provide
`
`sufficient detail to inform with clarity one of ordinary scope in the art as to its
`
`scope. Nothing herein shall be taken as waiver of such issues in other fora or
`
`as an affirmation of definiteness by the Petitioner.
`
`
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`13
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`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
`
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`the terms “arbiter,” “arbiter circuit,” and “memory arbiter,” Petitioner notes2 the
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`import of the agreed constructions in the invalidity analysis that follows.
`
`D.
`
`Identification of How the Claims Are Unpatentable
`1.
`
`Challenge #1: Claims 1, 4, 5, 7, 10, 12, 16, and 17 are
`obvious over Bowes, Datasheet, and Artieri
`
`
`
`Bowes describes an arbitration scheme for a computer system in which a
`
`digital signal processor (DSP) resides on a system’s memory bus without
`
`requiring memory dedicated to the DSP. APL1005, Abstract. Bowes describes
`
`multiple “bus masters” coupled to the common memory bus. APL1005, 2:52-3:2,
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`4:15-17. Bowes’ examples of “bus masters” include “the CPU, the DSP, the I/O
`
`interface and the NuBus controller,” each of which operates on data stored in main
`
`memory subsystem 14. APL1005, 6:21-25, 7:66-67; APL1003, ¶¶47-54. To
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`accommodate various potential bus masters, Bowes provides a memory controller
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`and arbiter (MCA) 200 that arbitrates access to memory bus 110 according to a
`
`priority scheme. APL1005, 7:64-8:10; Figure 3. Bowes indicates that its DSP,
`
`which can be programmed for image processing, resides on the system’s memory
`
`bus and operates from main memory. APL1005, 6:33-35; APL1003, ¶¶50, 53-545,
`
`88.
`
`
`2 See infra notes 3, 5, 8 and 9.
`
`
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`14
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`Petition for Inter Partes Review of U.S. Patent No. 7,542,045
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`Bowes’ system includes a DSP designed for multimedia applications.
`
`
`
`
`APL1006, p. 1; APL1003, ¶¶53-59. Bowes indicates that, in one embodiment,
`
`the DSP may be an AT&T DSP3210 (“DSP3210”) digital signal processor.
`
`APL1005, 6:28-30. Datasheet shows a “typical system” for a DSP3210 that
`
`resembles Bowes’ system in that the DSP3210 is coupled to a system bus and
`
`accesses system memory. APL1006, p. 4, Figure 2; APL1003, ¶57. Datasheet
`
`confirms that a “primary benefit of this system architecture is the DSP’s ability to
`
`access program and data from system memory without host intervention.
`
`Furthermore, expensive local SRAM is replaced by the computer’s existing
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`system memory.” APL1006, 4, col. 1. Notably, the DSP3210 in Bowes’ system is
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`programmed to perform “image processing.” APL1005, 6:34.
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`Artieri discloses processing circuitry “for decoding an image encoded
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`according to an MPEG standard” for use in a “[s]ystem for processing images.”
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`APL1007, pp. 1-2. Like Bowes, Artieri’s processing circuitry is configured as
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`digital signal processing circuitry coupled to memory via a bus. APL1007, Figure
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`3; APL1003, ¶¶60-62. Unlike Bowes’ DSP, however, Artieri’s processing
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`circuitry provides a specially-adapted pipeline for performing operations typical
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`of video image decoding, and in particular, MPEG video decoding. APL1007, p.
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`11, APL1003, ¶¶61-63. Artieri illustrates its decoder circuitry transferring data to
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`and from bus-coupled memory (15) and suggests that DRAM would be
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`advantageous based on size, costs and capacity. APL1007, FIG. 3, pp. 12-14, 20,
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`36; APL1003, ¶¶60, 62. Memory 15 of Artieri includes an area “CD” to store
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`compressed data (CD) prior to being processed and picture areas (IM1, IM2, and
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`IM3) to store a currently reconstructed picture and previously decoded pictures.
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`APL1007, p. 14.
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`i. Reasons to Combine - Bowes, Datasheet, and Artieri
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`In considering the system of Bowes, one of skill in the art would have
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`looked to the Datasheet based on Bowes’ specific reference to, and suggestion of,
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`the DSP3210. APL1003, ¶¶56, 99-100.
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`Bowes discusses using its system for real-time processing tasks including
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`“speech processing, audio channel control, modem emulation, image processing
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`and the like” and further suggests video and video conferencing applications.
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`APL1005, 6:32-34, 1:34-41. On this suggestion of Bowes, one of skill in the art
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`would have been motivated to implement video processing in Bowes’ system.
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`APL1003, ¶¶54, 67-77, 101-103.
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`To meet goals of video image processing at frame rates desirable for human
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`viewing and for large, high-quality images, one of skill in the art would have
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`looked to replace or augment the capabilities of the DSP3210-type digital signal
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`processor described in Bowes to include circuitry specialized to the desired
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`purpose—processing, and more particularly decoding, of video images. APL1003,
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`¶¶72-86, 102-103. To achieve these goals, one of skill in the art would have
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`looked to implement video decompression methods such as MPEG to facilitate
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`storage and transfer of video in compressed form and thereby accommodate
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`bandwidth limitations of a bus. APL1003, ¶75. Indeed, design challenges of
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`providing sufficient bandwidth on the memory bus to perform real-time
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`isochronous signal processing were recognized by Bowes. APL1005, 4:62-67;
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`APL1003, ¶75.
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`Bowes recognizes that its DSP “require[s] a large amount of bandwidth to
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`memory” for real-time processing. APL1005, 1:51-53. Therefore, one of skill in
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`the art would have considered video storage and processing methods that employ
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`compression, and MPEG was a recognized standard for processing video while
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`addressing storage compactness and bandwidth demands. APL1003, ¶¶75-87,
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`102-103.
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`In reviewing DSP3210 functionality, and in light of the desire to support
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`video processing that provides the benefits of compressed video data storage, one
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`of skill in the art would have looked to Artieri for its teaching of digital signal
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`processing circuitry capable of performing MPEG video decompression in the
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`image processing capable system described in Bowes. APL1003, ¶103, see also
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`¶¶72-87, 101-103. While DSP3210 was, at the time, capable of performing
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`MPEG computations, the desire to provide video frame rate processing for images
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`of increasing size and quality would have motivated one of skill in the art to
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`consider Artieri’s specialized MPEG decoder circuits. APL1003, ¶76, see also
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`¶¶72-87, 101-103. Indeed, Artieri itself invites application of its circuitry into a
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`microcomputer system such as described in Bowes. APL1007, p. 38. One of skill
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`in the art would have recognized that providing Artieri’s decoder circuitry in a
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`DSP configured to cooperatively use main memory of the computer system such
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`as in Bowes provides a predictable result, while maintaining real-time operation
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`for video decoding computations that (at video frame rates) can be more taxing
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`than still image processing. APL1005, 7:26-30, 8:40-42, APL1003, ¶103; see
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`also ¶¶72-87 (“decoder”), 88-94 (“memory”).
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`ii. Summary of the Central Bowes and Artieri Combination
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`Annotations to Figure 2 of Bowes and Figure 3 of Artieri are provided
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`below to facilitate an overall understanding of the invalidity of the identified
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`claims of the ’045 Patent and are illustrative of certain aspects of the specific
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`challenges set forth in detail below. APL1003, ¶¶66-71. Bowes’ representative
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`Figure 2 teaches the system espoused by the ’045 Patent – multiple devices on a
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`bus (110) accessing a shared main memory (14) and an arbiter (200) controlling
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`access to the shared main memory (14). The claims of the ’045 Patent apply this
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`concept of shared memory to a system specifically including a decoder for video
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`images. Bowes describes a DSP (20) and a CPU (10) as two of the devices
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`sharing the main memory. APL1005, 5:20-30, 6:21-44. While indicating that its
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`DSP 20 may be programmed for image processing, Bowes does not explicitly
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`state that its DSP 20 is a “decoder.” See APL1005, 6:33-35. As detailed below
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`however, the evidence of the present Petition establishes that one of skill in the art
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`would have recognized a capability and, indeed, motivation to enhance Bowes’
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`DSP (20) with video decoder circuits specialized for computations dictated by
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`industry-accepted MPEG standards.
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`APL1003, ¶68.
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`As
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`in most
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`tradeoffs between
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`(i) generally-applicable hardware
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`programmable to a specialized task and (ii) more task-specialized hardware,
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`performance or computational throughput considerations tend to favor specialized
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`hardware. APL1003, ¶¶68. One of skill in the art would have been motivated to
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`consider specialized hardware based on a desire to support images of increasing
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`size and quality at higher frame rates. APL1003, ¶¶68, 73-77. Doing so involved
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`no more than the straightforward introduction of known MPEG decoder circuitry
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`into the shared main memory architecture of Bowes. APL1003, ¶68, see also
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`¶¶69-94. As exemplified above, Artieri at Figure 3 discloses exemplary decoder
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`circuitry that provides an MPEG-specialized pipeline that one of skill in the art
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`would have considered for inclusion in the system of Bowes’ Figure 2.
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`iii. Detailed Analysis
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`The following analysis describes how Bowes as informed by Datasheet and
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`in view of Artieri renders obvious each and every element of at least claims 1, 4,
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`5, 7, 10, 12, 16, and 17 of the ’045 Patent. A corresponding claim chart is
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`contained in Dr. Colwell’s expert declaration. See APL1003 beginning at page 55.
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`Claim 1
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`[1.0]
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`An electronic system comprising:
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`Bowes describes a computer system (APL1005, 5:10-12, see also 1:18-22),
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`which is an “electronic system,” as recited in the claim. See also APL1003, pp.
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`55-56.
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`[1.1]
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`a bus coupleable to a main memory having stored therein data
`corresponding to video images to be decoded and also decoded data
`corresponding to video images that have previously been decoded;
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`Bowes describes memory bus 110 coupleable to a main memory subsystem
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`14 (a main memory) of its electronic system. APL1005, 5:10-23. FIG. 2 of
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`Bowes is illustrative:
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`APL1005, Figure 2, annotated
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`Thus, Bowes’ system has a bus for accessing the main memory subsystem
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`and teaches “an electronic system comprising: a bus coupleable to a main
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`memory.”
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`Bowes’ architecture provides for data, including image data, to be
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`read/written to the main memory 14 by its digital signal processor, DSP 20.
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`APL1005, 6:22-37, 7:2-12, 7:23-26, 6:28-34; APL1003, ¶88. Bowes emphasizes
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`that its DSP and CPU share the main memory (DRAM):
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`[I]t is an object of the present invention to provide a mechanism
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`and method for arbitrating the memory bus bandwidth to
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`efficiently allow the use of a digital signal processor and a CPU
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`over a common memory bus sharing the system's dynamic
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`random acc