Trials@uspto.gov
`571-272-7822
`
`
`Paper 14
`Entered: January 6, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`HTC CORPORATION,
`HTC AMERICA, INC.,
`LG ELECTRONICS, INC.,
`SAMSUNG ELECTRONICS CO., LTD., and
`SAMSUNG ELECTRONICS AMERICA, INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2015-01502
`Patent 7,542,045 B2
`____________
`
`
`
`Before JAMES B. ARPIN, MATTHEW R. CLEMENTS, and
`SUSAN L. C. MITCHELL, Administrative Patent Judges.
`
`ARPIN, Administrative Patent Judge.
`
`
`DECISION
`Granting Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`Apple Exhibit 1012
`Page 1 of 30
`
`
`571-272-7822
`
`
`Paper 14
`Entered: January 6, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`HTC CORPORATION,
`HTC AMERICA, INC.,
`LG ELECTRONICS, INC.,
`SAMSUNG ELECTRONICS CO., LTD., and
`SAMSUNG ELECTRONICS AMERICA, INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2015-01502
`Patent 7,542,045 B2
`____________
`
`
`
`Before JAMES B. ARPIN, MATTHEW R. CLEMENTS, and
`SUSAN L. C. MITCHELL, Administrative Patent Judges.
`
`ARPIN, Administrative Patent Judge.
`
`
`DECISION
`Granting Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`Apple Exhibit 1012
`Page 1 of 30
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`IPR2015-01502
`Patent 7,542,045 B2
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`
`I.
`INTRODUCTION
`HTC Corporation; HTC America, Inc.; LG Electronics, Inc.; Samsung
`Electronics Co., Ltd.; and Samsung Electronics America, Inc. (collectively
`“Petitioner”) filed a Petition requesting inter partes review of claims 1, 2, 4–
`7, 9, 10, 12, 13, and 15–17 (“the challenged claims”) of Patent No. US
`7,542,045 B2 (Ex. 1001, “the ’045 patent”). Paper 2 (“Pet.”). Parthenon
`Unified Memory Architecture LLC (“Patent Owner”) filed a Preliminary
`Response. Paper 7 (“Prelim. Resp.”). We review the Petition pursuant to 35
`U.S.C. § 314, which provides that an inter partes review may be authorized
`only if “the information presented in the petition . . . and any [preliminary]
`response . . . shows that there is a reasonable likelihood that the petitioner
`would prevail with respect to at least 1 of the claims challenged in the
`petition.” 35 U.S.C. § 314(a); 37 C.F.R. § 42.4(a). Upon consideration of
`the Petition and the Preliminary Response, and the accompanying evidence,
`we determine that the information presented by Petitioner establishes that
`there is a reasonable likelihood that Petitioner would prevail in showing the
`unpatentability of at least one of the challenged claims of the ’045 patent.
`Accordingly, pursuant to 35 U.S.C. § 314, we institute an inter partes review
`of claims 1, 2, 4–7, 9, 10, 12, 13, and 15–17 of the ’045 patent.
`
`A. Related Proceedings
`
`The ’045 patent is involved in several cases pending in the Eastern
`District of Texas. Pet. 2–4; Paper 5, 2–3. Petitioner also has filed other
`petitions seeking inter partes review of related patents. Pet. 3–4.
`
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`B. The ’045 patent
`The ’045 patent relates generally “to the field of electronic systems
`having a video and/or audio decompression and/or compression device, and
`is more specifically directed to sharing a memory interface between a video
`and/or audio decompression and/or compression device and another device
`contained in the electronic system.” Ex. 1001, col. 1, ll. 36–41. As of the
`effective filing date of the ’045 patent,1 a typical decoder included a
`dedicated memory, which represented a significant percentage of the cost of
`the decoder and which went unused most of the time. Id. at col. 2, ll. 21–63,
`col. 4, ll. 43–60, Figs. 1a–1c.
`To address these and other concerns, the ’045 patent discloses an
`electronic system in which a first device and a video and/or audio
`decompression and/or compression device are coupled to a shared memory
`through a bus that may have bandwidth sufficient for the video and/or audio
`decompression and/or compression device to operate in real time. Id. at col.
`4, l. 64–col. 5, l. 7. Figure 2 is reproduced below.
`
`
`1 The ’045 patent claims the benefit of a string of earlier-filed U.S. patent
`applications, the earliest of which was filed on August 26, 1996. Petitioner
`does not challenge the entitlement of the ’045 patent to this earliest filing
`date and argues that the ’045 patent will expire in August of 2016,
`presumably based on this earliest filing date. Pet. 12–13. Patent Owner
`implicitly claims the entitlement of the ’045 patent to the benefit of this
`earliest filing date and expressly states that the ’045 patent will expire on
`August 26, 2016. Paper 8, 1.
`
`3
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`Figure 2 is a block diagram of an electronic system that contains a device
`with a memory interface and an encoder and decoder. Id. at col. 6, ll. 3–5.
`“First device 42 can be a processor, a core logic chipset, a graphics
`accelerator, or any other device that requires access to the memory 50.” Id.
`at col. 6, ll. 29–32. Both first device 42 and decoder/encoder 80 have access
`to memory 50 through memory interfaces 72 and 76, respectively, coupled
`to fast bus 70. Id. at col. 6, ll. 27–29, col. 7, ll. 26–28, 48–51. Fast bus 70
`may have at least the bandwidth required for decoder/encoder 80 to operate
`in real time and, preferably, has a bandwidth of at least approximately twice
`the bandwidth required for decoder/encoder 80 to operate in real time. Id. at
`col. 7, ll. 48–51, col. 8, ll. 28–33.
`During operation, decoder/encoder 80, first device 42, and refresh
`logic 58, if it is present, request access to memory 50 through arbiter 82. Id.
`
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`at col. 12, ll. 53–56. Arbiter 82 determines which of the devices may access
`memory 50. Id. at col. 12, ll. 57–58. Decoder/encoder 80 may get access to
`memory 50 in the first time interval, and first device 42 may get access to
`memory 50 in the second time interval. Id. at col. 12, ll. 58–61. Direct
`Memory Access (DMA) engine 52 of decoder/encoder 80 determines the
`priority of decoder/encoder 80 for access to memory 50 and the burst length
`when decoder/encoder 80 has access to memory 50. Id. at col. 12, ll. 61–67.
`DMA engine 60 of first device 42 determines its priority for access to
`memory 50 and the burst length when first device 42 has access to memory
`50. Id. at col. 12, ll. 65–67.
`When decoder/encoder 80 or one of the other devices generates a
`request to access memory 50, the request is transferred to arbiter 82, and
`access to memory 50 is determined based on the state of arbiter 82 and on a
`priority scheme. Id. at col. 13, ll. 1–30. The priority scheme can be any
`scheme that ensures decoder/encoder 80 gets access to memory 50 often
`enough to operate properly, but does not starve entirely other devices
`sharing memory 50. Id. at col. 13, ll. 31–37; see id. at col. 8, ll. 9–13
`(describing a “starvation period”).
`
`C. Illustrative Claim
`
`Of the challenged claims, claims 1, 4, 5, and 12 are independent. Ex.
`1001, col. 15, ll. 35–56 (claim 1), col. 15, l. 63–col. 16, l. 36 (claims 4 and
`5), col.16, l. 54–col. 17, l. 2 (claim 12). Claim 2 depends directly from
`claim 1 (id. at col. 15, ll. 57–60); claims 6, 7, 9, and 10 depend directly from
`claim 5 (id. at col. 16, ll. 37–42, 46–49); and claims 13 and 15–17 depend
`directly from claim 12 (id. at col. 17, ll. 3–6, col. 18, ll. 1–8). Claim 1 is
`
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`illustrative and is reproduced below, with disputed claim limitations
`emphasized:
`
`1.
`An electronic system comprising:
`a bus coupleable to a main memory having stored therein
`data corresponding to video images to be decoded and also
`decoded data corresponding to video images that have previously
`been decoded;
`a video decoder coupled to the bus for receiving encoded
`video images and for outputting data for displaying the decoded
`video images on a display device, the decoder configured to
`receive data from the main memory corresponding to at least one
`previously decoded video image and to a current video image to
`be decoded and outputting decoded data corresponding to a
`current video image to be displayed, the current video image to be
`displayed adapted to be stored in the main memory;
`
` a
`
` microprocessor system configured to be coupled to the
`main memory, the microprocessor system for storing non-image
`data in and retrieving non-image data from the main memory; and
`an arbiter circuit coupled to both the microprocessor system
`and the video decoder for controlling the access to said main
`memory by the video decoder and the microprocessor.
`Ex. 1001, col. 15, ll. 35–56 (emphasis added).
`D. Applied References and Declarations
`Petitioner relies upon the following references and declarations in
`support of its grounds for challenging the identified claims of the ’045
`patent:2
`
`
`2 Our rules require that Petitioner number its exhibits “sequentially” in a
`range of 1001–1999. 37 C.F.R. § 42.63(c). By “reserving” Exhibit Nos.
`1017, 1018, 1021, and 1022; Petitioner failed to follow this rule. Petitioner
`shall number all future exhibits sequentially starting with Exhibit No. 1031.
`We shall expunge any further exhibits filed by either party that are not
`
`
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`Exhibit
`1002
`1003
`1004
`
`1005
`
`1007
`1008
`1030
`Pet. vii–viii.
`
`References and Declarations
`File History of Patent No. US 7,542,045 B2
`Patent No. US 5,546,547 (“Bowes”)
`International Organization for Standardization, “ISO/IEC
`11172-2: Information technology—Coding of moving
`pictures and associated audio for digital storage media at up to
`about 1,5 Mbit/s—Part 2: Video,” (1st ed. Aug. 1, 1993)
`(“MPEG”)
`S. Rathnam et al., “An Architectural Overview of the
`Programmable Multimedia Processor, TM-1,” IEEE
`Proceedings of COMPCON ’96, pp. 319-326 (1996)
`(“Rathnam”)
`Patent No. US 5,774,676 (“Stearns”)
`Declaration of Santhana Chari, Ph.D.
`Declaration of Harold S. Stone, Ph.D. (the “Stone Decl.”)
`
`E. Asserted Grounds of Unpatentability
`Petitioner argues that the challenged claims are unpatentable based on
`the following grounds (Pet. 5–6):
`References
`Rathnam
`
`Claims challenged
`Basis
`§ 102(e) 1, 2, 4–7, 9, 10, 12, 13, and
`15–17
`§ 103(a) 1, 4, 5, 7, 10, 12, 16, and 17
`§ 103(a) 9 and 15
`§ 103(a) 2, 6, and 13
`
`Bowes and MPEG
`Bowes, MPEG, and Rathnam
`Bowes, MPEG, and Stearns
`
`
`
`numbered sequentially. 37 C.F.R. §§ 42.5(a), 42.7(a), and 24.12(a)(1) and
`(b)(2).
`
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`II. ANALYSIS
`
`A. Claim Construction
`Pursuant to 37 C.F.R. § 42.100(b), “[a] claim in an unexpired patent
`shall be given its broadest reasonable construction in light of the
`specification of the patent in which it appears.” Petitioner alleges that the
`’045 patent will expire in August of 2016. Pet. 12–13. Patent Owner states
`that the ’045 patent will expire on August 26, 2016. Paper 8, 1. Thus, the
`’045 patent will expire before we are likely to issue a final written decision
`as to the patentability of the challenged claims.
`Although Petitioner proposes a construction based on the broadest
`reasonable interpretation standard for three terms, Petitioner argues that its
`proposed constructions will remain the same even if we apply the claim
`construction standard used by the U.S. district courts and set forth in Phillips
`v. AWH Corp., 415 F.3d 1303, 1314 (Fed. Cir. 2005) (en banc). Pet. 13.
`Patent Owner proposes no construction for any term at this preliminary
`proceeding stage. In order to determine if Petitioner has demonstrated a
`reasonable likelihood that it will prevail in this initial proceeding, given the
`patent’s pending expiration, we analyze Petitioner’s arguments through the
`lens of the claim construction standard of Phillips that will apply to our final
`written decision. 37 C.F.R. §§ 42.5(b) and 42.100(b); see Toyota Motor
`Corp. v. Cellport Sys., Inc., Case IPR2015-00633, slip op. at 8–10 (PTAB
`Aug. 14, 2015) (Paper 11); cf. In re Rambus Inc., 694 F.3d 42, 46 (Fed. Cir.
`2012) (“While claims are generally given their broadest possible scope
`during prosecution, the Board’s review of the claims of an expired patent is
`similar to that of a district court’s review.”) (internal citation omitted).
`
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`“In determining the meaning of the disputed claim limitation, we look
`principally to the intrinsic evidence of record, examining the claim language
`itself, the written description, and the prosecution history, if in evidence.”
`DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 469 F.3d 1005, 1014
`(Fed. Cir. 2006) (citing Phillips, 415 F.3d at 1312–17). The words of a
`claim generally are given their ordinary and customary meaning, and that is
`the meaning the term would have to a person of ordinary skill at the time of
`the invention, in the context of the entire patent including the specification.
`See Phillips, 415 F.3d at 1312–13. Claims are not interpreted in a vacuum
`but are a part of and read in light of the specification. See Slimfold Mfg. Co.
`v. Kinkead Indus., Inc., 810 F.2d 1113, 1116 (Fed. Cir. 1987). Although it is
`improper to read a limitation from the specification into the claims, the
`claims still must be read in view of the specification of which they are a part.
`See Microsoft Corp. v. Multi-Tech Sys., Inc., 357 F.3d 1340, 1347 (Fed. Cir.
`2004).
`1. “video decoder”
`Each of challenged claims 1, 2, 4–6, 9, 12, 13, and 15 expressly
`recites a “video decoder.” E.g., Ex. 1001, col. 15, ll. 40–48. Petitioner
`proposes to construe the term “video decoder” to mean “hardware and/or
`software that translates data streams into video information.” Pet. 9–10
`(citing Ex. 1001, col. 1, ll. 66–67 (“a video and/or audio decompression
`device (hereinafter ‘decoder’)”), col. 15, ll. 30–33 (“[a]ny conventional
`decoder including a decoder complying to the MPEG-1, MPEG-2, H.261, or
`H.261 standards, or any combination of them, or any other conventional
`standard can be used as the decoder/encoder.”); see Phillips, 415 F.3d at
`1312–13 (regarding a term’s ordinary and customary meaning to a person of
`
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`ordinary skill in the art, in the context of the entire patent, including the
`specification). Petitioner further relies upon a dictionary definition for
`“decoder” as evidence of the term’s ordinary and customary meaning to a
`person of ordinary skill in the art as of the effective filing date of the ’045
`patent. Id. at 10 (citing Ex. 1014, 56 (“decoder (n). Any hardware or
`software system that translates data streams into video or audio
`information.”).
`In addition to its usage in the challenged claims, as noted above, the
`’045 patent uses the term “video decoder” throughout the Specification.
`Moreover, we find nothing in the usage of the term “video decoder” in the
`claims that is inconsistent with the usage of the term elsewhere in the
`Specification of the ’045 patent, with the dictionary definition of “decoder”
`in Exhibit 1014, or with the Petitioner’s proposed construction. The ’045
`patent’s definition of “decoder” to mean “a video and/or audio
`decompression device,” and its disclosure that the “decoder/encoder” can be
`any conventional decoder complying to any conventional standard support a
`construction of “video decoder” that encompasses both hardware and
`software, are persuasive of the term’s proper construction, in the context of
`the entire ’045 patent, including the Specification. See, e.g., Ex. 1001, col.
`1, ll. 66–67, col. 15, ll. 20–33.
`Accordingly, on this record, and for purposes of this Decision, we
`adopt Petitioner’s proposed construction of “video decoder” as “hardware
`and/or software that translates data streams into video information.”
`
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`2. “fast bus”
`Challenged claim 4 recites a “fast bus.” Ex. 1001, col. 15, l. 64–col.
`16, l. 2. Petitioner proposes to construe the term “fast bus” to mean “any
`bus having a bandwidth sufficient to allow the system to operate in real
`time.” Pet. 10–11 (quoting Ex. 1001, col. 5, ll. 26–31(emphasis added)); cf.
`Ex. 1013, 1 (“bus with a bandwidth equal to or greater than the required
`bandwidth to operate in real time”). Petitioner further argues that “[t]he
`specification provides examples of fast buses that purportedly permit ‘real
`time’ data transfers between a decoder and a memory under at least some
`bandwidth calculations, including the industry standard PCI bus.” Id.
`(citing Ex. 1001, col. 5, ll. 26–31).
`
`Petitioner further argues that statements made during prosecution of a
`child application (see Ex. 1015, 1) are inconsistent with the statements in
`the Specification of the ’045 patent, regarding the requirements for “real
`time” operation. Pet. 11. In view of these alleged inconsistencies,
`Petitioner argues that claim 4 is indefinite. See 35 U.S.C. § 112, ¶ 2. Such
`arguments are improper in the context of an inter partes review. See 35
`U.S.C. § 311(b); 37 C.F.R. § 42.104(b)(2). Further, because these
`arguments are based on the prosecution history of a related, but later-filed,
`application, we do not find them persuasive with respect to the construction
`of claim terms in the ’045 patent.
`Accordingly, on this record, and for purposes of this Decision, we
`adopt Petitioner’s proposed construction of “fast bus” as “any bus having a
`bandwidth sufficient to allow the system to operate in real time.”
`
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`3. “decoder directly supplies a display device with an image”
`Challenged claims 6 and 13 recite a “decoder directly supplies a
`display device with an image.” Ex. 1001, col. 16, ll. 37–40 (claim 6), col.
`17, ll. 3–6 (claim 13). Petitioner argues that this limitation may refer to a
`decoder that directly supplies a display adapter with an image, and the
`display adapter is considered to be a part of the display device. Pet. 12
`(citing Ex. 1001, col. 5, ll. 34–37 (“the decoder directly supplies a display
`adapter of the screen with an image under decoding which is not used to
`decode a subsequent image”), col. 10, ll. 42–44 (“[t]he display adapter then
`supplies these data to a display device such as a screen”)). Nevertheless,
`Petitioner also argues that this limitation is not adequately supported by
`written description in the Specification of the ’045 patent. See 35 U.S.C.
`§ 112, ¶ 1. Such arguments again are improper in the context of an inter
`partes review. See 35 U.S.C. § 311(b); 37 C.F.R. § 42.104(b)(2).
`For purposes of this Decision, we are persuaded that this limitation
`describes an image as being “directly supplied” if it is supplied without
`being stored in main memory for purposes of decoding subsequent images.
`Ex. 1013, 1; see Ex. 1011, 19; Ex. 1012, 22; see also Power Integrations,
`Inc. v. Lee, 797 F.3d 1318, 1326 (Fed. Cir. 2015) (“The fact that the board is
`not generally bound by a previous judicial interpretation of a disputed claim
`term does not mean, however, that it has no obligation to acknowledge that
`interpretation or to assess whether it is consistent with the broadest
`reasonable construction of the term.”).
`4. Other Claim Terms
`Petitioner offers no other constructions of any claim term in the
`challenged claims. See Pet. 8–13. Only terms which are in controversy in
`
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`this proceeding need to be construed, and then only to the extent necessary
`to resolve the controversy. Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200
`F.3d 795, 803 (Fed. Cir. 1999). For purposes of this Decision, no other
`claim terms require express construction.3
`
`B. Asserted Grounds of Unpatentability
`1. Overview
`
`Petitioner argues that claims 1, 2, 4–7, 9, 10, 12, 13, and 15–17 of the
`’045 patent are anticipated by Rathnam or are rendered obvious by Bowes
`and MPEG, alone or in combination with Rathnam or Stearns. See supra
`Section I.E.
`“A claim is anticipated only if each and every element as set forth in
`the claim is found, either expressly or inherently described, in a single prior
`art reference.” Verdegaal Bros. v. Union Oil Co., 814 F.2d 628, 631 (Fed.
`Cir. 1987). The elements must be arranged as required by the claim, but this
`is not an ipsissimis verbis test. In re Bond, 910 F.2d 831, 832 (Fed. Cir.
`1990). Our reviewing court guides that
`[U]nless a reference discloses within the four corners of the
`document not only all of the limitations claimed but also all of
`the limitations arranged or combined in the same way as recited
`in the claim, it cannot be said to prove prior invention of the
`thing claimed, and thus, cannot anticipate under 35 U.S.C. §
`102.
`Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008);
`
`
`3 On this record, we are persuaded that our construction of the terms “video
`decoder,” “fast bus,” and “decoder directly supplies a display device with an
`image” set forth above would have been substantially the same had we
`applied the broadest reasonable interpretation standard. See Pet. 13.
`
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`accord Application of Arkley, 455 F.2d 586 (CCPA 1972). However, “it is
`proper to take into account not only specific teachings of the reference but
`also the inferences which one skilled in the art would reasonably be
`expected to draw therefrom.” In re Preda, 401 F.2d 825, 826 (CCPA 1968).
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are “such
`that the subject matter[,] as a whole[,] would have been obvious at the time
`the invention was made to a person having ordinary skill in the art to which
`said subject matter pertains.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398,
`406 (2007). The question of obviousness is resolved on the basis of
`underlying factual determinations, including: (1) the scope and content of
`the prior art; (2) any differences between the claimed subject matter and the
`prior art; (3) the level of skill in the art;4 and (4) objective evidence of
`nonobviousness, i.e., secondary considerations.5 Graham v. John Deere Co.,
`383 U.S. 1, 17–18 (1966). On this record and for the reasons set forth
`below, we are persuaded that Petitioner demonstrates a reasonable likelihood
`of prevailing in showing that claims 1, 2, 4–7, 9, 10, 12, 13, and 15–17 of
`the ’045 patent are unpatentable.
`
`
`4 Petitioner proposes a definition for a person of ordinary skill in the art.
`Pet. 13 (citing Ex. 1030 ¶¶ 78–81). Patent Owner does not challenge
`Petitioner’s proposed definition and does not propose an alternative. To the
`extent necessary and for purposes of this Decision, we adopt Petitioner’s
`definition.
`5 Patent Owner does not contend in its Preliminary Response that such
`secondary considerations are present.
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`2. Claims 1, 2, 4–7, 9, 10, 12, 13, and 15–17— Anticipation by
`Rathnam (Ground A)
`Petitioner argues that claims 1, 2, 4–7, 9, 10, 12, 13, and 15–17 are
`unpatentable under 35 U.S.C. § 102(e) as anticipated by Rathnam. Pet. 13–
`32.
`
`a. Rathnam (Ex. 1005)
`Rathnam describes a programmable multimedia processor called
`TM-1. Ex. 1005, Title, Abstract. TM-1 has a high performance VLIW-CPU
`core with video and audio peripheral units designed to support popular
`multimedia applications. Id. at Abstract. “TM-1 easily implements popular
`multimedia standards such as MPEG-1 and MPEG-2, but its orientation
`around a powerful general-purpose CPU makes it capable of implementing a
`variety of multimedia algorithms, whether open or proprietary.” Id. at 319.
`Figure 1 of Rathnam is reproduced below.
`
`Figure 1 shows a block diagram of TM-1. Id. at 320. The CPU and
`peripherals are time-shared and communication between units is through the
`
`
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`SDRAM memory. Id. at 320–321. “The internal data bus connects all
`internal blocks together and provides access to internal control registers (in
`each on-chip peripheral units), external SDRAM, and the external PCI bus.”
`Id. at 322. “Access to the internal bus is controlled by a central arbiter,
`which has a request line from each potential bus master.” Id.
`In operation, “[t]he TM-1 CPU can enlist the [Image Coprocessor
`(ICP)] and video-in units to help with some of the straightforward, tedious
`tasks associated with video processing. . . . A typical mode of operation for
`a TM-1 system is to serve as a video-decompression engine on a PCI card
`in a PC.” Id. at 321. “Video decompression begins when the PC operating
`system hands the TM-1 a pointer to compressed video data in the PC’s
`memory.” Id. “The TM-1 CPU fetches data from the compressed video
`stream via the PCI bus, decompresses frames from the video stream, and
`places them into local SDRAM.” Id. “Decompression may be aided by the
`VLD (variable-length decoder) unit, which implements Huffman decoding
`and is controlled by the TM-1 CPU.” Id. “The TM-1 CPU hands the VLD
`a pointer to a Huffman-encoded bit stream, and the VLD produces a
`tokenized bit stream that is very convenient for the TM-1 image
`decompression software to use.” Id. at 324.
`
`Analysis
`b.
`Petitioner provides a detailed explanation of its arguments regarding
`the mapping of Rathnam to the limitations of the challenged claims. Pet.
`13–32. In light of the arguments and evidence of record, however, we are
`not persuaded that Petitioner has established a reasonable likelihood that any
`of claims 1, 2, 4–7, 9, 10, 12, 13, and 15–17 are unpatentable as anticipated
`by Rathnam.
`
`16
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`Claim 1 recites that
`the decoder configured to receive data from the main memory
`corresponding to at least one previously decoded video image
`and to a current video image to be decoded and outputting
`decoded data corresponding to a current video image to be
`displayed, the current video image to be displayed adapted to be
`stored in the main memory.
`Ex. 1001, col. 15, ll. 42–48 (emphasis added). The other independent claims
`include substantially the same limitations. See also id. at col. 16, ll. 8–13
`(claim 4), 27–33 (claim 5), 59–65 (claim 12). With regard to these
`limitations, Petitioner argues that
`
`Rathnam’s SDRAM (i.e., main memory) stores encoded
`video images. See, e.g., id. at 14 (“The CPU compresses the
`video data in software (using a set of powerful data-parallel
`operations) and writes the compressed data to a separate area
`of SDRAM.”) (emphasis added).
`Rathnam’s video decoder, which can decode MPEG-1
`and MPEG-2 encoded data, receives encoded video images via
`the bus and decodes them. See, e.g., id. at 17 (“The variable-
`length decoder (VLD) . . . can be used to help decode MPEG-1
`and MPEG-2 video streams. . . . The format of the output token
`stream is optimized for the MPEG-2 decompression software so
`that communication between the CPU and VLD is minimized.”)
`(emphasis added). Since Rathnam’s video decoder can decode
`MPEG-1 and MPEG-2 encoded data, and such encoded data is
`disclosed to have been written to the SDRAM, Rathnam’s
`decoder must receive data via the bus from the SDRAM (i.e.,
`main memory) corresponding to at least one previously
`decoded video image and to a current video image to be
`decoded. See, e.g., supra Section IX.A.1.b; see also Ex. 1030,
`Stone Decl. ¶ 45–59, 84, 87–108, 132–134, 137–139, 149, 161,
`164, 172.
`
`17
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`Pet. 17–18 (underlining added). Thus, Petitioner argues that
`Rathnam’s video decoder receives encoded data for decoding from the
`SDRAM, i.e., from the shared main memory.
`Patent Owner contends, however, that Rathnam teaches that
`images for decoding are received from a personal computer’s memory
`via the PCI bus, not from the SDRAM. Prelim. Resp. 16. Patent
`Owner’s annotated version of Rathnam’s TM-1 figure is reproduced
`below.
`
`
`Id. at 15 (reproducing TM-1 figure from Ex. 1005, 14 (Section 3.1)).
`Patent Owner contends that the SDRAM (i.e., the main memory) and
`the PCI Interface and Bus are separate and distinct components of
`Rathnam’s device. Id. at 14.
`In particular, Rathnam states that
`
`Video decompression begins when the PC operating
`system hands the TM-1 a pointer to compressed video data in
`
`18
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`the PC’s memory (the details of the communication protocol
`are typically handled by a software driver installed in the
`PC’s operating system).
`The TM-1 CPU fetches data from the compressed
`video stream via the PCI bus, decompresses frames from the
`video stream, and places
`them
`into
`local SDRAM.
`Decompression may be aided by the VLD (variable-length
`decoder) unit, which implements Huffman decoding and is
`controlled by the TM-1 CPU. When a frame is ready for
`display, the TM-1 CPU gives the ICP (image coprocessor) a
`display command. The ICP then autonomously fetches the
`decompressed frame data from SDRAM.
`Prelim. Resp. 16 (quoting Ex. 1005, 14 (Section 3.2, emphasis
`added)). Patent Owner contends that images are placed in the
`SDRAM after they are decompressed but are not obtained from the
`SDRAM for decompression. Id. at 15. We agree. Rathnam
`teaches that the TM-1 CPU fetches data from the compressed video
`stream via the PCI bus, and not from the SDRAM. Therefore, we
`are not persuaded that Petitioner has established a reasonable
`likelihood of prevailing in showing that Rathnam teaches each and
`every element of the challenged independent claims 1, 4, 5, and 12
`or of the challenged claims which depend from independent claims
`1, 5, and 12.
`Conclusion
`c.
`On this record, we are not persuaded that Petitioner has established a
`reasonable likelihood that it would prevail in showing that any of claims 1,
`2, 4–7, 9, 10, 12, 13, and 15–17 are unpatentable as anticipated by Rathnam.
`
`19
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`3. Claims 1, 4, 5, 7, 10, 12, 16, and 17 — Obviousness over Bowes
`and MPEG (Ground B)
`Petitioner argues that claims 1, 4, 5, 7, 10, 12, 16, and 17 are
`unpatentable under 35 U.S.C. § 103(a) as obvious over Bowes and MPEG.
`Pet. 32–48.
`
`Bowes (Ex. 1003)
`a.
`Bowes describes a memory bus arbiter for a computer system having
`a DSP co-processor. Ex. 1003, Title. According to Bowes,
`In prior art computer systems, because of the high bandwidth
`required for real-time processing by a DSP, it has not been
`possible for the DSP to run off of the computer system’s
`DRAM in the way the CPU 10 utilizes it without adversely
`affecting the rest of the computer system. Thus, there has been
`provided a large block of SRAM 24 for use by the DSP 20. . . .
`
` A
`
` significant disadvantage to the prior art computer architecture
`of FIG. 1 is the requirement of a substantial block of static
`random access memory 24. SRAMs are significantly more
`expensive than DRAM which greatly increases the cost of
`computer systems which incorporate SRAM.
`Id. at col. 2, ll. 24–48. Thus, it is an object of Bowes “to provide a
`mechanism and method for arbitrating the memory bus bandwidth to
`efficiently allow the use of a digital signal processor and a CPU over a
`common memory bus sharing the system’s dynamic random access
`memory subsystem without requiring an expensive block static
`random access.” Id. at col. 2, ll. 57–63.
`
`20
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`Apple Exhibit 1012
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`Figure 2 of Bowes is reproduced below.
`
`
`Figure 2 illustrates a block diagram of a computer architecture incorporating
`the arbitration scheme described in Bowes. Id. at col. 3, ll. 62–64. “The
`scheme is implemented such that the DSP is provided with sufficient
`bandwidth to perform real-time digital signal processing using the system’s
`dynamic random access memory (DRAM) and not requiring the
`incorporation of an expensive block of static random access memory
`(SRAM).” Id. at col. 4, ll. 55–60.
`As shown in Figure 2, the system includes CPU 10, memory
`controller and arbiter (MCA) 200, main memory subsystem 14, and DSP 20.
`Id. Fig. 2. “Unl
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