(12) United States Patent
`Steigerwald et al.
`
`I lllll llllllll Ill lllll lllll lllll lllll lllll 111111111111111111111111111111111
`US006828596B2
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,828,596 B2
`Dec. 7, 2004
`
`(54) CONTACTING SCHEME FOR LARGE AND
`SMALL AREA SEMICONDUCTOR LIGHT
`EMITTING FLIP CHIP DEVICES
`
`(75)
`
`Inventors: Daniel A. Steigerwald, Cupertino, CA
`(US); Jerome C. Bhat, San Francisco,
`CA (US); Michael J. Ludowise, San
`Jose, CA (US)
`
`(73) Assignee: Lumileds Lighting U.S., LLC, San
`Jose, CA (US)
`
`( *) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 10/172,311
`
`(22) Filed:
`
`Jun. 13, 2002
`
`( 65)
`
`Prior Publication Data
`
`US 2003/0230754 Al Dec. 18, 2003
`
`Int. Cl.7 ................................................ HOlL 33/00
`(51)
`(52) U.S. Cl. ............................. 257/99; 257/88; 257/93;
`438/34; 438/42; 438/46; 438/47; 313/505
`(58) Field of Search .............................. 257/88, 91, 93,
`257/99; 313/505; 438/34, 42, 46, 47
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,696,389 A * 12/1997 Ishikawa et al. .............. 257/99
`5,886,401 A * 3/1999 Liu ............................ 257/678
`5,898,185 A * 4/1999 Bojarczuk, Jr. et al.
`.... 257/103
`5,998,232 A
`12/1999 Maruska ...................... 438/46
`RE36,747 E * 6/2000 Manabe et al. ............. 257/431
`6,274,924 Bl
`8/2001 Carey et al. ................ 257/676
`6,278,136 Bl * 8/2001 Nitta . ... ... ... .. ... ... ... ... .. . 257 /99
`
`6,518,598 Bl * 2/2003 Chen ........................... 257/91
`6,693,306 B2 * 2/2004 Chen et al. ................... 257/99
`
`FOREIGN PATENT DOCUMENTS
`
`EP
`GB
`JP
`JP
`JP
`JP
`
`0 921 577 Al
`2 343 994
`2-148776
`7-30153
`11-150298
`2002-280618
`
`6/1999
`* 5/2000
`* 6/1990
`* 1/1995
`6/1999
`9/2002
`
`........... HOlL/33/00
`........... HOlL/33/00
`........... HOlL/33/00
`
`OTHER PUBLICATIONS
`
`Abstract of Japanese Patent No. 2002280618, 1 page.
`* cited by examiner
`Primary Examiner-Bradley Baumeister
`(74) Attorney, Agent, or Firm-Patent Law Group LLP;
`Rachel V. Leiterman
`
`(57)
`
`ABSTRACT
`
`In accordance with the invention, a light emitting device
`includes a substrate, a layer of first conductivity type over(cid:173)
`lying the substrate, a light emitting layer overlying the layer
`of first conductivity type, and a layer of second conductivity
`type overlying the light emitting layer. A plurality of vias are
`formed in the layer of second conductivity type, down to the
`layer of first conductivity type. The vias may be formed by,
`for example, etching, ion implantation, or selective growth
`of the layer of second conductivity type. A set of first
`contacts electrically contacts the layer of first conductivity
`type through the vias. A second contact electrically contacts
`the layer of second conductivity type. In some embodiments,
`the area of the second contact is at least 75% of the area of
`the device. In some embodiments, the vias are between 2 and
`100 microns wide and spaced between 5 and 1000 microns
`apart.
`
`28 Claims, 14 Drawing Sheets
`
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`IPR PAGE 1
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`Acuity v. Lynk
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`
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`

`
`U.S. Patent
`
`Dec. 7, 2004
`
`Sheet 1 of 14
`
`US 6,828,596 B2
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`IPR PAGE 2
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`

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`U.S. Patent
`
`Dec. 7, 2004
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`U.S. Patent
`
`Dec. 7, 2004
`
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`U.S. Patent
`
`Dec. 7, 2004
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`Dec. 7, 2004
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`Dec. 7, 2004
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`Dec. 7, 2004
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`Dec. 7, 2004
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`U.S. Patent
`
`Dec. 7, 2004
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`IPR PAGE 10
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`
`U.S. Patent
`
`Dec. 7, 2004
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`US 6,828,596 B2
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`U.S. Patent
`
`Dec. 7, 2004
`
`Sheet 11 of 14
`
`US 6,828,596 B2
`
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`IPR PAGE 12
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`

`
`U.S. Patent
`
`Dec. 7, 2004
`
`Sheet 12 of 14
`
`US 6,828,596 B2
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`IPR PAGE 13
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`

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`U.S. Patent
`
`Dec. 7, 2004
`
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`
`U.S. Patent
`
`Dec. 7, 2004
`
`Sheet 14of14
`
`US 6,828,596 B2
`
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`IPR PAGE 15
`
`

`
`US 6,828,596 B2
`
`1
`CONTACTING SCHEME FOR LARGE AND
`SMALL AREA SEMICONDUCTOR LIGHT
`EMITTING FLIP CHIP DEVICES
`
`FIELD OF THE INVENTION
`
`This invention relates generally to light emitting diodes
`and more specifically to contacts for light emitting diodes.
`
`BACKGROUND
`
`2
`75% of the area of the device. In some embodiments, the
`vias are between about 2 and about 100 microns wide and
`spaced between about 5 and about 1000 microns apart. In
`some embodiments, the vias are formed in a square array, a
`5 hexagonal array, a rhombohedral array, or an arbitrary
`arrangement.
`A light emitting device according to the present invention
`may offer several advantages. First, since the distance over
`which current must laterally spread within the semiconduc-
`10 tor is reduced, the series resistance of the device may be
`reduced. Second, more light may be generated and extracted
`from the device since the area of the active region and the
`area of the second contact are larger than a device with a
`single first contact. Third, the invention may simplify the
`15 geometry of the interconnections between the device and the
`submount, enabling the use of, for example, low cost solder
`deposition methods.
`In one embodiment, the first contacts are connected by a
`set of interconnects. An insulating layer is formed over the
`device. On one portion of the insulating layer, openings
`aligned with the second contacts are made in the insulating
`layer. On another portion of the insulating layer, openings
`aligned with the first contacts and the interconnects are made
`in the insulating layer. A first layer of a submount connection
`material such as solder is deposited on one portion of the
`device and a second layer of submount connection material
`is deposited on the other portion of the device. The two
`submount connection layers can then be used to connect the
`device to a submount.
`
`20
`
`Semiconductor light emitting devices such as light emit(cid:173)
`ting diodes (LEDs) are among the most efficient light
`sources currently available. Material systems currently of
`interest in the manufacture of high brightness LEDs capable
`of operation across the visible spectrum include group III-V
`semiconductors, particularly binary, ternary, and quaternary
`alloys of gallium, aluminum, indium, and nitrogen, also
`referred to as III-nitride materials; and binary, ternary, and
`quaternary alloys of gallium, aluminum, indium, and
`phosphorus, also referred to as III-phosphide materials.
`Often III-nitride devices are epitaxially grown on sapphire,
`silicon carbide, or III-nitride substrates and III-phosphide
`devices are epitaxially grown on gallium arsenide by metal
`organic chemical vapor deposition (MOCVD) molecular 25
`beam epitaxy (MEE) or other epitaxial techniques. Often, an
`n-type layer (or layers) is deposited on the substrate, then an
`active region is deposited on the n-type layers, then a p-type
`layer (or layers) is deposited on the active region. The order
`of the layers may be reversed such that the p-type layers are 30
`adjacent to the substrate.
`Some of these substrates are insulating or poorly con(cid:173)
`ducting. In some instances, a window is attached to the
`semiconductor layers to enhance optical extraction. Devices
`fabricated from semiconductor crystals grown on or affixed 35
`to poorly conducting substrates must have both the positive
`and the negative polarity electrical contacts to the epitaxially
`grown semiconductor on the same side of the device. In
`contrast, semiconductor devices grown on conducting sub(cid:173)
`strates can be fabricated such that one electrical contact is 40
`formed on the epitaxially grown material and the other
`electrical contact is formed on the substrate. However,
`devices fabricated on conducting substrates may also be
`designed to have both contacts on the same side of the
`device on which the epitaxial material is grown so as to 45
`improve light extraction from the LED chip. There are two
`types of devices with both the p- and n-contacts formed on
`the same side. In the first (also known as the flip chip), the
`light is extracted through the substrate or window material.
`In the second (also known as an epi-up structure), the light 50
`is extracted through the contacts, through the uppermost
`semiconductor layers of the device, or through the edges of
`the devices.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is an example of a large junction light emitting
`device.
`FIG. 2 is a plan view of a large junction light emitting
`device with vias.
`FIG. 3 is a cross sectional view of the device shown in
`FIG. 2 along axis A
`FIGS. 4A-4E illustrate an embodiment of the present
`invention at various stages during fabrication.
`FIG. 5 is a plan view of a light emitting device with vias
`and solder connections.
`FIG. 6 is a cross sectional view of the device shown in
`FIG. 5 along axis AA.
`FIG. 7 is a cross sectional view of the device shown in
`FIG. 5 along axis BB.
`FIG. 8 is a plan view of a small junction light emitting
`device with vias.
`FIG. 9 is a cross sectional view of the device shown in
`FIG. 8 along axis CC.
`FIG. 10 is an exploded view of a light emitting device
`incorporated into a package.
`FIG. 11 is a cross sectional view of multiple light emitting
`55 devices mounted on a board.
`FIG. 12 illustrates a light emitting device incorporated
`into a package.
`FIG. 13 illustrates a light emitting device with a with a
`wavelength converting material.
`FIG. 14 is a cross sectional view of an alternative embodi(cid:173)
`ment of a small junction light emitting device.
`FIG. 15 is a plan view of an alternative embodiment of a
`small junction light emitting device.
`
`SUMMARY
`
`In accordance with one embodiment of the invention, a
`light emitting device includes a substrate, a layer of first
`conductivity type, a light emitting layer, and a layer of
`second conductivity type. A plurality of vias are formed in
`the layer of second conductivity type, down to the layer of 60
`first conductivity type. The vias may be formed by, for
`example, etching, ion implantation, diffusion, or selective
`growth of at least one layer of second conductivity type. A
`set of first contacts electrically contacts the layer of first
`conductivity type through the vias. A second contact elec- 65
`trically contacts the layer of second conductivity type. In
`some embodiments, the area of the second contact is at least
`
`DETAILED DESCRIPTION
`In accordance with embodiments of the invention, a light
`emitting device such as a light emitting diode is formed with
`
`IPR PAGE 16
`
`

`
`US 6,828,596 B2
`
`3
`an n-contact compnsmg a plurality of vias. Such light
`emitting devices may be any suitable material system,
`including, for example, II-VI materials systems and III-V
`materials systems such as III-nitride, III-phosphide, and
`III-arsenide.
`FIG. 1 illustrates an example of a large area III-nitride flip
`chip light emitting device. A large area device is a device
`with an area greater than or equal to about 0.2 square
`millimeter, while a small area device is a device with an area
`less than about 0.2 square millimeter. A small area device
`may be, for example, 0.3 mm by 0.4 mm. The device
`illustrated in FIG. 1 may be, for example, 1 mm on a side.
`The device shown in FIG. 1 is described in more detail in
`application Ser. No. 09/469,657, titled "III-Nitride Light(cid:173)
`Emitting Device With Increased Light Generating
`Capability," filed Dec. 22, 1999 on an invention of Krames
`et al., and incorporated herein by reference. The device
`shown in FIG. 1 has a single, large n-contact and a single,
`large p-contact.
`Because of the high resistivity of the p-type layers,
`III-nitride light emitting devices employ a metal layer over(cid:173)
`lying the p-type layers to provide p-side current spreading.
`When both contacts are formed on the same side of the
`device, the n-side current spreading must occur through the
`n-type III-nitride layers. In 11-phosphide devices formed on 25
`conducting substrates, n-side current spreading may also
`occur through the substrate. In both III-nitride and III(cid:173)
`phosphide devices, the distance over which current spread(cid:173)
`ing within the semiconductor is required should be
`minimized, since requiring current spreading over large
`distances causes higher resistance and less uniform current
`density. Increased driving voltages must be applied to the
`devices in order to get the required current density at every
`point in then-type layers. In the III-nitride device shown in
`FIG. 1, for example, the distance required for current
`spreading by the n-type layer may be kept less than about
`200 microns, meaning no part of the p-contact is more than
`200 microns from the nearest part of the n-contact.
`Current spreading can be a particular problem in the case
`of large area devices, in which the current in the lower
`semiconductor layers must spread some considerable lateral
`distance. In order to circumvent this problem, the concept of
`using the current spreading fingers as shown in FIG. 1 has
`been proposed. However, in devices with current spreading
`fingers on the n-contact as shown in FIG. 1, considerable
`active region must be sacrificed in order to provide fingers
`for increased current spreading. In small area chips, i.e.
`devices with an area less than 0.2 square millimeter, efficient
`current spreading may be less of an issue than in large area
`chips. However, LED active region area must still be sac(cid:173)
`rificed in order to make contact to the semiconductor layer.
`Typically, the minimum absolute area required to make such
`a contact would be fixed by the minimum size to which it is
`possible to make electrical contact to the chip. In the case of
`a flip chip, the minimal manufacturable size of a solder
`bump would determine the minimum size of the underlying
`contact area. In the case of an epi-up structure, the minimum
`area to which wire bonds could be made reproducably would
`determine this minimum contact area. Therefore, as the area
`of LED chips decrease, the fractional area of the chip
`required to make the contact to the n-type semiconductor
`layer increases and the fractional active region area of the
`LED decreases.
`FIG. 2 illustrates a plan view of an example of an LED
`formed in accordance with the present invention. Rather
`than using a single, large n-contact as shown in the device
`in FIG. 1, the device of FIG. 2 makes contact to then-layer
`
`4
`of the device through a series of vias 14 which are etched
`through the active region and the p-layers of the device.
`FIG. 3 is a cross section of the device shown in FIG. 2,
`taken through axis A In FIGS. 2 and 3 only the semicon-
`5 ductor layers, and not metal contacts, are shown for clarity.
`As shown in FIG. 3, one or more n-type layers 11 are formed
`over a substrate 10. An active region 12 is formed over the
`one or more n-type layers and one or more p-type layers 13
`are formed over the active region. Several vias 14 are
`10 formed in the device down to n-type layers 11 by etching
`away p-type layers 13 and active region 12 with, for
`example, a reactive ion etch; by ion implantation; by dopant
`diffusion; or by selective growth of active region 12 and
`p-type layers 13. The diameter (dimension a in FIG. 3) of the
`via may be, for example, between about 2 microns and about
`15 100 microns, and is usually between about 10 microns and
`about 50 microns. The spacing between vias (dimension b in
`FIG. 3) may be, for example, about 5 microns to about 1000
`microns, and is usually about 50 microns to about 200
`microns. The device illustrated in FIG. 2 has a 4x4 rectan-
`20 gular array of vias. A rectangular array of a different size (for
`example, 6x6 or a 9x9) may also be used, as well as a
`hexagonal array, a rhombohedral array, a face-centered
`cubic array, an arbitrary arrangement, or any other suitable
`arrangement.
`A p-contact is formed on what remains of p-type layers
`13, and n-contacts are deposited in vias 14. The p- and
`n-contacts are usually selected for low optical absorption of
`light and low contact resistivity. For a III-nitride device, the
`p-contact may consist of, for example, Ag, Al, Au, Rh, Pt. A
`30 multilayer contact may include a very thin semitransparent
`ohmic contact in conjunction with a thick reflective layer
`which acts as a current spreading layer. An optional barrier
`layer is included between the ohmic layer and the reflective
`layer. One example of such a p-type multilayer contact is a
`35 gold/nickel oxide/aluminum contact. Typical thicknesses for
`this type of contact are 30 angstroms of gold, 100 angstroms
`of nickel oxide, and 1500 angstroms of aluminum. The
`n-contact of a III-nitride device may be, for example, Al, Ag,
`or a multilayer contact. A suitable n-type III-nitride multi-
`40 layer contact is titanium and aluminum with typical thick(cid:173)
`nesses of 30 angstroms of titanium and 1500 angstroms of
`aluminum. For a III-phosphide device, the p-contact may be,
`for example, Au:Zn, Au:Be, Al, Pt, Pd, Rh, or Ag. The
`n-contact of a III-phosphide device may be, for example,
`45 Au:Te, Au:Sn, Au:Ge, Ag, Al, Pt, Rh, or Pd.
`FIGS. 4A-4E illustrate an embodiment of the present
`invention at various stages during fabrication. In FIG. 4A,
`one or more n-type layers 11 are deposited epitaxially on a
`substrate 10. N-type layers 11 may include, for example, a
`50 buffer layer, a contact layer, an undoped crystal layer, and
`n-type layers of varying composition and dopant concentra(cid:173)
`tion. N-type layers may be deposited by, for example,
`MOCVD. An active region 12 is then formed on n-type
`layers 11. Active region 12 may include, for example, a set
`55 of quantum well layers separated by a set of barrier layers.
`One or more p-type layers 13 are then formed on the active
`region. P-type layers 13 may include, for example, an
`electron confining layer, a contact layer, and other p-type
`layers of various composition and dopant concentration.
`60 One or more p-metal layers 20 which will form the electrode
`or contact to p-type layers 13 is then deposited on p-type
`layers 13. P-metal 20 may be a highly reflective metal such
`as, for example, silver. When silver is used as p-metal 20, a
`thin metal layer for making ohmic contact, such as nickel, is
`65 optionally deposited under p-metal 20.
`P-metal 20 is then patterned as shown in FIG. 4B, using
`for example photolithography along with etching, or a
`
`IPR PAGE 17
`
`

`
`US 6,828,596 B2
`
`5
`lift-off process. The patterning removes any p-metal 20 that
`will not be used as a p-contact. The patterning thus removes
`any p-metal 20 overlying vias 14 shown in FIGS. 2 and 3.
`In FIG. 4C, an optional guard metal layer 50 is deposited
`over the remaining p-metal 20 and the exposed p-type layers
`13. Guard metal layer 50 is used for example when silver is
`used asp-metal 20. Guard metal layer 50 prevents the silver
`p-metal from migrating to other parts of the device. Guard
`metal layer 50 is then patterned and etched in one or more
`etching steps to form vias 14. Rather than etching, vias 14 10
`may be formed by selectively growing p-type layers 13 such
`that no p-type layer is grown where the vias are to be
`located. Or, vias 14 may be formed by implanting or
`diffusing n-type ions into the p-type region and active region
`located in the vias to form an n-type region in the vias, rather
`than etching away the p-type layer and active region in the
`via locations. Thus, vias 14 are not necessarily openings
`formed in the p-type layers 13 and the active region 12.
`A dielectric layer 22, such as for example aluminum
`oxide, is deposited in FIG. 4D to electrically isolate p-metal
`20 and guard metal 50 from an n-metal to be deposited in via
`14. Dielectric layer 22 may be any material that electrically
`isolates two materials on either side of dielectric layer 22.
`Dielectric layer 22 is patterned to remove a portion of the
`dielectric material covering n-type layer 11 at the bottom of
`via 14. Dielectric layer 22 must have a low density of
`pinholes to prevent short circuiting between the p- and
`n-contacts. In some embodiments, dielectric layer 22 is
`multiple dielectric layers.
`In FIG. 4E, n-metal 21 is deposited in via 14. Interconnect
`15a, which connect the n-metal deposited in each via, may
`also be deposited at this time.
`Making contact to the n-type layers of a light emitting
`device using an array ofvias 14 as shown in FIG. 2 may offer 35
`several advantages. First, the use of vias reduces the amount
`of lateral current spreading required in the device by reduc(cid:173)
`ing the maximum distance from any point underlying the
`p-contact to any point underlying then-contact. Calculations
`show that the current spreading resistance in the n-type
`layers of large area LEDs having then-type layer contacted
`in an array of vias can be reduced by a factor of 10 to 20.
`Reduction of the device resistance also reduces the normal
`operating voltage of the device, which enhances the wall
`plug efficiency of the device. The wall plug efficiency of a
`device is defined as the ratio of optical watts out to electrical
`watts put into the device. Thus, for injection of the same
`current density through the active region, a device such as
`that shown in FIG. 2 would require less forward voltage than
`a device such as that shown in FIG. 1. Furthermore, the 50
`reduced distance over which current spreading occurs in the
`n-type semiconductor layer results in more uniform current
`density in the active region which leads to more uniform
`operation and light output of the device. In addition, less
`resistance means that less heat is generated in the device,
`which also leads to more efficient light generation through
`reduced junction temperature. A reduction in heat output
`may also simplify submount design, since less heat needs to
`be dissipated by the connection to the submount.
`Second, when vias are used to make contact to the n-type
`layer as shown in FIG. 2, instead of a single large contact as
`shown in FIG. 1, the area utilization ratio of the device
`increases. The area utilization ratio is defined as the ratio of
`the p-metal area to the surface area of the side of the device
`on which the contacts are formed. An increase in area
`utilization ratio means that the device has more active
`region, since the active region underlies the p-metal, and
`
`6
`therefore can generate more light. Also, an increase in area
`utilization ratio means an increase in the area of the highly(cid:173)
`refiective p-contact. Thus, a greater fraction of the light
`incident on the contact side of the device is incident on the
`5 highly-reflective p-contact, thereby decreasing the absorp(cid:173)
`tion of the light which is generated within the device. For a
`1 square millimeter device using vias for the n-contact, the
`area utilization ratio may exceed 80%, compared to 68% for
`a finger-contact scheme as shown in the device of FIG. 1.
`Third, the use of vias instead of a large n-contact can
`simplify the design of the submount, by making the arrange(cid:173)
`ment of the submount connections to the p-metal and
`n-metal arbitrary. The ability to make arbitrarily-arranged
`submount connections is illustrated in FIGS. 5, 6, and 7.
`15 FIG. 5 is a plan view of a large junction device (i.e. an area
`greater than or equal to 0.2 square millimeters) using vias.
`Vias 14 are interconnected by horizontal interconnections
`15a and vertical interconnections 15b. Interconnections 15a
`and 15b may be, for example, 10 microns wide. FIG. 5 also
`20 shows a possible submount connection. Submount connec(cid:173)
`tion layers 16 and 17 make electrical connection between the
`light emitting device and the submount while providing a
`thermal path for heat removal during operation. Submount
`connection layers 16 and 17 may be solder layers, or any
`25 other type of conductive connection between the submount
`and the device such as elemental metals, metal alloys,
`semiconductor-metal alloys, thermally and electrically con(cid:173)
`ductive pastes or compounds (e.g. epoxies), eutectic joints
`between dissimilar metals between the light emitting device
`30 and the submount (e.g. Pd-In-Pd), gold stud-bumps, or
`solder bumps. Submount connection 16 connects to portions
`of the p-metal of the device, and submount connection 17
`connects to the n-metal deposited in some vias and the
`interconnects 15a and 15b connecting the vias.
`As is shown in FIG. 5, the interconnected vias form a grid
`over the device. Though only then-metal in vias 14 contact
`the n-type layer, interconnects 15a and 15b are electrically
`connected to the vias and are thus electrically connected to
`the n-type layers. Accordingly, both vias 14 and intercon-
`40 nects 15a and 15b are available as n-contacts to a submount.
`Unlike then-contact shown in FIG. 1, vias 14 and intercon(cid:173)
`nects 15a and 15b are not confined to a particular area on the
`chip. Similarly, the grid formed by vias 14 and interconnects
`15a and 15b encloses an array of nine p-contact sections
`45 available as p-contacts to a submount. Like the n-contacts,
`the p-contact sections are not confined to a particular area on
`the chip. Thus, since p-contacts and n-contacts are located in
`many places on the chip, the submount connections are not
`limited by the shape and location of the p- and n-contacts.
`FIG. 6 is a cross section of the device shown in FIG. 5,
`taken along axis AA. Then-type layers 11, active region 12,
`p-type layers 13, and p-metal 20 are formed for example as
`described above in reference to FIGS. 4A-4E. Optional
`guard layer 50 is omitted for clarity. The vias are isolated
`55 from the p-type layers and p-metal contacts by dielectric
`layer 22. An n-metal may then be deposited over the entire
`chip and patterned to form n-contacts 21 in vias 14 and
`interconnects 15a and 15b. A horizontal interconnect 15a is
`shown in FIG. 6. A second dielectric layer 23 is then
`60 deposited over the chip. The second dielectric layer 23 is
`patterned to create a first set of openings aligned with
`p-metal regions 20 on the side of the device underlying
`submount connection 16, and a second set of openings
`aligned with vias 14 and interconnects 15a and 15b on the
`65 side of the device underlying submount connection 17.
`Since submount connection 16 is the p-contact to the
`submount, dielectric layer 23 isolates submount connection
`
`IPR PAGE 18
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`

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`US 6,828,596 B2
`
`5
`
`35
`
`7
`16 from interconnects 15a and 15b. Since submount con(cid:173)
`nection 17 is the n-contact to the submount, dielectric layer
`23 is removed from the interconnects and vias underlying
`layer 17 such that submount connection 17 can make
`electrical contact with vias 14 and interconnects 15a and
`15b.
`FIG. 7 is a cross section of the device shown in FIG. 5,
`taken along axis BB. Submount connection 16 is to make
`contact to p-metal 20, thus in the area directly underlying
`submount connection 16, all of dielectric layer 23 is 10
`removed, except the portion covering vertical interconnects
`15b. Submount connection 17 is to make contact to the
`n-metal and interconnects, thus in the area underlying sub(cid:173)
`mount connection 17 dielectric layer 23 is removed only
`from the top surface of vertical interconnects 15b. P-metal
`layer 20 is thus isolated from submount connection 17 by
`dielectric layer 23. Submount connections 16 and 17 need
`not be deposited as shown in FIG. 5. Other configurations
`are possible by properly patterning dielectric layer 23.
`The ability to make arbitrary connections to the submount
`provides several advantages. Large conductive submount
`connections as shown in FIG. 5 may be easier and cheaper
`to deposit on the device than one or multiple smaller
`submount connections. For example, in the device shown in
`FIG. 5, solder layers can easily by deposited for submount
`connections 16 and 17 by screen or stencil printing. In
`contrast, the device shown in FIG. 1 requires solder bumps
`in order to contact the n-electrode. Solder bumps are costly
`and require tight manufacturing tolerances. Screen printing
`solder is comparatively cheaper and simpler. Also, large 30
`conductive submount connections dissipate more heat from
`the LED flip chip than smaller connections. As is known in
`the art, cooler light emitting devices typically generate more
`light than warmer devices and offer improved operation
`lifetime.
`FIG. 8 is a plan view of a small junction device (i.e. an
`area less than one square millimeter) using vias. FIG. 9 is a
`cross section of the device shown in FIG. 8, taken along axis
`CC. The device shown in FIGS. 8 and 9 has a single via 14
`etched down ton-type layer 11. Ann-contact 21 is deposited
`in via 14. N-via 14 is located at the center of the device to
`provided from improved uniformity of current and light
`emission. A highly reflective p-contact 20 is deposited on
`p-type layer 13. An optional guard metal layer 50 covers 45
`reflective p-contact 20, and a thick p-metal layer 20a is
`deposited over guard metal layer 50. N-contact 21 is sepa(cid:173)
`rated from the three p-metal layers 20, 50, and 20a by one
`or more dielectric layers 22. A p-submount connection 16
`connects top-metal layer 20a and an n-submount connection 50
`17 connects ton-metal layer 21, for connecting the device to
`a submount.
`As illustrated in FIG. 8, the device is connected to a
`submount by three submount connections, two p-submount
`connections 16 and one n-submount connection 17. 55
`N-submount connection 17 may be located anywhere within
`n-contact region 21 (surrounded by insulating layer 22) and
`need not be located directly over via 14. Similarly,
`p-submount connections 16 may be located anywhere on
`p-metal layer 20a. As a result, the connection of the device 60
`to a submount is not limited by the shape or placement of
`p-contact 20a and n-contact 21.
`In large or small junction devices, vias may be used in
`conjunction with larger contacts. FIG. 15 is a plan view of
`a small junction device. FIG. 14 is a cross section along axis
`DD of the device shown in FIG. 15. As illustrated in FIG. 15,
`a device may include one or more vias 21 together with a
`
`8
`continuous n-contact ring 25 surrounding the active region.
`FIG. 14 illustrates that via 21 and ring 25 are electrically
`connected by interconnect 15a. Ring 25 reduces the distance
`current must spread laterally and hence reduces the series
`resistance of the device. The device illustrated in FIGS. 14
`and 15 shows a small junction device with a single via. Ring
`25 from FIGS. 14 and 15 may also be used in large junction
`devices with more than one via 21.
`Although the examples above describe the interconnects
`between the light emitting device die and the submount as
`being solder, any suitable interconnect may be used. For
`example, the interconnects may be elemental metals, metal
`alloys, semiconductor-metal alloys, solders, thermally and
`electrically conductive pastes or compounds such as epoxy,
`15 eutectic joints such as Pd-In-Pd, Au stud bumps, or
`solder bumps.
`FIG. 10 is an expl