`
`Paper:
`Entered:
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_____________________
`
`
`
`
`
`HTC CORPORATION, HTC AMERICA, INC., AND APPLE INC.,
`Petitioners,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner
`
`_____________________
`
`
`
`Case IPR2016-011211
`Patent No. 5,960,464
`
`_____________________
`
`
`
`PETITIONER’S REPLY
`
`
`
`
`1 Case IPR2017-00513 has been joined with this proceeding.
`
`

`

`
`
`I.
`
`II.
`
`
`
`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
`
`
`
`
`
`
`
`TABLE OF CONTENTS
`
`Introduction ...................................................................................................... 1
`
`The combination of Gulick and Nale renders obvious the
`“continuous use” limitation. ............................................................................ 2
`
`A.
`
`B.
`
`The combination of Gulick and Nale teaches a control
`circuit “configured to request continuous use of several
`portions of the main memory from the operating system”
`as recited in claims 1, 10, and 19. ......................................................... 2
`
`A POSITA reading Gulick and Nale would have known
`how to request “continuous use” of a block of memory
`from an operating system. ..................................................................... 4
`
`1.
`
`2.
`
`A POSITA reading Nale would have understood
`Nale to “request continuous use” of memory for
`each graphic mode. ..................................................................... 6
`
`The evidence in the record establishes that a
`POSITA reading Nale would have known that the
`allocated memory was for “continuous use.” ............................. 7
`
`3. Whether Nale uses virtual or physical memory is
`irrelevant to whether the combination of Gulick
`and Nale renders the “continuous use” limitation
`obvious. ....................................................................................... 9
`
`C.
`
`Patent Owner seeks to improperly import a “locked
`down” requirement into the claim limitation. .....................................11
`
`III. A POSITA would have been motivated to combine the
`teachings of Nale with the disclosure of Gulick. ...........................................13
`
`IV. Gulick combined with Nale renders obvious claims 3-4, 7-8,
`12-13, 16-17, and 20-23. ...............................................................................19
`
`V.
`
`Conclusion .....................................................................................................20
`
`VI. Certificate of Word Count .............................................................................21
`
`
`
`ii
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`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`PETITIONER’S UPDATED EXHIBIT LIST
`
`June 9, 2017
`
`Description
`
`Exhibit
`Ex. 1001 U.S. Patent No. 5,960,464
`Ex. 1002 Prosecution History of U.S. Patent No. 5,960,464
`Ex. 1003 Declaration of Robert Colwell, Ph.D., Under 37 C.F.R. § 1.68
`Ex. 1004 Curriculum Vitae of Robert Colwell, Ph.D.
`Ex. 1005 U.S. Patent No. 5,797,028 to Gulick et al. (“Gulick”)
`Ex. 1006 U.S. Patent No. 5,793,385 to Nale (“Nale”)
`Ex. 1007 Reserved
`Ex. 1008 U.S. Patent No. 5,680,482 to Liu et al. (“Liu”)
`Ex. 1009
`Intel 82430FX PCISet Datasheet 82437FX System Controller (TSC)
`and 82438FX Data Path Unit (TDP), Intel Corporation, June 1995
`Ex. 1010 Joint Claim Construction and Prehearing Statement, Parthenon
`Unified Memory Architecture LLC v. Apple Inc., case no. 2:15-cv-632-
`JRG-RSP (Feb. 16, 2016, E.D. Tex.)
`Ex. 1011 Decision of Institution of Inter Partes Review, Samsung Elec. Co.,
`Ltd., et al. v. Parthenon Unified Memory Architecture LLC, IPR2015-
`01946 (Paper No. 7)
`Ex. 1012 Claim Construction Memorandum Opinion and Order, Parthenon
`Unified Memory Architecture LLC v. ZTE Corp. et al., No. 2:15-CV-
`00225 (E.D. Tex.)
`Ex. 1013 Claim Construction Memorandum Opinion and Order, Parthenon
`Unified Memory Architecture LLC v. Samsung Elecs. Co. Ltd. et al.,
`No. 2:14-CV-00902 (E.D. Tex.)
`Ex. 1014 Claim Construction Memorandum Opinion and Order, Parthenon
`Unified Memory Architecture LLC v. HTC Corp. et al., 2:14-CV-
`00690 (E.D. Tex.)
`Ex. 1015 U.S. Patent No. 5,649,029 (“Galbi”)
`Ex. 1016 Parthenon Unified Memory Architecture LLC v. Apple Inc., case no.
`2:15-cv-632-JRG-RSP, Document No. 10 (June 16, 2015, E.D. Tex.)
`
`
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`iii
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`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`
`
`Description
`Exhibit
`Ex. 1017 Declaration of Yakov Zolotorev in Support of Motion for Pro Hac
`Vice Admission
`Ex. 1018 Deposition Transcript of Dr. Mitchell A. Thornton
`Ex. 1019 Second Expert Declaration of Dr. Robert Colwell
`
`
`
`iv
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`

`

`
`Introduction
`
`
`
`I.
`
`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`
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`The Petition and the record as a whole provides detailed reasons why a
`
`person of skill in the art (“POSITA”) would have understood Gulick and Nale to
`
`render obvious each and every element of the challenged claims. None of Patent
`
`Owner’s arguments overcome the express teachings of this combination.
`
`Accordingly, the Board should find claims 1, 3-4, 7-8, 10, 12-13, 16-17, and 19-23
`
`unpatentable in its Final Written Decision.
`
`In its Response, Patent Owner presents two arguments—that Nale does not
`
`teach “continuous use” and that a person of ordinary skill in the art (POSITA)
`
`would not combine Gulick and Nale. With regard the first argument, Patent Owner
`
`erroneously imports a limitation from the specification into the claims by requiring
`
`that memory be “locked down” in order to be in “continuous use.” This argument
`
`ignores what a POSITA would have understood from the teachings of Nale (e.g.,
`
`allocated memory would not be released until a change in mode removed the need
`
`for that memory).
`
`With regard to the second argument, Patent Owner relies on a bodily
`
`incorporation of Nale’s address translator into Gulick’s system. Such attempts to
`
`disprove obviousness via bodily incorporation are improper. Rather, the Petition
`
`establishes that a POSITA would have been motivated to combine the memory
`
`interfacing teachings of Nale with the control circuit (chipset) teaching of Gulick
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`
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`1
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`

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`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`and that the combination would have taught “the control circuit being configured
`
`
`
`
`
`
`
`to request continuous use of several portions of the main memory from the
`
`operating system.” Thus, Patent Owner’s argument is unpersuasive because it fails
`
`to addresses the reasons provided in the Petition for why a POSITA would make
`
`the combination.
`
`Accordingly, Gulick combined with Nale renders obvious claims 1, 3-4, 7-8,
`
`10, 12-13, 16-17, and 19-23. For the reasons shown in the Petition and below, the
`
`challenged claims of the ’464 patent are unpatentable.
`
`II. The combination of Gulick and Nale renders obvious the “continuous
`use” limitation.
`
`Patent Owner argues that the combination Gulick and Nale does not render
`
`obvious each and every limitation of the challenged claims. Patent Owner,
`
`however, focuses on one limitation (“request[ing] continuous use”) of claim 1, and
`
`the similar limitations in claims 10 and 19. Response, Paper No. 25 (“Response”),
`
`at 6-10. As discussed below, Patent Owner’s argument is unpersuasive.
`
`A. The combination of Gulick and Nale teaches a control circuit
`“configured to request continuous use of several portions of the
`main memory from the operating system” as recited in claims 1,
`10, and 19.
`
`According to Patent Owner, the combination of Gulick and Nale fail to
`
`render obvious “the control circuit being configured to request continuous use of
`
`several portions of the main memory from the operating system.” Response at 5.
`
`
`
`2
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`

`

`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`None of Patent Owner’s arguments, however, are persuasive in rebutting the
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`
`
`
`
`
`
`simple fact that a POSITA was already well-versed in implementing such
`
`“continuous use,” as already set forth in the Petition.
`
`In particular, as established in the Petition, Gulick teaches a chipset (control
`
`circuit) that “is preferably similar to the Triton chipset.” Petition, Paper No. 2
`
`(“Petition”), at 34. Nale enhances the disclosure of Gulick by further teaching
`
`specific functionalities provided by such chipsets, such as how memory can be
`
`requested for continuous use. Id. at 34-35.
`
`Specifically, Nale teaches a memory interfacing technique that interacts with
`
`an operating system to allocate memory blocks for a graphics controller: “upon a
`
`request to the operating system” several portions of main memory are dynamically
`
`allocated to the graphics controller. Ex. 1006 (Nale) at 4:19-22; 4:30-31. This
`
`“dynamic allocat[ion]” includes the operating system responding with “starting
`
`addresses of available memory blocks,” which are written to locations in a look-up
`
`table. Id. at 6:13-23.
`
`When the operating system in Nale allocates memory blocks for a graphics
`
`controller, it is for the continuous use of the graphics controller. Petition at 34-37;
`
`Ex. 1003 (Colwell Decl.) at pp. 42-45 (the requests in Nale would include “a
`
`mechanism to instruct the operating system to treat the allocated blocks as
`
`nonswappable until released.”). Consequently, this allocation of the memory
`
`
`
`3
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`

`

`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`blocks in Nale (in combination with Gulick’s control circuit teachings) renders
`
`
`
`
`
`
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`obvious the recited “control circuit being configured to request continuous use of
`
`several portions of the main memory from the operating system.”
`
`Thus, Gulick’s chipset (control circuit) teaching, combined with Nale’s
`
`teachings of translating memory addresses and requesting allocation of memory
`
`blocks for continuous use by the requesting device, discloses the “continuous use”
`
`limitation.
`
`B. A POSITA reading Gulick and Nale would have known how to
`request “continuous use” of a block of memory from an operating
`system.
`
`Patent Owner argues that neither Gulick nor Nale teach the “continuous use”
`
`limitation on the basis that a POSITA would not understand Nale’s request to
`
`include instructing an operating system to treat the allocated blocks as
`
`nonswappable until released. Response at 7-10. However, Patent Owner’s
`
`argument is incorrect as it contradicts the teachings of the prior art, the knowledge
`
`of POSITAs at the time, and the Background of the ’464 patent itself. In the end,
`
`Patent Owner’s arguments do not change the conclusion that a POSITA, reading
`
`Nale’s teachings, would have understood Nale to teach “request[ing] continuous
`
`use of several portions of the main memory from the operating system.”
`
`According to the Federal Circuit, “[w]hether a claimed invention would have
`
`been obvious is a question of law, based on factual determinations regarding the
`
`
`
`4
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`

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`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`scope and content of the prior art, differences between the prior art and the claims
`
`
`
`
`
`
`
`at issue, the level of ordinary skill in the pertinent art, and any objective indicia of
`
`nonobviousness.” Randall Mfg. v. Rea, 733 F.3d 1355, 1362 (Fed. Cir. 2013)
`
`(citing KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007)). “In KSR, the
`
`Supreme Court criticized a rigid approach to determining obviousness based on the
`
`disclosures of individual prior art references, with little recourse to the knowledge,
`
`creativity, and common sense that an ordinarily skilled artisan would have brought
`
`to bear when considering combinations or modifications.” Id. (citing KSR, 550
`
`U.S. at 415-22).
`
`Instead of focusing on individual documents, “the Court required an analysis
`
`that reads the prior art in context, taking account of ‘demands known to the design
`
`community,’ ‘the background knowledge possessed by a person having
`
`ordinary skill in the art,’ and ‘the inferences and creative steps that a person of
`
`ordinary skill in the art would employ.’” Id. (emphasis added) (citing KSR, 550
`
`U.S. at 418). Moreover, “[i]n recognizing the role of common knowledge and
`
`common sense,” the Court has “emphasized the importance of a factual foundation
`
`to support a party’s claim about what one of ordinary skill in the relevant art would
`
`have known.” Id.
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`
`
`5
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`

`

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`
`
`
`1.
`
`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`A POSITA reading Nale would have understood Nale to
`“request continuous use” of memory for each graphic mode.
`
`
`
`
`
`As noted above, Nale teaches a memory interfacing technique that interacts
`
`with an operating system to allocate memory blocks for a graphics controller:
`
`“upon a request to the operating system” several portions of main memory are
`
`dynamically allocated to the graphics controller. Ex. 1006 (Nale) at 4:19-22; 4:30-
`
`31. This “dynamic allocat[ion]” includes the operating system responding with
`
`“starting addresses of available memory blocks,” which are written to locations in
`
`a look-up table. Id. at 6:13-23. In Nale, the request is made to “the operating
`
`system” when “the graphics mode is changed” for additional needed memory. Id.
`
`at 6:13-15. In turn, the operating system responds with the “starting addresses of
`
`available memory blocks.” Id. at 6:15-17. Accordingly, a POSITA would have
`
`understood that the memory allocated by the operating system to the graphics
`
`controller would be maintained for the graphics controller until the graphic mode is
`
`changed. Petition at 34-35; Ex. 1003 (Colwell Decl.) at pp. 43-44; Ex. 1019
`
`(Colwell Supp. Decl.) ¶ 2.
`
`Dr. Thornton confirms this as well by stating in deposition that: “I don’t
`
`think that Nale contemplated anything other than it says that there is a dynamic
`
`allocation whenever the graphics modes change. So that would insinuate that
`
`when it changes to a smaller mode, that it would release those blocks. Otherwise,
`
`
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`6
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`

`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`it would be a pretty bad design.” Ex. 1018 (Thornton Depo.) at 59:6-16 (emphasis
`
`
`
`
`
`
`
`added). Dr. Thornton also agrees that “one of skill in the art would know how to
`
`retain memory” and that Nale would be included in that understanding. Id. at
`
`61:18-62:3; Ex. 1019 (Colwell Supp. Decl.) ¶ 3.
`
`Thus, a POSITA reading Nale would have understood Nale to include
`
`allocating memory for “continuous use” for the graphics controller operating in a
`
`particular graphic mode.
`
`2.
`
`The evidence in the record establishes that a POSITA
`reading Nale would have known that the allocated memory
`was for “continuous use.”
`
`A POSITA reading Nale would have known that the memory allocated to
`
`the graphics controller was for “continuous use” in order to prevent the
`
`reallocation of that memory to another process. See Ex. 1003 (Colwell Decl.) at pp.
`
`43-44. Additionally, according to Dr. Thornton, “[o]ne of skill would know how to
`
`make sure that they could prevent an operating system from reallocating memory
`
`to another process. They would know how to do that.” Ex. 1018 (Thornton Depo.)
`
`at 54:22-55:8. Thus, POSITAs reading Nale would have understood that Nale’s
`
`allocation of memory was for “continuous use.” Ex. 1019 (Colwell Supp. Decl.) ¶
`
`4.
`
`This is further established by the Background section of the ’464 Patent,
`
`which provides three examples known to POSITAs for allocating memory for
`
`
`
`7
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`

`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`continuous use. In a first example, “two or more identical processors [] each access
`
`
`
`
`
`
`
`the same block of main memory” and the second processor cannot access a portion
`
`of memory in use by the first processor until the first processor is done with it. Ex.
`
`1001 (’464 Patent) at 2:25-30. In a second example, directed to unified memory for
`
`graphics, a video accelerator causes a reservation of a portion of main memory
`
`during boot-up that prohibits other applications from accessing it. Id. at 2:37-51. In
`
`a third example, the Windows 95 operating system “dynamically allocates memory
`
`to an application . . . [and] as soon as the application no longer uses the memory,
`
`Windows 95 allocates that memory to another application.” Id. at 2:52-59. Thus,
`
`these examples and Dr. Thornton all confirm the obvious—that various types of
`
`“continuous use” (i.e., the allocation of memory that is released when the
`
`requesting application no longer requires it) were well known to POSITAs before
`
`the ’464 Patent. Ex. 1019 (Colwell Supp. Decl.) ¶ 5.
`
`This evidence from Dr. Thornton and the Background section of the ’464
`
`Patent is consistent with Dr. Colwell’s declaration cited in the Petition, (see Ex.
`
`1003 (Colwell Decl.) at p. 44), and represents the general knowledge that a
`
`POSITA would have had regarding how to “make sure they could prevent an
`
`operating system from reallocating to another process.” See Ex. 1018 (Thornton
`
`Depo.) at 55:5-8. Consequently, the background knowledge of a POSITA would
`
`have included knowing how to allocate blocks of memory such that the operating
`
`
`
`8
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`

`

`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`system would not reallocate, swap, or otherwise modify these blocks until released.
`
`
`
`
`
`
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`Ex. 1019 (Colwell Supp. Decl.) ¶ 6. Thus, the evidence of record shows that a
`
`POSITA would have known that Nale’s memory allocation to the graphics
`
`controller by the operating system when the graphic mode changes is a “request for
`
`continuous use.”
`
`3. Whether Nale uses virtual or physical memory is irrelevant
`to whether the combination of Gulick and Nale renders the
`“continuous use” limitation obvious.
`
`Patent Owner ignores the background knowledge of a POSITA (discussed
`
`above) and instead argues over whether “[a] person having ordinary skill in the art
`
`would have understood, reading Nale, that the request would include a mechanism
`
`to instruct the operating system to treat the allocated blocks as nonswappable until
`
`released.” See Response at 8; see also Petition at 36; Ex. 1003 (Colwell Decl.) at
`
`pp. 44-45. Patent Owner is of the opinion that “[a] POSA would not understand
`
`Nale to be using a virtual memory system where the concept of ‘swapping’ is
`
`relevant.” Response at 8. However, the type of memory system used in Nale,
`
`whether virtual or physical, is irrelevant to whether the combination of Gulick and
`
`Nale teaches a “request for continuous use” of memory to a POSITA.
`
`In fact, Patent Owner’s argument ignores the background knowledge of a
`
`POSITA and is not conducting “the Court required [] analysis” of “read[ing] the
`
`prior art in context, taking account of ‘demands known to the design community,’
`
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`9
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`

`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
`
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`‘the background knowledge possessed by a person having ordinary skill in the
`
`
`
`
`
`
`
`art,’ and ‘the inferences and creative steps that a person of ordinary skill in the art
`
`would employ.’” Randall Mfg., 733 F.3d at 1362 (emphasis added). Patent
`
`Owner’s argument also fails to establish how the concept of virtual memory is
`
`beyond the understanding of a POSITA when applying Gulick and Nale to the
`
`challenged claims. To the contrary, as discussed above, the background knowledge
`
`of a POSITA would include multiple methods of allocating memory for continuous
`
`use including making the memory nonswappable as set forth in the Petition.
`
`Even if Patent Owner is attempting to argue that virtual memory concepts
`
`are outside the scope of the claims, the only embodiment described in the ’464
`
`Patent is “a Windows 95 -based application” that “perform[s] operations on what
`
`appears to be a 2-megabyte continuous block of main memory.” See Ex. 1001
`
`(’464 Patent) at 3:29-31, 7:1-50. Moreover, Dr. Thornton admits that the Windows
`
`95 operating system utilizes virtual memory management techniques. Ex. 1018
`
`(Thornton Decl.) at 23:20-25 (“Q. . . . And, to your knowledge, did Windows 95
`
`use virtual memory? A. It did have a provision for use of virtual memory.”). Thus,
`
`Patent Owner’s argument about whether a POSITA reading Nale would understand
`
`the memory allocated to the graphics controller to be “nonswappable” is not only a
`
`red-herring, but also disingenuous about the scope of the disclosure and the claims
`
`in the ’464 Patent.
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`
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`10
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`

`
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`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
`
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`Accordingly, Patent Owner’s arguments that the combination of Gulick and
`
`
`
`
`
`Nale fail to render obvious the “continuous use” limitation fail and the Board’s
`
`findings in the Institution Decision should be maintained.
`
`C.
`
`Patent Owner seeks to improperly import a “locked down”
`requirement into the claim limitation.
`
`As discussed above, Patent Owner argues that neither Gulick nor Nale
`
`disclose a control circuit that “requests continuous use of several portions of the
`
`main memory” because “[a] POSA would understand that when the claimed
`
`control circuit requests ‘continuous’ use of a portion of memory, it is requesting
`
`that the portion of memory be locked down for a specific duration of time.”
`
`Response at 6 (citing Ex. 2003 (Thornton Decl.) ¶ 35). While this argument fails
`
`for the reasons given above, it also fails because it improperly attempts to import
`
`limitations into claims.
`
`“[I]t is improper to read limitations from a preferred embodiment described
`
`in the specification—even if it is the only embodiment—into the claims absent a
`
`clear indication in the intrinsic record that the patentee intended the claims to be so
`
`limited.” Liebel-Flarsheim Co. v. Medrad, Inc., 358 F. 3d 898, 913 (Fed. Cir.
`
`2004); see also Phillips v. AWH Corp., 415 F. 3d 1303, 1323 (Fed. Cir. 2005)
`
`(there exists a “danger of reading limitations from the specification into the
`
`claims”).
`
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`11
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`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
`
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`Patent Owner’s reliance on this embodiment from the specification clearly
`
`
`
`
`
`violates the prohibition against importing limitations into the claims. See Phillips,
`
`415 F. 3d at 1323. The claim language merely recites “request continuous use of
`
`several portions” of memory. The claims do not recite any additional language
`
`requiring that all of the memory be allocated in a particular way, that all of the
`
`memory be allocated at a particular time (i.e., at initiation v. while processing), or
`
`that all of the memory be allocated using a particular technique (i.e., locked down
`
`v. some other memory reservation technique).
`
`Moreover, Patent Owner has not pointed to a single instance of a clear
`
`indication in the intrinsic record that the claims are to be so limited. See Liebel-
`
`Flarsheim, 358 F. 3d at 913. In fact, the specification of the ’464 patent states the
`
`opposite—that the claims should not be limited to the specific embodiments
`
`disclosed in the specification. See Ex. 1001, 9:30-34 (“Although specific
`
`embodiments of, and examples for, the present invention have been described
`
`herein for purposes of illustration, various equivalent modifications can be made
`
`without departing from the spirit and scope of the invention, as will be known by
`
`those skilled in the relevant art.”).
`
`Consequently, the “continuous use” limitation in the independent claims
`
`cannot be limited solely as Patent Owner alleges to require “locking down” the
`
`memory. See Phillips, 415 F. 3d at 1323; Liebel-Flarsheim, 358 F. 3d at 913. As
`
`
`
`12
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`

`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
`
`
`demonstrated above, Petitioner has shown that a POSITA reading Nale would
`
`
`
`
`
`
`
`understand that memory requested from an operating system would be in
`
`continuous use and would not be reallocated until the graphics mode changes.
`
`III. A POSITA would have been motivated to combine the teachings of Nale
`with the disclosure of Gulick.
`
`Patent Owner further argues that “[a] POSA would not be motivated to
`
`combine Gulick and Nale.” Response at 10. According to Patent Owner, the reason
`
`for this is “because Nale’s address translator is incompatible” with Gulick’s
`
`decoding systems. Id. This supposed incompatibility is because Nale’s address
`
`translator is “designed to work with ‘a graphics controller’,” and “Nale’s graphics
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`controller is not a decoder.” Id. at 10-11. Patent Owner further argues that Nale is
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`incompatible because, “[i]f placed in Gulick’s system, Nale’s address translator
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`would never allocate memory to the ‘MPEG digital signal processor chip’.”
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`Response at 11-12 (citing Ex. 2003 (Thornton Decl.) ¶ 40).
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`These assertions fail because (1) they attempt to impose an improper “bodily
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`incorporation” requirement; (2) they fail to recognize that the Petition consistently
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`relies on the teachings of Nale with respect to memory interfacing functions,
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`including the translation of addresses between contiguous and non-contiguous
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`addresses in combination with the teachings of Gulick; and (3) they fail to
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`recognize that Nale was within the scope of the prior art that a POSITA would
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`have considered.
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`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`First, Patent Owner errs in arguing that the bodily incorporation of Nale’s
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`address translator would be incompatible with Gulick’s “MPEG decoding digital
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`signal processor chip” (or with Gulick generally). This is because “[t]he test for
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`obviousness is not whether the features of a secondary reference may be bodily
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`incorporated into the structure of the primary reference.” Allied Erecting and
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`Dismantling Co., Inc. v. Genesis Attachments, LLC, 825 F.3d 1373, 1381 (Fed. Cir.
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`2016) (quoting In re Keller, 642 F.2d 413, 425 (CCPA 1981)). Instead, the test is
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`whether “a skilled artisan would have been motivated to combine the teachings of
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`the prior art references to achieve the claimed invention.” Id.
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`Patent Owner engages in precisely the legal error that the Federal Circuit
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`cautions to avoid. This is evident by the assertion that Nale’s address translator is
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`“not compatible with a decoder,” allegedly because “Nale’s graphics controller is
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`not a decoder” or because memory would “never [be] allocate[d]” to Gulick’s
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`MPEG decoder. Response at 11, 12. In other words, Patent Owner’s argument
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`erroneously attempts to bodily incorporate Nale’s address translator operating with
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`a graphics controller into Gulick. Further, Patent Owner does not actually address
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`anything related to the actual test, that of whether there was a motivation to
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`combine the teachings of Nale with the teachings of Gulick.
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`This leads to the second point, namely how a POSITA would be motivated
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`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`to combine the teachings of Nale with that of Gulick. A POSITA would have
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`understood memory interfacing functions for shared memories to be part of
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`Gulick’s chipset, and Nale teaches specific examples of memory interfacing
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`functions, including address translation between contiguous and non-contiguous
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`addresses. See Petition at 34-35.
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`A POSITA, faced with the disclosure of Gulick with respect to the MPEG
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`decoder/DSP engine of Gulick’s digital system chip, would have been motivated to
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`look to teachings within the art regarding how to interface with a shared memory.
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`Nale provides interfacing teachings for requesting devices/processes using a shared
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`memory. Ex. 1003 (Colwell Decl.) ¶¶ 69-70. It is therefore inapposite that the
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`address translation occurs in Nale’s example with a graphics controller, since the
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`question turns instead to whether a POSITA would have been motivated to
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`combine the teachings. A POSITA would have looked to the teachings of Nale for
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`a variety of reasons. See Petition at 22-25.
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`Third, a POSITA would have been further motivated to turn to Nale when
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`reading Gulick because Nale was within the scope of the prior art that would have
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`been considered. see also KSR, 550 U.S. at 420 (“any need or problem known in
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`the field of endeavor at the time of the invention and addressed by the patent . . .
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`can provide a reason for combining the elements in the manner claimed.”). In fact,
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`here, the ’464 Patent and Nale are both involved in overlapping fields of endeavor.
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`Ex. 1019 (Colwell Supp. Decl.) ¶¶ 7-9.
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`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`According to the ’464 Patent, it “relates to the field of electronic systems
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`requiring blocks of memory.” Ex. 1001 (’464 Patent) at 1:19-20. The ’464 Patent
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`then gives an example of “electronic systems” that use “decompression devices,
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`such as audio and/or video decompression.” Id. at 1:20-22. As part of the related
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`art, the ’464 Patent discusses computers “employ[ing] graphics of video
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`accelerator cards.” Id. at 2:1-3. Even Dr. Thornton agrees that graphics accelerators
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`were part of the related art of the ’464 Patent background. Ex. 1018 (Thornton
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`Depo.) at 66:20-23 (“Q. And the particular related art that he [the inventor]
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`mentions in this example is a graphics accelerator with this feature. Right? A.
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`Correct.”); Ex. 1019 (Colwell Supp. Decl.) ¶ 10.
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`Further, it was known to a POSITA that graphics accelerators were used in
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`cooperation with graphics controllers. Ex. 1019 (Colwell Supp. Decl.) ¶ 11. Dr.
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`Thornton’s testimony is consistent with this understanding:
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`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`Ex. 1018 (Thornton Depo.) at 68:2-12.
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`Dr. Thornton also agrees, in answer to a question about video accelerators,
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`that “one would use a graphics controller. It wouldn’t make sense to accelerate the
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`graphics and then—I mean, there could be a case where you were processing
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`graphics without displaying it, but in general you would find those both
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`together.” Id. at 69:4-8 (emphasis added). Accordingly, graphics controllers are in
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`the related art, since they are accelerated by the graphics accelerators admitted to
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`be in the related art to the ’464 Patent. Ex. 1019 (Colwell Supp. Decl.) ¶ 12. A
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`POSITA would have therefore turned to the teachings of Nale when considering
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`the ’464 Patent because graphics controllers are in the same general field of the
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`’464 Patent, including “electronic systems requiring blocks of memory.” Id.
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`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`Finally, both graphics controllers (e.g., example given in Nale) and MPEG
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`decoders (e.g., example given in Gulick), were known to require contiguous
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`memory. Ex. 1019 (Colwell Supp. Decl.) ¶ 13. The ’464 Patent acknowledges this,
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`stating that “MPEG 2 decoding requires 2 megabytes of contiguous memory.” Ex.
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`1001 (’464 Patent) at 2:59-61. Nale recognized the same need with respect to
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`graphics controllers: “most graphics controllers are designed to address contiguous
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`memory.” Ex. 1006 (Nale) at 2:3-6. Dr. Thornton also agrees that “at the time [of
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`the ’464 filing] most graphics controllers did use contiguous graphics memory.”
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`Ex. 1018 (Thornton Depo.) at 78:17-22.
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`A POSITA would have recognized this contiguous memory requirement as a
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`problem in unified memory architectures, such as those disclosed in Gulick and
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`Nale, where other devices sharing the memory compete for memory space. Ex.
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`1019 (Colwell Supp. Decl.) ¶ 14. Nale teaches a solution to this problem with
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`address translation to “dynamically allocate memory but still provide contiguous
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`memory to the decoder/DSP engine.” Ex. 1003 (Colwell Decl.) ¶ 70. A POSITA
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`would have therefore recognized Nale’s solution to be applicable to multiple
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`resources requiring contiguous memory in a unified memory architecture,
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`motivating the POSITA to turn to Nale when considering Gulick. Ex. 1019
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`(Colwell Supp. Decl.) ¶ 14.
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`Patent Owner therefore errs in arguing that a POSITA would not be
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`Petitioner’s Reply
`IPR2016-01121 (Patent No. 5,960,464)
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`motivated to combine Nale with Gulick due to an alleged incompatibility between
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`Nale’s address translator and Gulick’s MPEG decoder. Instead, the evidence
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`reflects that a POSITA would have been motivated to combine Nale’s teachings
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`with Gulick’s teachings in order to interface Gulick’s decoder teachings with a
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`shared memory. A POSITA would have also been motivated to combine Gulick’s
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`and Nale’s teachings because they are within the related art of the ’464 Patent.
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`IV. Gulick combined with Nale renders obvious claims 3-4, 7-