IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`Petition for Inter Partes Review
`
`Attorney Docket No.: 52959.21
`Customer No.:
`27683
`
`Real Party in Interest:
`Apple Inc.
`
`
`
`
`
`§
`§
`§
`§
`§
`§
`§
`§
`§
`
`In re patent of Owen et al.
`
`U.S. Patent No. 7,321,368
`
`Issued: Jan 22, 2008
`Title: Electronic System and Method
`For Display Using a Decoder and
`Arbiter To Selectively Allow Access
`to a Shared Memory
`
`
`
`
`
`
`
`
`
`Declaration of Robert Colwell, Ph.D.
`Under 37 C.F.R. § 1.68
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`Apple Exhibit 1003
`Page 1 of 105
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`Table of Contents
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`Introduction .......................................................................................................... 4 
`I. 
`II.  Qualifications and Professional Experience ........................................................ 5 
`III.  Level of Ordinary Skill in the Art ....................................................................... 9 
`IV. Relevant Legal Standards .................................................................................. 10 
`V.  The ’368 Patent .................................................................................................. 11 
`A.  Overview ..................................................................................................... 11 
`
`B.  History of the ’368 Patent ........................................................................... 18 
`
`VI. Claim Construction ............................................................................................ 19 
`VII.  Overview of References .............................................................................. 27 
`A.  Overview of Bowes (U.S. Patent No. 5,546,547) ...................................... 27 
`
`B.  Overview of DSP3210 Data Sheet ............................................................. 30 
`
`C.  Overview of Artieri (translation of EP 0626653) ....................................... 33 
`
`D.  Overview of Gove ...................................................................................... 36 
`
`E.  Overview of Christiansen (U.S. Patent No. 5,787,264) ............................. 37 
`
`F.  Overview of Tahara (U.S. 5,473,380) ........................................................ 39 
`
`VIII.  Challenge #1: Claims 1, 7, 13, 15, 18, 20, and 24-25 are invalid under
`35 U.S.C § 103 over Bowes as informed by the DSP3210 Data Sheet
`and in view of Artieri .................................................................................. 40 
`A.  Bowes’ DSP as a “decoder” [or “video decoder”] ..................................... 44 
`
`B.  Use of a shared “main memory” was known ............................................. 55 
`
`C.  An arbiter circuit (or “memory arbiter” or “arbiter”) ................................. 60 
`
`D.  Reasons to Combine Bowes, DSP3210 Data Sheet, and Artieri ................ 62 
`
`E.  Detailed Analysis: Claims 1, 7, 13, 15, 18, 20, and 24-25 ......................... 64 
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`IX. Claims 2, 3, 14 and 21 are invalid under 35 U.S.C § 103 over Bowes as
`informed by the DSP3210 Data Sheet and in view of Artieri and in
`further view of Tahara ................................................................................. 90 
`A.  Reasons to Combine Bowes, DSP3210 Data Sheet, Artieri, and Tahara .. 90 
`
`B.  Detailed Analysis of Claims 2, 3, 14 and 21 .............................................. 91 
`
`X.  Challenge #2: Claims 17 and 23 are invalid under 35 U.S.C § 103 over
`Bowes in view of DSP3210 Data Sheet, Artieri, and Gove ....................... 96 
`A.  Reasons to Combine Bowes, DSP3210 Data Sheet, Artieri, and Gove ..... 97 
`
`B.  Detailed Analysis of Claims 17 and 23 ...................................................... 98 
`
`XI. Claim 19 is invalid under 35 U.S.C § 103 over Bowes in view of DSP3210
`Data Sheet, Artieri, and Christiansen ........................................................101 
`A.  Reasons to Combine Bowes, DSP3210 Data Sheet, Artieri and
`Christiansen .............................................................................................. 101 
`
`B.  Detailed Analysis of Claim 19 ................................................................. 103 
`
`XII.  Declaration .................................................................................................105 
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`I.
`
`Introduction
`
`I, Robert Colwell, Ph.D., declare:
`
`1.
`
`I am making this declaration at the request of Apple Inc. in the matter
`
`of the Inter Partes Review of U.S. Patent No. 7,321,368 (“the ’368 Patent”) to
`
`Owen et al.
`
`2.
`
`I am being compensated for my work in this matter. I am also being
`
`reimbursed for reasonable and customary expenses associated with my work and
`
`testimony in this investigation. My compensation is not contingent on the outcome
`
`of this matter or the specifics of my testimony.
`
`3.
`
`In the preparation of this declaration, I have studied:
`
`(1) The ’368 Patent, Exhibit 1001;
`
`(2) The prosecution history of the ’368 Patent, Exhibit 1002;
`
`(3) U.S. Patent No. 5,546,547 to Bowes et al. (“Bowes”), Exhibit 1005;
`
`(4)
`
`“AT&T DSP3210 Digital Signal Processor The Multimedia Solution”
`
`Data Sheet March 1993 (“DSP3210 Data Sheet”), Exhibit 1006;
`
`(5) EP 0626653 to Artieri, English translation (“Artieri”), Exhibit 1007;
`
`(6) R. Gove, “The MVP: A Highly-Integrated Video Compression Chip”,
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`IEEE 1994 (“Gove”), Exhibit 1008;
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`(7) U.S. Patent No. 5,787,264 to Christiansen et al. (“Christiansen”),
`
`Exhibit 1011;
`
`(8) U.S. Patent No. 5,473,380 to Tahara (“Tahara”), Exhibit 1012; and
`
`(9)
`
`other documentation as cited in the analysis below.
`
`
`
`4.
`
`In forming the opinions expressed below, I have considered:
`
`(1) The documents listed above,
`
`(2) The relevant legal standards, including the standard for obviousness
`
`provided in KSR International Co. v. Teleflex, Inc., 550 U.S. 398 (2007), and
`
`(3) My own knowledge and experience, including my work experience in
`
`the fields of electrical engineering, computer engineering, computer
`
`architectures, memory interfacing, and multimedia technologies, and my
`
`experience in working with others involved in those fields, as described
`
`below.
`
`II. Qualifications and Professional Experience
`
`5. My complete qualifications and professional experience are described
`
`in my curriculum vitae, a copy of which can be found in Exhibit 1004. The
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`following is a brief summary of my relevant qualifications and professional
`
`experience.
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`6.
`
`I have nearly 40 years of professional experience in the field of
`
`processor and system architecture design. I consider myself an expert in, among
`
`other things, CPU architecture and computer systems.
`
`7.
`
`I received an undergraduate Bachelor of Science degree in Electrical
`
`Engineering from the University of Pittsburgh in 1977. I received a Master’s of
`
`Science degree in Computer Engineering from Carnegie Mellon University in 1978
`
`as well as a Ph.D. in Computer Engineering in 1985.
`
`8.
`
`From 1977 to 1980, I held an engineering position at Bell Telephone
`
`Laboratories where I worked on, among other things, microprocessor hardware
`
`design.
`
`9.
`
`From 1980 to 1984, I held an engineering position at Perq Systems,
`
`where I worked on hardware design in computer environments. From 1985 to
`
`1990, I held an engineering position at Multiflow Computer, where I served as a
`
`hardware architect. While at Multiflow Computer, I assisted in creating the first
`
`very long instruction word (VLIW) scientific supercomputer.
`
`10. From 1990 to 2001, I held various positions at Intel including Senior
`
`CPU Architect and later Chief Architect (for Intel’s IA-32, also known as x86). As
`
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`part of my responsibilities at Intel, I co-invented Intel’s P6 microarchitecture that
`
`formed the core of the Pentium II manufactured by Intel (as well as the Pentium
`
`III, Celeron, Xeon, and Centrino families). The P6 core is still very influential
`
`today, in Intel’s top-of-the-line Core i3, i5, and i7 processors. In addition, I led
`
`Intel’s x86 Pentium CPU architecture endeavors. I was honored to be named an
`
`Intel fellow in 1997 in recognition of my contributions to the P6 microarchitecture
`
`development.
`
`11.
`
`I became a self-employed industry consultant in 2001, working with
`
`computer industry clients such as Safeware, the University of Pittsburgh, Intel,
`
`many venture capital companies, and the U.S. Department of Defense (DoD).
`
`12. From 2011 to 2014, I worked at the Defense Advanced Research
`
`Projects Agency (DARPA) first as Deputy Director, then Director, of the
`
`Microsystems Technology Office (MTO). MTO had an annual budget of
`
`approximately $600M, and my job as office leader was to invest that money in
`
`promising new technologies for the DoD, including new energy-efficient
`
`computing systems, modular and adaptable radars, position/navigation/timing
`
`systems for GPS-denied environments, computer-mediated prosthetics for military
`
`(and civilian) amputees, traumatic brain injury detection devices for soldiers, fused
`
`multiple-band night vision sensors, extremely high power lasers, and much more.
`
`13.
`
`
`
`I have been recognized by the industry for my contributions to
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`processor design. I received the Eckert-Mauchly Award in 2005 for “outstanding
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`achievements
`
`in
`
`the design and
`
`implementation of
`
`industry-changing
`
`microarchitectures, and for significant contributions to the RISC/CISC architecture
`
`debate.” The Eckert-Mauchly Award is generally viewed as the highest possible
`
`recognition in the field of computer architecture.
`
`14.
`
`I was inducted into the National Academy of Engineering in 2006, the
`
`nation’s highest honorary society for engineering achievement. In 2012 I was
`
`inducted into the American Academy of Arts and Sciences; other inductees in my
`
`“class” that year included Sir Paul McCartney, Hillary Rodham Clinton, and Mel
`
`Brooks.
`
`15.
`
`In 2015 I received the Bob Rau Award from the Institute of Electrical
`
`and Electronics Engineers (IEEE), for “contributions to critical analysis of
`
`microarchitecture and the development of the Pentium Pro processor.”
`
`16.
`
`I have published many conference papers, sections of textbooks, and
`
`articles for magazines. I have also been named an inventor on 40 patents related to
`
`computer hardware and processor design. I have also been an editor for several
`
`IEEE publications.
`
`17. My curriculum vitae (Ex. 1004) includes a list of all publications I
`
`have authored in the last 10 years.
`
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`18.
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`In summary, I have extensive familiarity with multimedia systems,
`
`computer architectures, unified memory architectures, and methods related to
`
`controlling memory access, and am familiar with what the states of these
`
`technologies were at the relevant time of the ’368 Patent invention and before.
`
`III. Level of Ordinary Skill in the Art
`
`19.
`
`I am familiar with the knowledge and capabilities of persons of
`
`ordinary skill in the computer system architecture and multimedia processing arts
`
`in the period around 1996. In addition to my own experiences, I worked with and
`
`spent 11 years leading an industrial microprocessor design team at Intel, which by
`
`the mid-1990s included more than 450 engineers. The majority of those engineers I
`
`personally interviewed as part of the recruiting and hiring process. My experience
`
`working in the industry and interactions with colleagues and supervision of
`
`practicing engineers has allowed me to become directly and personally familiar
`
`with the level of skill of individuals and the general state of the art as of 1996.
`
`20.
`
`I have been informed by counsel that the earliest alleged priority date
`
`for the ’368 Patent is August 26, 1996. Unless otherwise stated, my testimony
`
`below refers to the knowledge of one of ordinary skill in the computer system
`
`architecture and multimedia processing arts in the period around and prior to
`
`August 26, 1996. In my opinion, the level of ordinary skill in the art appropriate to
`
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`understanding the scientific and engineering principles applicable to the ’368
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`Patent is (i) a Bachelor of Science degree (or higher degree) in an academic area
`
`emphasizing electrical or computer engineering and (ii) three years of relevant
`
`industry.
`
`IV. Relevant Legal Standards
`
`21.
`
`I have been asked to provide my opinions regarding whether claims 1-
`
`3, 7, 13-15, 17-21, and 23-25 of the ’368 Patent would have been obvious to a
`
`person having ordinary skill in the art at the time of the alleged invention, in light
`
`of the prior art. I have been informed by counsel that a claimed invention is
`
`unpatentable under 35 U.S.C. § 103 if the differences between the invention and
`
`the prior art are such that the subject matter as a whole would have been obvious at
`
`the time the invention was made to a person having ordinary skill in the art to
`
`which the subject matter pertains. I have also been informed by counsel that the
`
`obviousness analysis takes into account factual inquiries including the level of
`
`ordinary skill in the art, the scope and content of the prior art, and the differences
`
`between the prior art and the claimed subject matter.
`
`22.
`
`I have been informed by counsel that the Supreme Court has
`
`recognized several rationales for combining references or modifying a reference to
`
`show obviousness of claimed subject matter. Some of these rationales include the
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`following: (a) combining prior art elements according to known methods to yield
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`predictable results; (b) simple substitution of one known element for another to
`
`obtain predictable results; (c) use of a known technique to improve a similar device
`
`(method, or product) in the same way; (d) applying a known technique to a known
`
`device (method, or product) ready for improvement to yield predictable results; (e)
`
`choosing from a finite number of identified, predictable solutions, with a
`
`reasonable expectation of success; and (f) some teaching, suggestion, or motivation
`
`in the prior art that would have led one of ordinary skill to modify the prior art
`
`reference or to combine prior art reference teachings to arrive at the claimed
`
`invention.
`
`V. The ’368 Patent
`
`A. Overview
`
`23. The ’368 Patent generally describes an electronic system with a first
`
`device and a “video/audio compression/decompression device such as a
`
`decoder/encoder” to share a memory. (Ex. 1001, Abstract). “An arbiter selectively
`
`provides access for the first device and/or the decoder/encoder to the memory
`
`based on priority.” (Ex. 1001, Abstract).
`
`24.
`
`In order to fit digital media, such as movies, onto a “conventional
`
`recording medium, such as a Compact Disc (CD),” the ’368 Patent recognizes it
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`was already known to “compress video and audio sequences before they are
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`transmitted or stored.” (Ex. 1001, 1:50-58). For compression/decompression, “[t]he
`
`MPEG standards are currently well accepted standards
`
`for one way
`
`communication. H.261, and H.263 are currently well accepted standards for video
`
`telephony.” (Ex. 1001, 2:13-16). The ’368 Patent further states that electronic
`
`systems added decoders to systems (such as a computer) in order to “allow them to
`
`display compressed sequences.” (Ex. 1001, 2:17-24).
`
`25. The ’368 Patent continues and explains that a decoder for MPEG
`
`sequences “typically … requires a 2 Mbyte memory,” and that such memory was
`
`“dedicated to the MPEG decoder 10 and increases the price of adding a decoder 10
`
`to the electronic system.” (Ex. 1001, 2:54-56). The ’368 Patent views this
`
`dedicated memory as a problem that increased the cost of the decoder. (Ex. 1001,
`
`2:57-59). The ’368 Patent allegedly addresses this problem by having the “video
`
`and/or audio decompression and/or compression device share[] a memory interface
`
`and the memory with the first device.” (Ex. 1001, 5:13-14). Figure 2 of the ’368
`
`Patent illustrates an electronic system containing a device (“first device”) having a
`
`shared memory with a decoder:
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`’368 Patent (Ex. 1001), FIG. 2
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`
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`The ’368 Patent explains that its proposed solution results in cost reduction “due to
`
`the fact that the video and/or audio decompression and/or compression device does
`
`not need its own dedicated memory but can share a memory with another device
`
`and still operate in real time.” (Ex. 1001, 5:61-64).
`
`26. The ’368 Patent further explains that the system, such as the system of
`
`FIG. 2, includes an arbiter, where requests for access to the memory are granted
`
`based on a priority scheme, which “can be any priority scheme that ensures that the
`
`decoder/encoder 80 gets access to the memory 50 often enough and for enough of
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`a burst length to operate properly, yet not starve the other devices sharing the
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`memory.” (Ex. 1001, 13:54-58). I note that below, in claim 1, the arbiter performs
`
`the function of “controlling access to said main memory by the decoder and the
`
`microprocessor” and in claim 13 the function of “controlling the access to the
`
`system memory.” (See also claims 7 and 20, where the arbiter analogously
`
`performs the function by “controlling access to the bus.”) As set forth in the ’368
`
`Patent specification, I understand that the arbiter performs this function by
`
`allowing only one of the devices to access the main memory at a given time. (Ex.
`
`1001, 13:34-53). The ’368 Patent states that its system includes a “bus 70 [FIG. 2
`
`above], that have a bandwidth greater than the bandwidth required for the
`
`decoder/encoder 80 to operate in real time. … A fast bus 70 is any bus whose
`
`bandwidth is equal to or greater than the required bandwidth.” (Ex. 1001, 7:66-
`
`8:29). Exemplary buses that, according to the ’368 Patent, provide bandwidth to
`
`be considered “fast” include “a PCI bus,…VESA Local Bus (VLB), an
`
`Accelerated Graphics Port (AGP) bus, or any bus having the required bandwidth.”
`
`(Ex. 1001, 10:41-43, see also Ex. 1001, 5:38-45). PCI bus, VESA Local Bus
`
`(VLB), and Accelerated Graphics Port (AGP) bus were known, available bus
`
`architectures.
`
`27. As an initial matter, I note that the alleged solution presented in the
`
`’368 Patent—sharing a memory between multiple devices and arbitrating access
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`thereto between the devices—was well known to persons of ordinary skill in the art
`
`before the earliest alleged priority date of the ’368 Patent. For example, others had
`
`previously identified the problem of dedicated “substantial block of static random
`
`access memory … SRAMs are significantly more expensive than DRAM which
`
`greatly increases the cost of computer systems which incorporate SRAM.” (Ex.
`
`1005, 2:36-41). Further, others had identified the same solution to the problem,
`
`namely providing “a mechanism and method for arbitrating the memory bus
`
`bandwidth to efficiently allow the use of a digital signal processor and a CPU over
`
`a common memory bus sharing the system's dynamic random access memory
`
`subsystem without requiring an expensive block static random access memory.”
`
`(Ex. 1005, 2:57-63).
`
`28. Additionally, digital signal processors were known to provide
`
`compression and decompression (e.g., MPEG) processing before the ’368 Patent.
`
`(See, e.g., Ex. 1019, “TMS” (TMS teaches that the single-chip multiprocessor DSP
`
`(“TMS320C8x” p. iii) may be used to accelerate applications “such as video
`
`compression and decompression, image processing, and graphics manipulation.”
`
`(See also Ex. 1019, p. A-6; Ex. 1009, p. 216).
`
`29.
`
`In claim 1 of the ’368 Patent, which is exemplary, a “microprocessor
`
`system” and a “decoder” both require access to a main memory. (Ex. 1001, 15:57-
`
`16:9). Claim 1 of the ’368 Patent recites:
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`An electronic system comprising:
`
`a main memory having stored therein data corresponding to images to
`
`be decoded and also decoded data corresponding to images that have
`
`previously been decoded;
`
`a bus coupled to the memory;
`
`a decoder coupled to the bus for receiving compressed images and for
`
`outputting data for displaying the decoded images on a display device, the
`
`decoder receiving data from the main memory corresponding to at least one
`
`previously decoded image and to a current image to be decoded and
`
`outputting decoded data corresponding to a current image to be displayed,
`
`the current image being stored in the main memory;
`
`a microprocessor system coupled to the main memory, the
`
`microprocessor system storing non-image data in and retrieving data from
`
`the main memory; and
`
`an arbiter circuit coupled to both the microprocessor system and the
`
`decoder for controlling the access to said main memory by the decoder and
`
`the microprocessor.
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`
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`30. Based on my experience, the electronic system described in the ’368
`
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`Patent and claimed in claim 1, as well as those systems of claims 2-3, 7, 13-15, 17-
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`21, and 23-25, were already well known to persons of ordinary skill in the art
`
`before the earliest alleged priority date. For instance, others had already taught the
`
`usefulness of unified memory architectures with arbitration to access the shared
`
`memory. (See Bowes, Ex. 1005). One of ordinary skill in the art would recognize
`
`that arbitration must be present in any system that shares access to a resource (e.g.,
`
`memory) in order to prevent conflicts. Arbitration schemes that were based on
`
`priority were well known. (See, e.g., Ex. 1005, 3:29-33; Ex. 1011, 1:16-19)
`
`31. Prior to the earliest alleged priority date of the ’368 Patent, others had
`
`also taught the usefulness of video circuitry or a decoder interacting with a
`
`memory in order to receive encoded data and output decoded data. (Ex. 1007,
`
`Figure 2). In fact, the International Organization for Standardization document
`
`“ISO/IEC 11172-2:1993:Information technology – Coding of moving pictures and
`
`associated audio for digital storage media at up to about 1,5 Mbit/s-Part 2:Video,”
`
`1st ed., August 1, 1993 (“MPEG Standard”), was publically available as of August
`
`1993, years before the earliest alleged priority date of the ’368 Patent. (Ex. 1018.)
`
`The MPEG Standard was a well-accepted industry standard. (Ex. 1001, 2:13-14.)
`
`The compression disclosed in the MPEG Standard allows videos to be encoded to
`
`reduce the bandwidth or memory requirements during storage or transmission; the
`
`compressed images are subsequently decoded for display. (Ex. 1018, at 52 (Figure
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`D.1)). The MPEG Standard provides for a decoder interacting with a “Picture
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`store” or a memory. (Ex. 1018, p. viii).
`
`Ex. 1018, MPEG Standard, Figure 4
`
`
`
`32. Accordingly, as I show below, it is my opinion that the elements and
`
`functionality recited in claims 1-3, 7, 13-15, 17-21, and 23-25 of the ’368 Patent
`
`were already well known before the earliest claimed priority date of the ’368
`
`Patent.
`
`B. History of the ’368 Patent
`
`33. The ’368 Patent issued on January 22, 2008 from U.S. Patent
`
`Application No. 10/174,918 by Jefferson Eugene Owen, Raul Zegers Diaz, and
`
`Osvaldo Colavin. Again, I have been informed by counsel that the earliest alleged
`
`priority date for the ’368 Patent is August 26, 1996.
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`34.
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`I have reviewed the prosecution history of the ’368 Patent and it is my
`
`understanding that none of the references cited in this declaration were discussed
`
`by the United States Patent Office during prosecution that led to the ’368 Patent. I
`
`also understand that the Office stated that the prior art did not teach “an arbiter
`
`circuit coupled to both the microprocessor system and the decode[r] for controlling
`
`access to said main memory by the decoder and the microprocessor.” (Ex. 1002,
`
`pp. 204-205). I disagree that this was not known in the art as discussed with
`
`reference to Bowes below.
`
`VI. Claim Construction
`
`35.
`
`It is my understanding that in order to properly evaluate the ’368
`
`Patent, the terms of the claims must first be interpreted. It is my understanding that
`
`for the purposes of this inter partes review the claims are to be given their broadest
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`reasonable interpretation in light of the specification. It is my further understanding
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`that claim terms are given their ordinary and customary meaning as would be
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`understood by one of ordinary skill in the art, unless the inventor has set forth a
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`special meaning for a term.
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`36.
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`In addition to the broadest reasonable interpretation set forth herein, I
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`have been informed that the ’368 Patent appears set to expire in August 2016. In
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`such cases, I have been told that the Board may construe patent claims, once
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`–19–
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`expired, according to the standard applied in the district courts by applying the
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`principles set forth in Philips v. AWH Corp., 415 F.3d 1030, 1312 (Fed. Cir. 2005)
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`(en banc). I am told under Philips principles, the words of the claims are generally
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`given their ordinary and customary meaning as understood by a person of ordinary
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`skill in the art in question, at the time of the alleged invention. It is my opinion
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`that this change of standards would not affect any of the invalidity grounds
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`discussed herein should construction of the claims remain as provided herein.
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`37.
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`In order to construe the following claim terms, I have reviewed the
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`entirety of the ’368 Patent as well as its prosecution history.
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`38.
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`“decoder” and “video decoder”
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`39. This claim term is found in claims 1, 7, and 20 as well as in the
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`detailed description. In context, the recited decoder is directed to image processing
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`as the claims recite, for example with respect to claim 1, that the decoder is
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`coupled to a bus “for receiving compressed images and for outputting data for
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`displaying the decoded images ….” (Ex. 1001, 15:62-64). The term “video
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`decoder” is used in claim 13 of the ’368 Patent and, based on the context provided
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`by the claim language itself, a video decoder is for “receiving compressed video
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`images and for outputting video data for displaying the video decoded images.”
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`(Ex. 1001, 17:51-53).
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`
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`–20–
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`40. The ’368 Patent sets forth a special meaning for “decoder” as follows:
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`“[t]he resulting bitstream is decoded by a video and/or audio decompression
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`device (hereinafter decoder) before the video and/or audio sequence is displayed.”
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`(Ex. 1001, 2:5-8 (emphasis added)). The ’368 Patent continues in the detailed
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`description: “[a]ny conventional decoder including a decoder complying to the
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`MPEG-1, MPEG-2, H.261, or H.261 standards, or any combination of them, of any
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`conventional standard can be used as the decoder/encoder.” (Ex. 1001, 15:51-54).
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`A person of skill in the art would recognize that such a decoder would ordinarily
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`be implemented using a combination of hardware, such as a digital signal
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`processor (DSP) with or without specialized computational pipelines, and software.
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`41.
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`It is therefore my opinion based on my review of the ’368 Patent that
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`one of ordinary skill in the art would understand that “decoder” means video
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`and/or audio decompression device. The recited decoder is directed to image
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`processing as the claims recite, for example with respect to claim 1, that the
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`decoder is coupled to a bus “for receiving compressed images and for outputting
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`data for displaying the decoded images ….” (Ex. 1001, 15:62-64). Independent
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`claims 7, 13 and 20 recite similar video-centric hints at proper construction. Thus,
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`“decoder” in the context of claims 1, 2, 7, 13-14, 16-17, 20-21, and 23 and “video
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`decoder” in the context of claims 13 and 19 means video decompression device.
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`42.
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` “fast bus”
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`–21–
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`43. The ’368 Patent identifies several known bus architectures as
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`exemplary “fast bus[es]” – “a fast bus (such as a memory bus, a PCI– “Peripheral
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`Component Interconnect”–bus, a VLB – “VESA (Video Electronics Standards
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`Association) Local Bus”, or an AGP– “Advanced Graphics Port”– bus, or any bus
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`having a bandwidth sufficient to allow the system to operate in real time)[.]” (Ex.
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`1001, 5:38-45). More generally, the ’368 Patent describes a “fast bus” as “any bus
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`having a bandwidth sufficient to allow the system to operate in real time.” (Ex.
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`1001, 5:42-43). (Emphasis added). (See also, 8:27-28). For the purposes of my
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`analysis herein, “fast bus” is any bus having a bandwidth sufficient to allow the
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`system to operate in real time.
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`44.
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`“directly supplies”
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`45. Dependent claim 2 further recites that the decoder “directly supplies a
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`display adapter with an image under decoding which is not used to decode a
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`subsequent image.” (Ex. 1001, 16:10-13). Dependent claims 14 and 21 further
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`recite that the decoder (see construction above) “directly supplies a display device
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`with an image under decoding which is not used to decode a subsequent image.”
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`(Ex. 1001, 18:8-11, 39-42).
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`46.
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`I have been informed that, in another proceeding involving similar
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`
`
`–22–
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`language appearing in the claims of related Patent 7,542,045,1 the Board has
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`adopted a preliminary construction of the phrase “decoder directly supplies a
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`display device with an image” consistent with a view that an image is directly
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`supplied if it is supplied without being stored in main memory for purposes of
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`decoding subsequent images. (See HTC Corporation et al v. Parthenon Unified
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`Memory Architecture LLC, IPR2015-01502, Institution Decision, paper 14 (PTAB
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`January 6, 2016)). I have also been informed that the Patent Owner has asserted in
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`ongoing litigation, and the district court has subsequently adopted, a construction
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`of “directly supplies” as supplies without being stored in main memory for
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`purposes of decoding subsequent images. (Ex. 1016, Parthenon Unified Memory
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`Architecture LLC v. Samsung et al., Document No. 155, Markman Order, p. 33
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`(Jan 25, 2016)).
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`47. Notwithstanding the apparent direction of the prior constructions, I do
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`not find clear support in the ’368 Patent for a construction of “directly supplies”
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`that would allow images to be indirectly supplied to a display adapter and stored in
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`main memory so long as the purpose of such storage is other than for decoding of
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`subsequent images. Quite to the contrary, the specification supports the conclusion
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`that “directly supplies” means that an image is supplied from the decoder to a
`
`
`1 I have been informed that the ’368 Patent is a parent patent of U.S. Patent
`7,542,045.
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`
`
`–23–
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`display adaptor without being stored in the main memory.
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`48. The ’368 Patent states that this direct supply to the display adapter is
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`for bidirectional images, rather than intra or predicted images. (Ex. 1001, 10:52-
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`55). This is hardly surprising because, in accordance with the MPEG-2 standards,
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`bidirectional images (or B frames), unlike intra or predicted images (i.e., I or P
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`frames), are not used for decoding other images. (See Ex. 1018, p. v; Ex. 1007, p.
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`16). A person of ordinary skill in the art would recognize that the ’368 Patent
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`sought to reduce traffic over its memory bus by eliminating an additional step of
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`storing, and then retrieving, bidirectional images from shared main memory. The
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`’368 Patent confirms this point with the statement that the required transfer rate on
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`bus 170 “is substantially decreased due to the bidirectional images not being
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`stored in main memory 168, but being directly sent to display adapter 120.” (Ex.
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`1001, 11:5-8). (Emphasis added.)
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`49. FIG. 4 (below) shows, and the corresponding description of the ’368
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`Patent explains (see Ex. 1001, 10:36-11:23) an embodiment in which the
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`b