`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`———————
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`———————
`
`
`
`APPLE INC.,
`Petitioner,
`
`v.
`
`Parthenon Unified Memory Architecture LLC,
`Patent Owner
`
`———————
`
`
`
`PETITION FOR INTER PARTES REVIEW
`
`OF
`
`U.S. PATENT NO. 7,777,753
`
`
`
`
`
`
`
`
`
`

`

`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
`TABLE OF CONTENTS
`
`I.  MANDATORY NOTICES ............................................................................... 1 
`
`A.  Real Party-in-Interest ................................................................................ 1 
`
`B.  Related Matters ......................................................................................... 1 
`
`C.  Lead and Back-up Counsel and Service Information .............................. 2 
`
`II.  GROUNDS FOR STANDING .......................................................................... 2 
`
`III.  INTRODUCTION; RELIEF REQUESTED ..................................................... 3 
`
`IV.  REASONS FOR THE REQUESTED RELIEF ................................................ 4 
`
`A. 
`
`’753 Patent ................................................................................................ 4 
`
`1.  Overview .......................................................................................... 4 
`
`2. 
`
`Prosecution History .......................................................................... 7 
`
`B. 
`
`Identification of Challenges ..................................................................... 7 
`
`1.  Challenged Claims ........................................................................... 7 
`
`2. 
`
`Statutory Ground for Challenges ..................................................... 7 
`
`3.  Note Regarding Page Citations ...................................................... 10 
`
`4.  Redundancy .................................................................................... 10 
`
`C.  Claim Construction ................................................................................. 11 
`
`1. 
`
`2. 
`
`3. 
`
`“decoder” (Claims 7-9 and 12) ...................................................... 12 
`
`“video circuit” (Claims 1, 2 and 4) ................................................ 13 
`
`“memory interface circuit” (Claim 7) ............................................ 14 
`
`4.  Other Claim Terms ......................................................................... 15 
`
`D. 
`
`Identification of How the Claims Are Unpatentable .............................. 16 
`
`
`
`
`

`

`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
`1.  Challenge #1: Claims 1 and 2 are obvious over Bowes,
`Datasheet, Artieri, and Arimilli ...................................................... 16 
`
`i. 
`
`Reasons to Combine—Bowes, Datasheet, Artieri
`and Arimilli ............................................................................. 18 
`
`ii.  Summary of the Central Bowes and Artieri Combination ..... 21 
`
`iii.  Detailed Analysis .................................................................... 23 
`
`2.  Challenge #2: Claim 4 is obvious over Bowes in view of
`Datasheet, Artieri, Arimilli, and Shanley ....................................... 42 
`
`i. 
`
`Reasons to Further Combine Shanley ..................................... 43 
`
`ii.  Detailed Analysis .................................................................... 44 
`
`3.  Challenge #3: Claim 7 is obvious over Bowes, Datasheet,
`Artieri, and Christiansen ................................................................ 46 
`
`i. 
`
`Reasons to Further Combine Christiansen ............................. 47 
`
`ii.  Detailed Analysis .................................................................... 48 
`
`4.  Challenge #4: Claims 8 and 10 are obvious over Bowes,
`Datasheet, Artieri, Christiansen, and Arimilli ............................... 60 
`
`5.  Challenge #5: Claim 9 is obvious over Bowes, Datasheet,
`Artieri, Christiansen, and Shanley ................................................. 65 
`
`6.  Challenge #6: Claim 12 is obvious over Bowes, Datasheet,
`Artieri, Christiansen, and Gove ...................................................... 66 
`
`i. 
`
`Reasons to Further Combine Gove ......................................... 67 
`
`ii.  Detailed Analysis .................................................................... 67 
`
`V.  Conclusion ....................................................................................................... 69 
`
`
`
`
`
`

`

`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
`I. MANDATORY NOTICES
`A. Real Party-in-Interest
`The real party-in-interest is Apple Inc.
`
`B. Related Matters
`As of the filing date of this petition, the ’753 Patent has been asserted in:
`
` STMicroelectronics v. Motorola Inc., 4:03-CV-00276 (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. Apple
`
`Inc.,
`
`2-15-CV-00621 (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. Huawei Tech. Co., Ltd. et
`
`al., 2:14-CV-00687 (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. Motorola Mobility, Inc.,
`
`2:14-CV-00689 (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. HTC Corp. et al.,
`
`2:14-CV-00690 (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. LG Elec., Inc. et al.,
`
`2:14-CV-00691 (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. Samsung Elecs. Co. Ltd.
`
`et al., No. 2:14-CV-00902 (E.D. Tex.);
`
` Parthenon Unified Memory Architecture LLC v. Qualcomm Inc. et al., No.
`
`2:14-CV-00930 (E.D. Tex.);
`
`
`
`–1–
`
`

`

`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
` Parthenon Unified Memory Architecture LLC v. ZTE Corp. et al., No.
`
`2:15-CV-00225 (E.D. Tex.); and
`
` Parthenon Unified Memory Architecture LLC v. LG Electronics
`
`MobileComm, USA, 2-15-CV-01950 (E.D. Tex.).
`
`Additionally, the ’753 Patent has been challenged in the following inter partes
`
`review proceedings:
`
` IPR2015-01501 and IPR2016-00670.
`
`Apple Inc. is not a real party-in-interest in either of these proceedings.
`
`C. Lead and Back-up Counsel and Service Information
`Lead Counsel
`
`Phone: (512) 867-8457
`David W O’Brien
`Fax: (214) 200-0853
`HAYNES AND BOONE, LLP
`david.obrien.ipr@haynesboone.com
`2323 Victory Ave. Suite 700
`USPTO Reg. No. 40,107
`Dallas, TX 75219
`
`Backup Counsel
`Andrew S. Ehmke
`HAYNES AND BOONE, LLP
`2323 Victory Ave. Suite 700
`Dallas, TX 75219
`
`
`Phone: (214) 651-5116
`Fax: (214) 200-0853
`andy.ehmke.ipr@haynesboone.com
`USPTO Reg. No. 50,271
`
`Please address all correspondence to lead and back-up counsel. Petitioner consents
`
`to electronic service by email to the addresses listed above.
`
`II. GROUNDS FOR STANDING
`Petitioner certifies that the ’753 Patent is eligible for inter partes review and
`
`that Petitioner is not barred or estopped from requesting inter partes review
`
`
`
`–2–
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
`
`challenging the patent claims on the grounds identified in this Petition. Petitioner
`
`was served with a complaint asserting infringement of the ’753 Patent on June 5,
`
`2015. Petitioner has not filed a civil action challenging the validity of any claim of
`
`the ’753 Patent.
`
`III.
`
`INTRODUCTION; RELIEF REQUESTED
`
`U.S. Patent No. 7,777,753 (“the ’753 Patent,” APL1001) is generally directed
`
`to a system having a memory shared between a video decoder and another device,
`
`such as a central processing unit (CPU), and describes arbitrating between the
`
`devices for access to the shared memory. See APL1001, Abstract, 4:64-5:15. The
`
`’753 Patent alleges that conventionally, a video decoder would have its own
`
`dedicated memory. APL1001, 2:47-51, 3:14-19, 4:43-45. The ’753 Patent proposes
`
`that dedicated memory increases costs and would be “unused most of the time.”
`
`APL1001, 4:50-52. According to the ’753 Patent, an advantage of its invention was
`
`cost reduction due to the fact that the video decoder did not need its own dedicated
`
`memory but could share memory with the other device and still operate in real time.
`
`See APL1001, 5:47-51.
`
`However, before the priority date of the ’753 Patent, others had recognized
`
`the cost concerns, had proposed to use a shared memory in lieu of a dedicated
`
`memory in similar systems, and had developed arbitration schemes for sharing this
`
`memory while supporting real time operation. See e.g., APL1003, ¶¶23-32. For
`
`
`
`–3–
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
`
`example, Bowes (APL1005) recognized the benefits of allowing its digital signal
`
`processor (DSP) to use shared main memory by arbitrating access to the shared
`
`memory among the DSP and other devices, including a CPU. APL1005, 2:57-63.
`
`The evidence in this Petition demonstrates that claims 1, 2, 4, 7-10 and 12 of
`
`the ’753 Patent are unpatentable under pre-AIA 35 U.S.C. §103. Accordingly, Apple
`
`Inc. (“Petitioner”) respectfully requests the Patent Trial and Appeal Board (“Board”)
`
`institute trial for inter partes review of claims 1, 2, 4, 7-10 and 12 of the ’753 Patent,
`
`and cancel each such claim as invalid.
`
`IV. REASONS FOR THE REQUESTED RELIEF
`As explained below and in the declaration of Petitioner’s expert, Robert
`
`Colwell, Ph.D., the concepts claimed in the ’753 Patent were neither new nor
`
`nonobvious. This Petition explains where each element of claims 1, 2, 4, 7-10 and 12
`
`is found in the prior art and why the claims would have been obvious to a person of
`
`ordinary skill in the art (“POSITA”) before the earliest claimed priority date of the
`
`’753 Patent. A full statement of the reasons for the relief requested follows.
`
`A.
`
`’753 Patent
`1. Overview
`The ’753 Patent generally describes an electronic system with a first device
`
`and a “video and/or audio decompression and/or compression device” that share a
`
`memory in a manner that permits the decompression/compression device to operate
`
`
`
`–4–
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
`
`in real time. APL1001, Abstract, 4:64-66. “An arbiter selectively provides access for
`
`the first device and/or the decoder/encoder to the memory based on priority.”
`
`APL1001, Abstract. To fit digital media, such as movies, onto a “conventional
`
`recording medium, such as a CD,” it was already known to “compress video and
`
`audio sequences before they are transmitted or stored.” APL1001, 1:50-51
`
`(recognizing same). For compression/decompression, “MPEG standards are
`
`currently well accepted standards for one way communication. H.261 and H.263 are
`
`currently well accepted standards for video telephony.” APL1001, 2:6-7. The ’753
`
`Patent indicates that electronic systems added decoders to computer systems to
`
`“allow them to display compressed sequences.” APL1001, 2:14-17.
`
`The ’753 Patent indicates that a decoder for MPEG sequences “typically…
`
`requires a 2 Mbyte memory,” and that such memory was typically “dedicated to the
`
`MPEG decoder 10 and increases the price of adding a decoder 10 to the electronic
`
`system.” APL1001, 2:44-51. The ’753 Patent views this dedicated memory as a
`
`problem that increased cost of the decoder. APL1001, 2:49-51. The ’753 Patent
`
`allegedly addressed this problem by having the “video and/or audio decompression
`
`and/or compression device share[] a memory interface and the memory with the first
`
`device.” APL1001, 5:2-3. Figure 2 of the ’753 Patent illustrates an electronic system
`
`containing a device (“first device”) having a shared memory with a decoder:
`
`
`
`–5–
`
`

`

`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
`’753 Patent, FIG. 2
`
`
`
`The ’753 Patent explains that its proposed solution results in cost reduction “due to
`
`the fact that the video and/or audio decompression and/or compression device does
`
`not need its own dedicated memory but can share memory with another device and
`
`still operate in real time.” APL1001, 5:48-51.
`
`The ’753 Patent further explains that the system of FIG. 2 includes an arbiter,
`
`whereby requests to obtain access to the memory are granted based on a priority
`
`scheme, which “can be any priority scheme that ensures that the decoder/encoder 80
`
`gets access to the memory 50 often enough and for enough of a burst length to
`
`operate properly, yet not starve the other devices sharing the memory.” APL1001,
`
`13:30-35.
`
`
`
`
`
`–6–
`
`

`

`
`
`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
`As discussed below in more detail, the system presented in the ’753
`
`Patent—sharing a memory between multiple devices and arbitrating access thereto
`
`between the devices—was well known in the art well before the ’753 Patent’s
`
`earliest alleged priority date.
`
`Prosecution History
`
`2.
`The ’753 Patent issued on August 17, 2010 from U.S. Patent Application No.
`
`12/424,389, which was filed on April 15, 2009. The ’753 Patent claims priority
`
`through a chain of applications to an earliest alleged priority date of August 26,
`
`1996. The only rejection of the claims during prosecution of Application No. 12/
`
`424,389 was a double patenting rejection. APL1002, 78-83. Upon acceptance of a
`
`terminal disclaimer, the Examiner allowed the claims, restating the “arbiter circuit”
`
`language of the independent claim in the reasons for allowance. APL1002, 148. As
`
`illustrated herein, arbiter circuits that perform the functions recited in the
`
`above-listed claims of the ’753 Patent were known in the art as evidenced by Bowes
`
`and Arimilli, neither of which were considered during the prosecution of the ’753
`
`Patent.
`
`B.
`
`Identification of Challenges
`1.
`Claims 1, 2, 4, 7-10, and 12 of the ’753 Patent are challenged.
`
`Challenged Claims
`
`2.
`Statutory Ground for Challenges
`Challenge #1: Claims 1 and 2 are obvious under 35 U.S.C. §103 over US
`
`
`
`–7–
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
`
`Patent No. 5,546,547 to Bowes et al. (“Bowes”) in view of “AT&T DSP3210 Digital
`
`Signal Processor The Multimedia Solution[,]” Data Sheet March 1993
`
`(“Datasheet”), European Patent Application Publication EP 0626653 A1 naming
`
`Artieri (“Artieri”) and U.S. Patent No. 6,029,217 to Arimilli et al. (“Arimilli”).
`
`Bowes was filed January 28, 1994, issued August 13, 1996, and for purposes
`
`of this Petition is prior art to the ’753 Patent at least under (pre-AIA) 35 U.S.C.
`
`§§102(a) and (e). Datasheet bears a date of March 1993 and a 1993 copyright notice
`
`(see APL1006, 1, 40) and was publicly available at least as of January 17, 1994
`
`when the document included as APL1006 was cited in a third party prior art
`
`submission to the USPTO. APL1014, 148. Datasheet is thus, for purposes of this
`
`Petition, prior art to the ’753 Patent at least under (pre-AIA) 35 U.S.C. §102(b).
`
`Artieri was published November 20, 1994 in the French language and thus, for the
`
`purposes of this Petition, is prior art to the ’753 Patent at least under (pre-AIA) 35
`
`U.S.C. §102(b). In compliance with 37 C.F.R. §42.63(b), a copy of the
`
`French-language document, an English translation, and an affidavit attesting to the
`
`accuracy of the translation are provided as Exhibit 1007. Arimilli was filed October
`
`3, 1994 and issued February 22, 2000, and for purposes of this Petition is prior art to
`
`the ’753 Patent at least under (pre-AIA) 35 U.S.C. §102(e).
`
`Challenge #2: Claim 4 is invalid under 35 U.S.C §103 over Bowes in view of
`
`Datasheet, Artieri, Arimilli and further in view of T. Shanley et al., “PCI System
`
`
`
`–8–
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
`
`Architecture”, Addison–Wesley Publ’g Co. (3rd ed. Feb. 1995) (“Shanley”).
`
`Shanley was published March 13, 1995, as indicated by the Date of Publication in
`
`its copyright registration. APL1021. For purposes of this Petition, Shanley is prior
`
`art to the ’753 Patent at least under (pre-AIA) 35 U.S.C. §102(b).
`
`Challenge #3: Claim 7 is invalid under 35 U.S.C §103 over Bowes in view of
`
`Datasheet, Artieri, and U.S. Patent No. 5,787,264 to Christiansen et al.
`
`(“Christiansen”). Christiansen was filed on May 8, 1995, granted on July 28, 1998,
`
`and for the purposes of this Petition is prior art to the ’753 Patent at least under
`
`(pre-AIA) 35 U.S.C. §102(e).
`
`Challenge #4: Claims 8 and 10 are invalid under 35 U.S.C §103 over Bowes
`
`in view of Datasheet, Artieri, Christiansen, and in further view of Arimilli.
`
`Challenge #5: Claim 9 is invalid under 35 U.S.C §103 over Bowes in view of
`
`Datasheet, Artieri, Christiansen, and in further view of Shanley.
`
`Challenge #6: Claim 12 is invalid under 35 U.S.C §103 over Bowes in view
`
`of Datasheet, Artieri, Christiansen and further in view of R.J. Gove, “The MVP: A
`
`Highly-Integrated Video Compression Chip,” Proceedings of the IEEE Data
`
`Compression Conference (DCC ’94), 215-224 (“Gove”). Gove was included as part
`
`of proceedings of the Data Compression Conference held March 29-31, 1994, and as
`
`such was publicly available at least as of March 29, 1994 as indicated by the Date of
`
`Publication in its copyright registration. APL1009; APL1021. Gove is thus, for
`
`
`
`–9–
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
`
`purposes of this Petition, prior art to the ’753 Patent at least under (pre-AIA) 35
`
`U.S.C. §102(b).
`
`Note Regarding Page Citations
`
`3.
`For exhibits that include suitable page, column, or paragraph numbers in their
`
`original publication, citations are to those original page, column, or paragraph
`
`numbers and not to the page numbers added for compliance with 37 CFR
`
`42.63(d)(2)(ii).
`
`4.
`Redundancy
`The ’753 Patent is currently the subject of additional inter partes review
`
`proceedings, IPR2015-01501 (instituted) and IPR2016-00670 (pre-institution
`
`stage). Apple is not a real party-in-interest in either IPR2015-01501 or
`
`IPR2016-00670 and has no control over the filings.
`
`Moreover, Apple’s interests are different than those of the IPR2015-01501
`
`and IPR2016-00670 petitioners. See Sony Mobile Comm. (USA) Inc., v. E-Watch,
`
`Inc., IPR2015-00401, Paper 13 at 9 (PTAB 2015) (dismissing Patent Owner’s
`
`§325(d) arguments citing the “need to be cognizant of the interests of other
`
`petitioners”).
`
`More importantly, the challenges presented in the instant petition rely on
`
`different prior art combinations, different arguments regarding the asserted prior
`
`art, and different expert declaration testimony than those relied upon in
`
`
`
`–10–
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
`
`IPR2015-01501 and IPR2016-00670. See, e.g., Nestle USA, Inc., v. Steuben Foods,
`
`Inc., IPR2014-01235, Paper 12 at 7 (PTAB 2014) (declining to deny petition under
`
`§325(d) where petition relied on “combination of references previously not
`
`considered and [was] supported by a declaration previously not considered”); see
`
`also Tandus Flooring, Inc. v. Interface, Inc., IPR2013-00333, Paper 16 at 6 (PTAB
`
`2013) (declining to deny petition under §325(d) where petitioner presented new
`
`declaration evidence). Accordingly, because the instant petition presents different
`
`prior art and arguments, it falls outside of the scope of §325(d).
`
`C. Claim Construction
`In inter partes review, the Board applies the broadest reasonable construction
`
`in light of the specification to claims of an unexpired patent. See 37 C.F.R.
`
`§42.100(b). Under the broadest reasonable construction, claim terms are given their
`
`ordinary and accustomed meaning as would be understood by one of ordinary skill
`
`in the art in the context of the entire disclosure. In re Translogic Tech., Inc., 504 F.3d
`
`1249, 1257 (Fed. Cir. 2007). However, patent claims, if expiring prior to a final
`
`decision by the Board, are typically construed by the standard applied in the district
`
`courts by applying the principles set forth in Phillips v. AWH Corp., 415 F.3d 1303
`
`(Fed. Cir. 2005). See, e.g., 37 C.F.R. §42.108(c). Under this standard, the claim
`
`terms are given their ordinary and accustomed meanings as understood by one
`
`having ordinary skill in the art at the time of the invention in the context of the entire
`
`
`
`–11–
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
`
`patent, considering intrinsic evidence (the claims, the specification, and the
`
`prosecution history), and extrinsic evidence (technical dictionaries, treatises, etc.) to
`
`a lesser extent.
`
`Petitioner believes that the ’753 Patent will expire during pendency of the
`
`requested inter partes review proceeding. Accordingly, the constructions proposed
`
`herein are consistent with both standards.
`
` “decoder” (Claims 7-9 and 12)
`
`1.
`This claim term, “decoder,” is found in claims 7-9 and 12. The ’753 Patent
`
`sets forth a special meaning for “decoder” as follows: “[t]he resulting bitstream is
`
`decoded by a video and/or audio decompression device (hereinafter decoder)
`
`before the video and/or audio sequence is displayed.” APL1001, 1:65-2:1 (emphasis
`
`added). The detailed description continues: “[a]ny conventional decoder including a
`
`decoder complying to the MPEG-1, MPEG-2, H.261, or H.261 standards, or any
`
`combination of them, of any conventional standard can be used as the
`
`decoder/encoder.” APL1001, 15:27-30. In context provided by claim 7 itself, the
`
`recited decoder is necessarily a video decoder in that the claim recites that the
`
`decoder is coupled to a bus “for receiving encoded video images and for outputting
`
`data for displaying decoded video images….” APL1001, 16:17-19. Claim 12
`
`recites similar video-centric hints at proper construction.
`
`Based on the foregoing, and as confirmed by Dr. Colwell, for purposes of
`
`
`
`–12–
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
`
`invalidity analysis in this Petition, “decoder” means video decompression device.
`
`APL1003, ¶¶38-42.
`
`“video circuit” (Claims 1, 2 and 4)
`
`2.
`The term “video circuit” appears in claims 1, 2 and 4 of the ’753 Patent and, in
`
`accordance with the express language of claim 1, a video circuit is “configured to
`
`receive…a current video image to be decoded and to output decoded video data
`
`corresponding to the current video image to be displayed….” APL1001, 15:36-40.
`
`As a result, the term is closely related to the “decoder” term construed above.
`
`Dr. Colwell notes that there is no clear description of video circuitry per se in
`
`the specification of the ’753 Patent. APL1003, ¶45. However, the ’753 Patent does
`
`identify a “video decoding circuit 12” block that is part of a more general “decoder.”
`
`APL1003, ¶45; see also APL1001, 6:47; FIGs. 1a, 1b and 2. Therefore, viewing
`
`“video circuit” as a component or aspect of a decoder implementation, Dr. Colwell
`
`notes that the closest approximation of a video circuit actually described in the
`
`patent would be in connection with the block diagram of FIG. 6 that the ’753 Patent
`
`identifies as an “electrical diagram, in block form” of “an MPEG decoder.”
`
`APL1001, 6:17-19, FIG. 6; APL1003, ¶45. Dr. Colwell explains the block-level
`
`hardware of FIG. 6 includes a computational pipeline through first-in, first-out
`
`(FIFO) memories, a variable length decoder (VLD), a run-length decoder (RLD), an
`
`inverse quantization circuit Q-1, an inverse discrete cosine transform circuit DCT-1,
`
`
`
`–13–
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
`
`
`adder, and a filter of a conventional decoder. APL1003, ¶46.
`
`Based on the somewhat limited block-level hardware description of the ’753
`
`Patent and the video image decoding context provided by claim 1 itself, Dr. Colwell
`
`concludes that a POSITA would understand the term “video circuit” to encompass
`
`hardware aspects of the previously construed “decoder” or video decoder, such as
`
`for example, an MPEG decoder pipeline of FIG. 6. Simply stated, Dr. Colwell
`
`concludes that a POSITA would understand “video circuit” to mean hardware of a
`
`video decoder. APL1003, ¶¶43-47.
`
` “memory interface circuit” (Claim 7)
`
`3.
`The term “memory interface circuit” appears multiple times in claim 7 of the
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`’753 Patent relative to devices coupled to a memory bus. More specifically, both the
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`recited decoder and the recited central processing unit (CPU) have a “memory
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`interface circuit.” While the full composite term, “memory interface circuit,” does
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`not actually appear in the ’753 Patent specification, the lesser included terms
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`“memory interface” and “interface circuit” are used throughout, including in the
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`discussions of conventional devices. In each instance of a device having a “memory
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`interface” or “interface circuit,” the ’753 Patent illustrates a connection of the device
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`having the memory interface to a memory bus for accessing memory. See, e.g.,
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`APL1001, FIG. 1a, 1b, 2, 3, 7, 9:48-54, 12:15-21; APL1003, ¶50.
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`Although the ’753 Patent does not expressly describe elements of a “memory
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`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
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`interface circuit,” as compared with a “memory interface,” Dr. Colwell notes that in
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`the portions of the ’753 Patent that refer to an “interface circuit,” the interface circuit
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`enables memory to be shared between devices that require access to the memory
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`over a bus (see APL1001, 2:64-67) or otherwise coordinate addressing of and
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`exchanges of data with bus-coupled memory (see APL1001, 11:59-67). APL1003,
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`¶51. Operation of each of the memory interfaces illustrated in the ’753 Patent (e.g.,
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`memory interfaces 72 and 76, see FIGs. 2, 3, 7) involves requests or grants received
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`or provided via a signaling path to or from an arbiter. APL1001, 7:26-28, 38-39,
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`9:63-66, 12:25-28; APL1003, ¶51. Accordingly, Dr. Colwell confirms that a
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`POSITA would understand the term “memory interface circuit” (as it is used in the
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`’753 Patent) to include request/grant lines or signaling paths (e.g., to/from other bus
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`requesters or an arbiter) to coordinate interaction of multiple devices contending for
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`bus access to memory. APL1003, ¶¶48-53.
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`Accordingly, the “memory interface circuit” of a device should be construed
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`as hardware, including signaling paths to or from a competing device or an arbiter,
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`to coordinate communication via a memory bus. APL1003, ¶¶48-53.
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`4. Other Claim Terms
`For completeness of the record relative to 37 CFR 42.104(b)(2), Petitioner
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`notes the Joint Claim Construction and Prehearing Statement (APL1018), which
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`identifies several terms to which construction has been agreed between parties.
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`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
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`Unless otherwise noted, these agreed constructions are applied in the present
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`invalidity analysis and include “bus,” “display device,” “arbiter,” and “arbiter
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`circuit.” APL1018, 1-2; APL1003, ¶¶63-64. With regard to the terms “arbiter” and
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`“arbiter circuit,” Petitioner notes2 the import of the agreed constructions in the
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`invalidity analysis that follows.
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`D.
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`Identification of How the Claims Are Unpatentable
`1.
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`Challenge #1: Claims 1 and 2 are obvious over Bowes,
`Datasheet, Artieri, and Arimilli
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`
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`Bowes describes an arbitration scheme for a computer system in which a
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`digital signal processor (DSP) resides on a memory bus without requiring memory
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`dedicated to the DSP. APL1005, Abstract; APL1003, ¶¶65-72. Bowes describes
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`multiple “bus masters” coupled to the common memory bus. APL1005, 2:52-3:2,
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`4:15-17. Bowes’ examples of “bus masters” include “the CPU, the DSP, the I/O
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`interface and the NuBus controller,” each of which operates on data stored in main
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`memory subsystem 14. APL1005, 6:21-25, 7:66-67; APL1003, ¶¶65-72. To
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`accommodate various potential bus masters, Bowes provides a memory controller
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`and arbiter (MCA) 200 that arbitrates access according to a priority scheme.
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`APL1005, 7:64-8:10. Bowes indicates that its DSP, which can be programmed for
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`2 See infra notes 4 and 6.
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`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
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`image processing, resides on the system’s memory bus and operates from main
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`memory. APL1005, 6:33-35; APL1003, ¶¶67-71.
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`Bowes’ system includes a DSP designed for multimedia applications.
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`APL1006, 4, col. 1; APL1003, ¶¶72-77. Bowes indicates that, in one embodiment,
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`the DSP may be an AT&T DSP3210 digital signal processor (“DSP3210”).
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`APL1005, 6:28-30. Datasheet shows a “typical system” for a DSP3210 that
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`resembles Bowes’ system in that the DSP3210 is coupled to a system bus and
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`accesses system memory. APL1006, 4, Figure 2; APL1003, ¶75. Datasheet
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`confirms that a “primary benefit of this system architecture is the DSP’s ability to
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`access program and data from system memory without host intervention.
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`Furthermore, expensive local SRAM is replaced by the computer’s existing system
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`memory.” APL1006, 4, col. 1. Notably, the DSP3210 in Bowes’ system is
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`programmed to perform “image processing.” APL1005, 6:34.
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`Artieri discloses processing circuitry “for decoding an image encoded
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`according to an MPEG standard” for use in a “[s]ystem for processing images.”
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`APL1007, 1-2. Like Bowes, Artieri’s processing circuitry is configured as digital
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`signal processing circuitry coupled to memory via a bus. APL1007, Figure 3;
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`APL1003, ¶¶78-81. Unlike Bowes’ DSP, however, Artieri’s processing circuitry
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`provides a specially-adapted pipeline for performing operations typical of video
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`image decoding, and in particular, MPEG video decoding. APL1007, 11; APL1003,
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`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
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`¶¶78-81. Artieri illustrates its decoder circuitry transferring data to and from a
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`bus-coupled memory (15) and suggests that DRAM would be advantageous based
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`on size, costs and capacity. APL1007, FIG. 3, 12-14, 20, 36; APL1003, ¶80.
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`Memory 15 of Artieri includes an area “CD” to store compressed data (CD) images
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`prior to being processed and picture areas (IM1, IM2, and IM3) to store currently
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`reconstructed images and previously decoded images. APL1007, 14; APL1003,
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`¶80.
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`Arimilli is directed to a data processing system, multiprocessor system 100,
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`which includes a plurality of processing units and system memory on a shared
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`system bus 108. APL1008, Figure 1, Abstract. Arimilli’s arbiter, system controller
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`130, controls requests for, and grants of, system bus access. APL1008, Arimilli,
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`3:62-63. When a peripheral device sends a bus request to the system controller, it is
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`“queued” by receiving the request using an input latch of the system controller.
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`APL1008, 4:16-34; APL1003, ¶82.
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`i.
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`Reasons to Combine—Bowes, Datasheet, Artieri
`and Arimilli
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`In considering the system of Bowes, a POSITA would have looked to
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`Datasheet based on Bowes’ specific reference to, and suggestion of, the DSP3210.
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`APL1003, ¶¶123-124. Bowes also discusses using its system for real-time
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`processing tasks including “speech processing, audio channel control, modem
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`emulation, image processing and the like” and further suggests video and video
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`Petition for Inter Partes Review of U.S. Patent No. 7,777,753
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`conferencing applications. APL1005, 6:32-34, 1:34-41. On this suggestion of
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`Bowes, a POSITA would have been motivated to implement video processing in
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`Bowes’ system. APL1003, ¶¶94-96, 123-127.
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`To meet goals of video image processing at frame rates desirable for human
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`viewing and for large, high-quality images, a POSITA would have looked to extend
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`the capabilities of the DSP3210-type digital signal processor described in Bowes to
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`include circuitry capable of processing (including decoding) video images.
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`APL1003, ¶¶92107, 123-127. To achieve these goals, a POSITA would have looked
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`to implement video decompression methods such as MPEG to facilitate storage and
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`transfer of video in compressed form and thereby accommodate data transfer
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`bandwidth limitations of a bus. APL1003, ¶¶31, 96, 126. Indeed, design challenges
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`of providing sufficient bandwidth on the memory bus to perform real-time
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`isochronous signal processing were recognized by Bowes. APL1005, 4:62-67;
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`APL1003, ¶96.
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`Bowes recognizes that its DSP “require[s] a large amount of bandwidth to
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`memory” for real-time processing. APL1005, 1:51-53. Therefore, a POSITA would
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`have considered video storage and processing methods that employ compression,
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`and MPEG was a recognized standard for processing video while addressing storage
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`compactness and bandwidth demands. APL1003, ¶¶96, 126.
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`Petition for Inter Partes Review of