Trials@uspto.gov
`571-272-7822
`
`
`Paper 12
`Entered: January 6, 2016
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`HTC CORPORATION,
`HTC AMERICA, INC.,
`LG ELECTRONICS, INC.,
`SAMSUNG ELECTRONICS CO., LTD., and
`SAMSUNG ELECTRONICS AMERICA, INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2015-01501
`Patent 7,777,753 B2
`____________
`
`
`
`Before JAMES B. ARPIN, MATTHEW R. CLEMENTS, and
`SUSAN L. C. MITCHELL, Administrative Patent Judges.
`
`ARPIN, Administrative Patent Judge.
`
`
`DECISION
`Granting Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
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`I.
`INTRODUCTION
`HTC Corporation; HTC America, Inc.; LG Electronics, Inc.; Samsung
`Electronics Co., Ltd.; and Samsung Electronics America, Inc. (collectively,
`“Petitioner”) filed a Petition requesting inter partes review of claims 1–4, 7–
`10, and 12 (“the challenged claims”) of Patent No. US 7,777,753 B2
`(Ex. 1001, “the ’753 patent”). Paper 1 (“Pet.”). Parthenon Unified Memory
`Architecture LLC (“Patent Owner”) filed a Preliminary Response. Paper 7
`(“Prelim. Resp.”). We review the Petition pursuant to 35 U.S.C. § 314,
`which provides that an inter partes review may be authorized only if “the
`information presented in the petition . . . and any [preliminary] response . . .
`shows that there is a reasonable likelihood that the petitioner would prevail
`with respect to at least 1 of the claims challenged in the petition.” 35 U.S.C.
`§ 314(a); 37 C.F.R. § 42.4(a). Upon consideration of the Petition and the
`Preliminary Response, and the accompanying evidence, we determine that
`the information presented by Petitioner establishes that there is a reasonable
`likelihood that Petitioner would prevail in showing the unpatentability of at
`least one of the challenged claims of the ’753 patent. Accordingly, pursuant
`to 35 U.S.C. § 314, we institute an inter partes review of claims 1–4 of the
`’753 patent.
`
`A. Related Proceedings
`
`The ’753 patent is involved in several cases pending in the Eastern
`District of Texas. Pet. 2–3; Paper 5, 2–3. Petitioner also has filed other
`petitions seeking inter partes review of related patents. Pet. 3.
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`B. The ’753 patent
`The ’753 patent relates generally “to the field of electronic systems
`having a video and/or audio decompression and/or compression device, and
`is more specifically directed to sharing a memory interface between a video
`and/or audio decompression and/or compression device and another device
`contained in the electronic system.” Ex. 1001, col. 1, ll. 36–41. As of the
`effective filing date of the ’753 patent,1 a typical decoder included a
`dedicated memory, which represented a significant percentage of the cost of
`the decoder and which went unused most of the time. Id. at col. 2, ll. 21–63,
`col. 4, ll. 43–60, Figs. 1a–1c.
`To address these and other concerns, the ’753 patent discloses an
`electronic system in which a first device and a video and/or audio
`decompression and/or compression device are coupled to a shared memory
`through a bus that may have bandwidth sufficient for the video and/or audio
`decompression and/or compression device to operate in real time. Id. at col.
`4, l. 64–col. 5, l. 7. Figure 2 is reproduced below.
`
`
`1 The ’753 patent claims the benefit of a string of earlier-filed U.S. patent
`applications, the earliest of which was filed on August 26, 1996. Petitioner
`does not challenge the entitlement of the ’753 patent to this earliest filing
`date and argues that the ’753 patent will expire in August of 2016,
`presumably based on this earliest filing date. Pet. 10–11. Patent Owner
`implicitly claims the entitlement of the ’753 patent to the benefit of this
`earliest filing date and expressly states that the ’753 patent will expire on
`August 26, 2016. Paper 8, 1.
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`Figure 2 is a block diagram of an electronic system that contains a device
`with a memory interface and an encoder and decoder. Id. at col. 6, ll. 3–5.
`“First device 42 can be a processor, a core logic chipset, a graphics
`accelerator, or any other device that requires access to the memory 50.” Id.
`at col. 6, ll. 29–32. Both first device 42 and decoder/encoder 80 have access
`to memory 50 through memory interfaces 72 and 76, respectively, coupled
`to fast bus 70. Id. at col. 6, ll. 27–29, col. 7, ll. 26–28, 48–51. Fast bus 70
`may have at least the bandwidth required for decoder/encoder 80 to operate
`in real time and, preferably, has a bandwidth of at least approximately twice
`the bandwidth required for decoder/encoder 80 to operate in real time. Id. at
`col. 7, ll. 48–51, col. 8, ll. 28–33.
`During operation, decoder/encoder 80, first device 42, and refresh
`logic 58, if it is present, request access to memory 50 through arbiter 82. Id.
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`at col. 12, ll. 53–56. Arbiter 82 determines which of the devices may access
`memory 50. Id. at col. 12, ll. 57–58. Decoder/encoder 80 may get access to
`memory 50 in the first time interval, and first device 42 may get access to
`memory 50 in the second time interval. Id. at col. 12, ll. 58–61. Direct
`Memory Access (DMA) engine 52 of decoder/encoder 80 determines the
`priority of decoder/encoder 80 for access to memory 50 and the burst length
`when decoder/encoder 80 has access to memory 50. Id. at col. 12, ll. 61–67.
`DMA engine 60 of first device 42 determines its priority for access to
`memory 50 and the burst length when first device 42 has access to memory
`50. Id. at col. 12, ll. 65–67.
`When decoder/encoder 80 or one of the other devices generates a
`request to access memory 50, the request is transferred to arbiter 82, and
`access to memory 50 is determined based on the state of arbiter 82 and on a
`priority scheme. Id. at col. 13, ll. 1–30. In particular,
`
`The state of the arbiter 82 is determined. The arbiter typically
`has three states. The first state is idle when there is no device
`accessing the memory and there are no requests to access the
`memory. The second state is busy when there is a device
`accessing the memory and there is no other request to access
`the memory. The third state is queue when there is a device
`accessing the memory and there is another request to access the
`memory.
`Id. at col. 13, ll. 3–10 (emphases added). The priority scheme can be any
`scheme that ensures decoder/encoder 80 gets access to memory 50 often
`enough to operate properly, but does not starve entirely other devices
`sharing memory 50. Id. at col. 13, ll. 31–37; see id. at col. 8, ll. 9–13
`(describing a “starvation period”).
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`C. Illustrative Claim
`
`Of the challenged claims, claims 1 and 7 are independent. Ex. 1001,
`col. 15, ll. 32–59 (claim 1), col. 16, ll. 15–36 (claim 7). Claims 2–4 depend
`directly from claim 1, and claims 8–10 and 12 depend directly from claim 7.
`Id. at col. 15, l. 60–col. 16, l. 9, col. 16, ll. 37–59, 62–63. Claim 1 is
`illustrative and is reproduced below:
`1.
`An electronic system comprising:
`a bus;
`a main memory coupled to the bus having stored therein
`data corresponding to video images;
`a video circuit coupled to the bus, the video circuit
`configured to receive data from the main memory corresponding
`to a current video image to be decoded and to output decoded
`video data corresponding to the current video image to be
`displayed on a display device, the current video image to be
`displayed adapted to be stored in the main memory;
`a processor coupled to the main memory, the processor for
`storing non-image data in the main memory and retrieving non-
`image data from the main memory; and
`an arbiter circuit coupled to the processor and to the video
`circuit, the arbiter circuit configured to receive requests for access
`to the main memory from the video circuit and the processor and
`to control access to the main memory by:
`providing access to the main memory for a request for
`access to the main memory when the arbiter circuit is in an idle
`state;
`
`queuing a request for access to the main memory when the
`arbiter circuit is in a busy state; and
`queuing a request for access to the main memory in an
`order based on a priority of the request and a priority of each of
`one or more other requests for access to the main memory that are
`currently queued when the arbiter circuit is in a queue state.
`Ex. 1001, col. 15, ll. 32–59.
`
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`D. Applied References and Declarations
`
`Petitioner relies upon the following references and declarations in
`support of its grounds for challenging the identified claims of the ’753
`patent:2
`
`
`
`Exhibit
`1002
`1003
`1004
`
`1006
`
`1007
`1008
`1017
`1018
`
`1019
`
`References and Declarations
`File History of Patent No. US 7,777,753 B2
`Patent No. US 5,546,547 (“Bowes”)
`International Organization for Standardization, “ISO/IEC
`11172-2: Information technology—Coding of moving
`pictures and associated audio for digital storage media at up to
`about 1,5 Mbit/s—Part 2: Video,” (1st ed. Aug. 1, 1993)
`(“MPEG”)
`Robert J. Gove, “The MVP: A Highly-Integrated Video
`Compression Chip,” Proceedings of the IEEE Data
`Compression Conference (DCC ‘94), pp. 215–224 (March
`29–31, 1994) (“Gove”)
`Patent No. US 5,774,676 (“Stearns”)
`Declaration of Santhana Chari, Ph.D.
`Patent No. US 5,748,983 (“Gulick”)3
`International Patent Application Publication No. WO
`96/11440, PCT/US95/12933 (“Whai”)
`T. Shanley et al., “PCI System Architecture,” Addison-
`Wesley Publ’g Co. (3rd ed. Feb. 1995) (“Shanley”)
`
`2 Our rules require that Petitioner number its exhibits “sequentially” in a
`range of 1001–1999. 37 C.F.R. § 42.63(c). By “reserving” Exhibit Nos.
`1005, 1010–1013, 1015, 1016, 1021, 1022, and 1026–1028; Petitioner failed
`to follow this rule. Petitioner shall number all future exhibits sequentially
`starting with Exhibit No. 1031. We shall expunge any further exhibits filed
`by either party that are not numbered sequentially. 37 C.F.R. §§ 42.5(a),
`42.7(a), and 24.12(a)(1) and (b)(2).
`3 Although Petitioner refers to this reference as “Gulick 983” (see, e.g., Pet.
`vi), Patent Owner does not (see, e.g., Prelim. Resp. 1). For consistency, we
`will refer to this reference only as “Gulick.”
`
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`1020
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`H. Stone, “Microcomputer Interfacing,” Addison-Welsey
`Publishing Co. (1982)
`Declaration of Harold S. Stone, Ph.D. (the “Stone Decl.”)
`
`1030
`
`
`Pet. vi–vii.
`
`E. Asserted Grounds of Unpatentability
`Petitioner argues that the challenged claims are unpatentable based on
`the following grounds (Pet. 5–6):
`References
`Gulick, MPEG, and Shanley
`Gulick, MPEG, Shanley, and Gove
`Bowes and MPEG
`Bowes, MPEG, and Stearns
`Bowes, MPEG, and Shanley
`Bowes, MPEG, and Whai
`Bowes, MPEG, Whai, and Shanley
`Bowes, MPEG, Whai, and Gove
`
`Basis Claim(s) challenged
`§ 103
`1–4 and 7–10
`§ 103
`12
`§ 103
`1 and 2
`§ 103
`3
`§ 103
`4
`§ 103
`7 and 8
`§ 103
`9 and 10
`§ 103
`12
`
`
`
`II. ANALYSIS
`
`A. Claim Construction
`Pursuant to 37 C.F.R. § 42.100(b), “[a] claim in an unexpired patent
`shall be given its broadest reasonable construction in light of the
`specification of the patent in which it appears.” Petitioner alleges that the
`’753 patent will expire in August of 2016. Pet. 10–11. Patent Owner states
`that the ’753 patent will expire on August 26, 2016. Paper 8, 1. Thus, the
`’753 patent will expire before we are likely to issue a final written decision
`as to the patentability of the challenged claims.
`Although Petitioner proposes a construction based on the broadest
`reasonable interpretation standard for one term, Petitioner argues that its
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`proposed construction will remain the same even if we apply the claim
`construction standard used by the U.S. district courts and set forth in Phillips
`v. AWH Corp., 415 F.3d 1303, 1314 (Fed. Cir. 2005) (en banc). Pet. 11.
`Patent Owner proposes no construction for any term at this preliminary
`proceeding stage. In order to determine if Petitioner has demonstrated a
`reasonable likelihood that it will prevail in this initial proceeding, given the
`patent’s pending expiration, we analyze Petitioner’s arguments through the
`lens of the claim construction standard of Phillips that will apply to our final
`written decision. 37 C.F.R. §§ 42.5(b) and 42.100(b); see Toyota Motor
`Corp. v. Cellport Sys., Inc., Case IPR2015-00633, slip op. at 8–10 (PTAB
`Aug. 14, 2015) (Paper 11); cf. In re Rambus Inc., 694 F.3d 42, 46 (Fed. Cir.
`2012) (“While claims are generally given their broadest possible scope
`during prosecution, the Board’s review of the claims of an expired patent is
`similar to that of a district court’s review.”) (internal citation omitted).
`“In determining the meaning of the disputed claim limitation, we look
`principally to the intrinsic evidence of record, examining the claim language
`itself, the written description, and the prosecution history, if in evidence.”
`DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 469 F.3d 1005, 1014
`(Fed. Cir. 2006) (citing Phillips, 415 F.3d at 1312–17). The words of a
`claim generally are given their ordinary and customary meaning, and that is
`the meaning the term would have to a person of ordinary skill at the time of
`the invention, in the context of the entire patent including the specification.
`See Phillips, 415 F.3d at 1312–13. Claims are not interpreted in a vacuum
`but are a part of and read in light of the specification. See Slimfold Mfg. Co.
`v. Kinkead Indus., Inc., 810 F.2d 1113, 1116 (Fed. Cir. 1987). Although it is
`improper to read a limitation from the specification into the claims, the
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`claims still must be read in view of the specification of which they are a part.
`See Microsoft Corp. v. Multi-Tech Sys., Inc., 357 F.3d 1340, 1347 (Fed. Cir.
`2004).
`1. “decoder”
`Each of challenged claims 7, 8, and 12 recites a “decoder.” E.g., Ex.
`1001, col. 16, ll. 18–25. Petitioner proposes to construe the term “decoder”
`to mean “hardware and/or software that translates data streams into video or
`audio information.” Pet. 9–10 (citing Ex. 1001, col. 1, ll. 66–67 (“a video
`and/or audio decompression device (hereinafter ‘decoder’)”), col. 15, ll. 27–
`30 (“[a]ny conventional decoder complying to the MPEG-1, MPEG-2,
`H.261, or H.261 standards, or any combination of them, or any other
`conventional standard can be used as the decoder/encoder.”)); see Phillips,
`415 F.3d at 1312–13 ( regarding a term’s ordinary and customary meaning
`to a person of ordinary skill in the art, in the context of the entire patent,
`including the specification). Petitioner further relies upon a dictionary
`definition for “decoder” as evidence of the term’s ordinary and customary
`meaning to a person of ordinary skill in the art as of the effective filing date
`of the ’753 patent. Id. at 10 (citing Ex. 1014, 56 (“decoder (n). Any
`hardware or software system that translates data streams into video or audio
`information.”).
`In addition to its usage in the challenged claims, as noted above, the
`’753 patent uses the term “decoder” throughout the Specification.
`Moreover, we find nothing in the usage of the term “decoder” in dependent
`claim 8 or 12 that is inconsistent with the usage of the term elsewhere in the
`Specification of the ’753 patent, with the dictionary definition of “decoder”
`in Exhibit 1014, or with the Petitioner’s proposed construction. The ’753
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`patent’s definition of “decoder” to mean “a video and/or audio
`decompression device,” and its disclosure that the “decoder/encoder” can be
`any conventional decoder complying to any conventional standard support a
`construction of “decoder” that encompasses both hardware and software, are
`persuasive of the term’s proper construction, in the context of the entire ’753
`patent, including the Specification. See, e.g., Ex. 1001, col. 1, ll. 66–67, col.
`15, ll. 27–30.
`Accordingly, on this record, and for purposes of this Decision, we
`adopt Petitioner’s proposed construction of “decoder” as “hardware and/or
`software that translates data streams into video or audio information.” 4
`2. Other Claim Terms
`Petitioner offers no other constructions of any claim term in the
`challenged claims. See Pet. 8–11. Only terms which are in controversy in
`this proceeding need to be construed, and then only to the extent necessary
`to resolve the controversy. Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200
`F.3d 795, 803 (Fed. Cir. 1999). For purposes of this Decision, no other
`claim terms require express construction.
`
`1. Overview
`
`B. Obviousness
`
`Petitioner argues that claims 1–4, 7–10, and 12 of the ’753 patent are
`rendered obvious by Gulick, MPEG, and Shanley or Bowes and MPEG,
`alone or in combination with another reference. See supra Section I.E. A
`
`
`4 On this record, we are persuaded that our construction of the term
`“decoder” set forth above would have been substantially the same had we
`applied the broadest reasonable interpretation standard.
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`patent claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the claimed subject matter and the prior art are “such that the
`subject matter[,] as a whole[,] would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations, including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art; (3)
`the level of skill in the art; 5 and (4) objective evidence of nonobviousness,
`i.e., secondary considerations.6 Graham v. John Deere Co., 383 U.S. 1, 17–
`18 (1966). On this record and for the reasons set forth below, we are
`persuaded that Petitioner demonstrates a reasonable likelihood of prevailing
`in showing that claims 1–4 of the ’753 patent are unpatentable.
`
`2. Claims 1–4 and 7–10 — Obviousness over Gulick, MPEG, and
`Shanley (Ground A)
`Petitioner argues that claims 1–4 and 7–10 are unpatentable under
`35 U.S.C. § 103(a) as obvious over Gulick, MPEG, and Shanley. Pet. 12–
`36.
`
`
`5 Petitioner proposes a definition for a person of ordinary skill in the art.
`Pet. 11 (citing Ex. 1030 ¶¶ 78–81). Patent Owner does not challenge
`Petitioner’s proposed definition and does not propose an alternative. To the
`extent necessary and for purposes of this Decision, we adopt Petitioner’s
`definition.
`6 Patent Owner does not contend in its Preliminary Response that such
`secondary considerations are present.
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`Gulick (Ex. 1017)
`a.
`Gulick describes a computer system having a dedicated multimedia
`engine and multimedia memory having arbitration logic which grants main
`memory access to either the central processing unit (CPU) or the multimedia
`engine. Ex. 1017, Title, Abstract. Figure 1 of Gulick is reproduced below.
`
`
`
`Figure 1 is a block diagram of a computer system including main memory
`110, multimedia engine 112, and multimedia memory 160. Id. at col. 3,
`ll. 29–31. The computer system includes CPU 102 coupled to chipset 106,
`which includes arbitration logic 107. Id. at col. 4, ll. 1–4. Chipset 106 is
`similar to known chipsets, but includes modifications to arbitration logic 107
`in order to accommodate multimedia engine 112. Id. at col. 4, ll. 4–8.
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`Chipset 106 and main memory 110 couple to multimedia engine 112 through
`memory bus 108. Id. at col. 4, ll. 10–16.
`Multimedia memory 160 also is coupled to memory bus 108 through
`arbitration block 161. Id. at col. 4, ll. 26–27. In a preferred embodiment,
`multimedia memory 160 is mapped to the main memory address space and,
`thus, is available to store non-multimedia data if, for example, main memory
`110 becomes full and CPU 102 needs to store code and data. Id. at col. 4, ll.
`31–40; see id. at col. 7, l. 65–col. 8, l. 3, Fig. 6; Pet. 13. Alternatively,
`multimedia memory 160 may be “comprised in the multimedia engine 112
`instead of external to the multimedia engine 112.” Id. at col. 6, ll. 4–7; see
`id. at Figs. 4 and 5. In either of these alternative embodiments, however,
`multimedia memory 160 remains distinct from the main memory in structure
`and priority in operation. See id. at col. 6, ll. 8–11 (referring to the
`embodiment of Figs. 4 and 5), col. 8, ll. 4–8 (referring to the embodiment of
`Fig. 6).
`Multimedia engine 112 performs video and audio processing
`functions. Id. at col. 4, ll. 16–18. Those functions are performed by one
`digital signal processor (DSP) engine 210, as shown in Figure 2, reproduced
`below, or by two or more DSP engines, as shown in Figure 3, reproduced
`below.
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`Figures 2 and 3 are block diagrams of embodiments of multimedia engine
`112. Id. at col. 3, ll. 32–35.
`In operation, multimedia engine 112 and CPU 102 arbitrate for access
`to multimedia memory 160. Id. at col. 8, ll. 4–7. A priority based
`arbitration scheme may be used. Id. at col. 8, ll. 15–17.
`b. MPEG (Ex. 1004)
`MPEG describes the coded representation of video for digital storage
`media and specifies the decoding process for the MPEG-2 standard.
`Ex. 1004, 1. The MPEG standard was known and accessible at least as of
`August of 1993. Ex. 1008 ¶ 8.
`c.
`Shanley (Ex. 1019)
`In Shanley, simultaneously-received bus masters’ requests are
`assigned one of two priority groups. Ex. 1019, 79–81. An arbiter may give
`greater priority to bus masters in the first group than the second group. Id.
`In particular, “[t]he arbiter can be programmed or designed to treat each
`group as rotational priority within the group and rotational priority between
`the two groups. This is pictured in figure 6-2.” Id. at 80. “The masters in
`the first group are permitted to access the bus more frequently than those
`that reside in the second group.” Id. at 81.
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`Shanley explains that Master A has priority over Master B and Master B has
`priority over the “Second Group,” i.e., Masters X, Y, and Z. Id. at 80–81.
`Thus, in Shanley’s exemplary arbitration scheme, the arbitration/priority
`sequence would be “A → B → X → A → B → Y→A → B → Z → A → B
`→ X, and so on.” Pet. 20 (citing Ex. 1019, 80).
`d.
`Analysis
`In light of the arguments and evidence of record, Petitioner has not
`established a reasonable likelihood that claims 1–4 and 7–10 are
`unpatentable as obvious over Gulick, MPEG, and Shanley.
`Independent claim 1 recites “a main memory” that is shared by the
`“processor” and the “video circuit.” Ex. 1001, col. 15, ll. 36–45. Similarly,
`independent claim 7 recites “a memory” that is shared by the “central
`processing unit” and the “decoder.” Id. at col. 16, ll. 17–35. Petitioner
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`identifies Gulick’s multimedia memory 160 and argues that it is “shared”
`because Gulick teaches that “arbiter block 161 performs arbitration between
`the CPU 102 and the multimedia engine 112 for the multimedia memory.”
`Pet. 12–13 (claim 1) (citing Ex. 1017, col. 4, ll. 26–27); see Pet. 28 (claim
`7). We are not persuaded, however, that Gulick’s multimedia memory 160
`is shared by the processing and video decoding components of claims 1 and
`7.
`
`The ’753 patent describes decoder/encoder 80 and a first device using
`a single memory. See, e.g., Ex. 1001, Figs. 2–4. Gulick, in contrast,
`describes main memory 110 in addition to multimedia memory 160. Ex.
`1017, Figs. 1, 4, and 6. The system described in Gulick does not, therefore,
`realize the advantage of sharing a single memory described by the ’753
`patent. Ex. 1001, col. 5, ll. 13–15, 47–51.
`Gulick describes CPU 102 as using primarily main memory 110.
`Referring again to FIG. 1, in the preferred embodiment, the
`main memory 110 stores the operating system and applications
`software as well as driver software, including video drivers and
`audio drivers. The CPU 102 executes applications software and
`driver software from the main memory 110 and writes any
`associated video and audio data to the main memory 110. The
`CPU 102 then provides high level instructions directly to the
`multimedia memory 160 and/or to the DMA engine 164, or to
`the multimedia engine 112.
`Ex. 1017, col. 6, ll. 13–22. Gulick further describes CPU 102 using
`multimedia memory 160 only in exceptional circumstances, such as when
`main memory 110 is full.
`Thus the multimedia memory 160 is available to store non-
`multimedia data as needed. In other words, if the main memory
`110 becomes full and additional memory is needed, the CPU
`102 can store code and data in the multimedia memory 160.
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`Thus, the multimedia memory 160 is used for real-time or
`multimedia data and is also used by the CPU 102 as overflow
`memory space.
`Id. at col. 4, ll. 34–40; see also id. at col. 8, ll. 2–3 (“Thus the multimedia
`memory 160 is available to store non-multimedia data as needed.”). Further,
`even when the multimedia memory is carved out from the main memory, as
`depicted in Gulick’s Figure 6, multimedia engine 112 preferably has priority
`access to multimedia memory 160. Id. at col. 8, ll. 7–8. Accordingly, in an
`embodiment, “the multimedia engine 112 simply writes one or more bits to a
`register in the arbiter 161 to gain control of the multimedia memory 160, and
`the CPU 102 is only granted access to the multimedia memory 160 after a
`certain starvation period.” Id. at col. 8, ll. 9–13 (emphases added).
`Because multimedia memory 160 exists in addition to main memory 110 and
`because CPU 102 uses multimedia memory 160 only in exceptional
`circumstances, we are not persuaded that multimedia memory 160 teaches or
`suggests the shared “main memory” of claim 1 or “memory” of claim 7.
`Even assuming that multimedia memory 160 is shared, we still are not
`be persuaded that modifying Gulick’s multimedia engine 112 to perform
`MPEG video decoding would have been obvious. Pet. 14–15. Independent
`claim 1 recites
`
`the video circuit configured to receive data from the main
`memory corresponding to a current video image to be decoded
`and to output decoded video data corresponding to the current
`video image to be displayed on a display device, the current
`video image to be displayed adapted to be stored in the main
`memory.
`Ex. 1001, col. 15, ll. 36–42. Petitioner acknowledges that Gulick does not
`disclose that multimedia engine 112 is configured to receive data from the
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`main memory corresponding to a current video image to be decoded and to
`output decoded video data corresponding to the current video image to be
`displayed on a display device and stored in the main memory. Pet. 14.
`Nevertheless, Petitioner argues that a person of ordinary skill in the art
`would have reason to modify Gulick’s “multimedia engine 112 in view of
`MPEG Standard to perform MPEG video decoding, which would have
`resulted in the claimed elements.” Id. at 15 (emphasis added). In particular,
`when implementing MPEG video decoding, one of ordinary
`skill in the art would have understood that Gulick’s multimedia
`to receive data from
`engine 112 would be configured
`multimedia memory 160 corresponding to a current video image
`to be MPEG-video decoded and
`to output video data
`corresponding to the current video image to be displayed on
`video monitor 114 via video port 172, the current video image
`to be displayed adapted to be stored in multimedia memory 160.
`Id. (emphases added) (citing Ex. 1030 ¶¶ 95–100). However, Petitioner fails
`to explain why a person of ordinary skill in the art would equate Gulick’s
`multimedia memory 160 with main memory 110 for purposes of
`implementing MPEG standards on Gulick’s system. Prelim. Resp. 10–11;
`see Ex. 1030 ¶ 99 (“Under Gulick 983, the multimedia memory 160 would
`serve as the previous and future picture stores shown above in Figure D.7 [of
`MPEG].”). Further, Petitioner does not adequately explain why a person of
`ordinary skill in the art would have reason to modify Gulick to disclose
`“storing a decoded video image in a ‘main memory’ (independent claim
`1)/‘memory’ (independent claim 7) that is shared by a video circuit/decoder
`and a processor/central processing unit.” Id. at 15; see Ex. 1030 ¶ 100.
`Petitioner argues that modification of Gulick’s multimedia engine 112 to
`perform MPEG video decoding “would constitute a combination of familiar
`elements according to known methods to yield predictable results.” Pet. 15–
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`16 (citing KSR, 550 U.S. at 401). We are not persuaded that such a
`conclusory statement and citation to KSR amount to more than
`impermissible hindsight and are sufficient to support Petitioner’s arguments
`for the combination of the cited references in the manner proposed to
`achieve the recited systems.
`On this record, Petitioner does not explain adequately how Gulick
`would have been modified in view of MPEG and Shanley. Pet. 15–16.
`Dr. Stone’s testimony is equally insufficient. In paragraph 101, for example,
`Dr. Stone testifies that “[a]t the time of the alleged invention of the ’753
`Patent, the MPEG-1 and MPEG-2 standards were ‘currently in use.’ [Ex.
`1001, col. 1, ll. 53–58.] Indeed, the ’753 Patent admits that ‘[t]he MPEG
`standards [were] currently well accepted standards.’ [Id. at col. 2, ll. 6–9.]”
`Ex. 1030 ¶ 101. Neither Petitioner nor its declarant explains in sufficient
`detail why or how a person of ordinary skill in the art would have modified
`Gulick’s system in view of MPEG to provide the recited structures for
`accessing Gulick’s “main memory” or to perform the functions recited for
`video decoding or decompression.
`e.
`Conclusion
`On this record, we are not persuaded that Petitioner has established a
`reasonable likelihood that it would prevail in showing that claims 1–4 and
`7–10 are unpatentable as obvious over Gulick, MPEG, and Shanley.
`
`3. Claim 12 – Obviousness over Gulick, MPEG, Shanley, and Gove
`(Ground B)
`Petitioner argues that claim 12 is unpatentable under
`35 U.S.C. § 103(a) as obvious over Gulick, MPEG, Shanley, and Gove. Pet.
`36–38.
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`a. Gove (Ex. 1006)
`Gove describes Texas Instruments, Inc.’s Multimedia Video Processor
`(MVP). The MVP is a “highly-integrated processing chip for performing a
`variety of functions” and is “particularly well suited for video compression
`algorithms.” Ex. 1006, 215 (Abstract).
`b. Analysis
`Claim 12 depends from independent claim 7. Petitioner relies upon its
`analysis Gulick, MPEG, and Shanley to teach the limitations of independent
`claim 7, and relies upon Gove only for the additional limitations recited in
`the dependent claim 12. See, e.g., Pet. 36 (“Gulick 983, in view of MPEG
`Standard and Shanley, discloses all claimed elements of claim 7.”). As
`discussed above, we are not persuaded that Petitioner has established a
`reasonable likelihood that independent claim 7 would have been obvious
`over Gulick, MPEG, and Shanley. See supra Section II.B.2. In these
`g