1%:£‘£l:§s?§
`
`
`?s=:%€§$§§$
`
` §’§s“s;s§f;are-35
`
`
`.?€§3§s‘2:s?§’ F51;
`
`€11;
`
`Apple Exhibit 1017
`Page 1 of 5
`
`Apple Exhibit 1017
`Page 1 of 5
`
`

`
`
`
`_
`
`Ffiflfiflifli *
`
` F
`
`E1
`
`V<‘:§3: EEEEE
`
`3%: §?E§%3.{§§% §%f%1§3‘¥3i $351 "§§ii;€‘§ gfififififiifi
`
`@3221} am 333*» it 4,53 aiigiém,
`
`§"‘§;~"§a%"a g’a:s::E§::r¥ 33 £1,313; a;‘i3aiz1*«a:a:‘ar§‘:€$%
`
`§§‘3%i‘§a3¥E a.:aa“% 31$: 4-%;s'a‘§'aLHi:a:¥ §as3'a§§_§‘ aré 2"%§4:fi§;'fiH"i;%§ii;fi%.‘E§} iii
`3%}; L Efiifi sé
`£3342: Q ‘a'fl7{:a'§'.~¥
`3»
`flaw: f*“3i3“§ we.
`3; :TZ!3€§”
`;‘31‘m§a:‘aL
`§fi‘=‘§Zf¥£E€" % 33% Eaifii
`§i‘i‘fi:"3;“§: :;‘3l3?i.¥ii§§.i5.E‘a'% %%€‘.§.§% Taiaaiaiaiafag 33%? awafigiigséfiiy fisiiii éfffiiiig ggaéiwasa.
`33:4 E344 yiifiifiifiifi
`aaifiaflfiisfi
`gaagaaaia:
`Ii a=§i§‘%5 —*
`§§a:s§$§£a§,==3:a3§a?: ‘is: 2% $33 :1; ma ~33“; 3%.’?-§4£—E§%3iZ§r Mafi
`1!:
`$2 3312?; ia§aa*a§§s:g§*::a,
`f<1sl..§.r:’f fig fiééégfisé $3?’ §:""§E7i¥‘£ii.§_§‘i
`22;:
`“
`
`33% fiafiv
`
`E
`
`:3? §*:$‘{=?i"a;%'aEfi §:§:>;2a§a3a;“%s§E-
`
`?£a‘§§EEa fie;
`
`3%‘??? mail gaa
`
`?:—L‘=$.§.—‘§3"
`§£§
`gig ‘{a:a fwi H £%fi ifi 3
`§:s=:af%:sfi:ia‘a:£
`is‘ iiaaaigsisfig £a§a;1 E?€§a:£E
`
`‘fizz
`
`ifi 33:33};
`
`am
`
`'%fi*!% 5331 Hrs 49%;
`
`;fiT:i§i33
`
`“BE
`
`ET: fig
`
`:4. ::;.;:2
`
`*%§?.a§
`
`£és;&’:%=:§§ar
`aiizaézza ii:
`
`%¥‘ ?:;,;{a3i§£s‘a :‘f~"*%*Ea §3€r3:€i,;.
`
`Eeifiaiarsyzfil 3} fiaazw
`
`a;s;€§a;:ai§a.*a?§, E37? ?=:sE§ v 2 fisaaa gétamiaua %a%:i%34;%.£ aéaémmfi aim: ix
`fifiériéiéifig“ $3;-“Ease 4;» fag}? aalafzéaifl £££sf=
`~f2§ag%E§::£’: §a;§€i
`
`:~'a-iiéiga
`"
`
`
`
`T
`
`: __
`
`
`
`
`
`
`Page 2 of 5
`
`,?siii;wa3—';ma:+E§
`Z‘
`
`55-
`,
`,
`_ _ ,
`
`H
`iii‘:
`32%
`
`
`pple Exhibit 1017
`
`Apple Exhibit 1017
`Page 2 of 5
`
`

`
`
`
`This article begins by presenting an overview of the
`Pentium processor. It then details the key technological
`features that enable the Intel solution to meet the mar-
`ket’s evolving requirements for high performance, con-
`tinued software compatibility, and advanced function-
`ality.
`
`THE WORLD'S BEST PERFORMANCE
`FOR ALL PC SOFTWARE
`
`The Pentium processor family includes the highest per-
`forming members of Intel‘s family of microprocessors.
`
`
`
`Intel’s Pentium® processor family combines the per-
`formance traditionally associated with minicomputers
`and workstations with the flexibility and compatibility
`that characterize the personal computer platform. De-
`signed to meet the needs of today’s and tomorrow’s
`sophisticated software applications, the Pentium proc-
`essor extends the range of Intel’s microprocessor archi-
`tecture to new heights, blurring previous distinctions
`between hardware platforms and creating an entirely
`new realm of possibilities for notebook computers,
`desktop PCs, and servers.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
` Pentium® Processor
`
`
`75/90/100/ 1 20/133 Core Frequency
`
`
`
`External Bus Interface
`
`iCOMP® Index
`
`
`
`
`
`
`
`
`the system bus frequencies range from 50 MHz to 66
`MHz, allowing cost effective system designs.
`
`THE PENT|UM® PROCESSOR:
`TECHNICAL INNOVATIONS
`A number of innovative product features contribute to
`the Pentium processor’s unique combination of high
`performance, compatibility, data integrity and upgrad-
`ability. These include:
`0 Superscalar Architecture
`0 Separate 8K Code and Data Caches
`' Writeback MESI Protocol in the Data Cache
`0 Dynamic Branch Prediction
`0 Pipelined Floating-point Unit
`0 Improved Instruction Execution Time
`0 64-Bit Data Bus
`
`0 Bus Cycle Pipelining
`1 Address Parity
`0 Internal Parity Checking
`0 Functional Redundancy Checking
`0 Execution Tracing
`0 Performance Monitoring
`
`V
`
`While incorporating new features and improvements
`made possible by advances in semiconductor technolo-
`gy, the Pentium processor is fully software compatible
`with previous members of the Intel microprocessor
`family-thereby preserving the value of users’ software
`investments. The Pentium processor meets the de-
`mands of computing in a number of areas: advanced
`operating systems, such as DOS‘, Windows‘, OS/2*,
`and UNIX*; computing-intensive graphics applica-
`tions, such as 3-D modeling, computer-aided design/
`engineering (CAD/CAE), large scale financial analysis,
`high-throughput client/server, handwriting, and voice
`recognition; network applications; virtual reality; elec-
`of the above areas; and
`tronic mail that combines many
`new applications yet to be developed.
`
`The Pentium processor family was designed using an
`y and has features that are
`advanced process technolog
`onth of a meter) in size.
`less than a micron (one-milli
`The Pentium processor (5l0\60, 567\66) was devel-
`oped utilizing 5V, 0.8 micron technology, while the
`Pentium processor
`(6l0\75,
`735\90,
`815\l00.
`l000\l20, lll0\l33) was designed using 3.3V, 0.6 mi-
`cron and 3.3V, 0.35 micron technology.
`
`(1 Pentium processor family
`The increasingly improve
`brings the users CPUs with higher frequencies, while
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Apple Exhibit 1017
`Page 3 of 5
`
`
`
`November 1995
`Order Number: 242423-G02
`
`Apple Exhibit 1017
`Page 3 of 5
`
`

`
`
`
`THE PENTIUPW9 FAMILY-A TECHNICAL QVERVIEW
`
`intel.
`
`This improves performance without affecting compati-
`bility. In the case of more complex instructions, the
`Pentium processor’s
`enhanced microcode
`further
`boosts performance by employing both dual
`integer
`pipelines to execute instructions.
`
`Separate 8K Code and Data Caches
`Pentium processors include separated code and data
`caches integrated on-chip to meet performance goals.
`On-chip caches increase performance by acting as tem-
`porary storage places for commonly-used instructions
`and data, replacing the need to go off-chip to the sys-
`tem’s main memory to fetch information. The separate
`caches reduce bus conflicts and are available more often
`when they are needed.
`
`The Pentium processor’s code and data ‘caches each
`contain 8 Kbytes of information and both are organized
`as two-way set associative caches-meaning that they
`save time by searching only pre-specified 32—byte seg-
`ments rather than the entire cache. Each cache has a
`dedicated Translation Lookaside Buffer (TLB) to trans-
`late linear addresses to physical addresses.
`
`The Pentium processor’s data cache is configurable to
`be “writeback” or “write through” on a line-by-line ba-
`sis and follows the MESI (Modified, Exclusive, Shared,
`Invalid) protocol. The “writeback” method transfers
`data to the cache without going out to main memory.
`Data is written to main memory only when it is re-
`moved from the cache. In contrast, the “write through”
`method transfer data to the external memory each time
`the processor writes data to the cache. The “writeback”
`technique increases performance by reducing bus utili-
`zation and preventing unnecessary bottlenecks in the
`system.
`
`To ensure that data in the cache and in main memory
`are consistent, the data cache implements the MESI
`protocol during reads and writes. This is especially im-
`portant in a multiprocessor environment.
`
`Dynamic Branch Prediction
`Branch prediction is an advanced computing technique
`that boosts performance by keeping the execution pipe-
`lines full. It is accomplished by predetermining the
`most likely set of instructions to be executed.
`
`
`
`Page 4 of 5
`
`Apple Exhibit 1017
`
`0 IEEE‘ 1149.1 Boundary Scan '
`0 System Management Mode
`0 Virtual Mode Extensions
`0 Upgradable With a Future Pentium OverDrive®
`Processor
`‘
`1‘
`' Multiprocessor Support
`
`In addition to the features listed above, the Pentium
`processor 75/90/ 100/120/ 133 offers the following en-
`hancements overithe Pentium processor 60/66'
`9 Dual Processing Support
`
`0 SL Power Management Features
`5 Fractional Bus Operation
`0 On-chip Local APIC Device
`
`superscalar Architecture
`
`The Pentium processor’s superscalar architecture en-
`ables the processor to achieve superior performance by
`executing more than one instruction per clock cycle.
`-he term “superscalar” refers to a microprocessor ar-
`chitecture that contains more than one execution unit.
`-hese execution units, or piplines are where the CPU
`processes the data and instructions that are fed to it by
`the rest of the system.
`
`The Pentium processor’s superscalar implementation
`represents a natural progression from previous genera-
`tions of processors in the 32-bit Intel architecture. The
`Intel486TM processor for instance, isable to execute
`many instructions in one clock cycle, while previous
`generations of Intel microprocessors require multiple
`clock cycles to execute a single instruction.
`
`The ability to execute multiple instructions per clock
`cycle is due to the fact that the Pentium processor has
`two pipelines that can execute two instructions simulta-
`neously. The Pentium processor’s dual pipelines exe-
`cute integer instructions in five stages: prefetch, de-
`code], decoa’e2, execute and writeback. This permits
`several instructions to be in various stages of execution,
`thus increasing processing performance.
`
`The Pentium processor also uses hardwired instruc-
`tions to replace many of the microcoded instructions
`used in previous microprocessor generations. Hard-
`wired instructions are simple and commonly used, and
`can be executed by the processor’s hardware without
`requiring microcode.
`
`
`
`
`
`Apple Exhibit 1017
`Page 4 of 5
`
`

`
`ntel.
`
`THE PENT|UM® FAMILY-A TECHNICAL OVERVIEW
`
`To understand the concept better, consider a typical
`application program. After each pass through a soft-
`ware loop, the program performs a conditional test to
`determine whether to return to the beginning of the
`loop or to exit and continue on to the next execution
`step. These two paths are ‘called branches. Dynamic
`branch prediction forecasts which branch the software
`will require, based on the assumption that the previous
`taken branch will be used again. Pentium processors
`make prediction by using a Branch Target Buffer
`(BTB). Pentium processors also implement two pre-
`fetch buffers, one to prefetch code in a linear fashion
`and the other to prefetch code according to the address-
`es in the BTB. As a result, the needed code is always
`prefetched before it is required for execution. In ‘addi-
`tion, the Pentium processors support more sophisticat-
`ed algorithms by using two level branch prediction.
`
`Pipe-lined Floating-Point Unit
`
`The 32-bit compute-intensive software applications re-
`quire a high degree of floating-point processing power
`to handle mathematical calculations. As the floating-
`point requirements of personal computer software have
`steadily increased, advances in microprocessor technol-
`ogy have been introduced to satisfy these needs. The
`Intel486 DX processor, for example, was the first Intel
`microprocessor to integrate math coprocessing func-
`tions on-chip; previous-generation Intel processors used
`off-chip math coprocessors when floating-point calcula-
`tions were required.
`
`The Pentium processor family takes math computation-
`al ability to the next performance level by using an
`enhanced on-chip floating-point unit that incorporates
`sophisticated eight-stage pipeline and hardwired func-
`tions. A three—stage floating-point instruction pipeline
`is appended to the integer pipelines. Most floating-point
`instructions begin execution in one of the integer pipe-
`lines, then move on to the floating-point pipeline. In
`addition, common floating-point functions; such as,
`add, multiply and divide, are hardwired for faster exe-
`cution.
`
`Enhanced 54-it ata
`
`The data bus is the highway that carries information
`between the processor and the memory subsystem. Be-
`cause of its external 64-bit data bus, the Pentium proc-
`essor can transfer data to and from memory at rates up
`to 528 Mbytes/second, a more than five-fold increase
`
`over the peak transfer rate of the 66 MHz Intel DXZTM
`microprocessor (105 Mbytes/second). This wider data
`bus facilitates high-speed processing by maintaining the
`flow of instructions and data to the processor’s supers-
`calar execution ‘unit.
`
`In addition to having a wider data bus, the Pentium
`processor implements bus cycle pipelining to increase
`bus bandwidth. Bus cycle pipelining allows a second
`cycle to start before the first one is completed. This
`gives the memory subsystem more time to decode the
`address, which allows slower and less-expensive memo-
`ry components to be used, resulting in a lower overall
`system cost. Burst reads and writes, parity on address
`and data, and a simple cycle identification all contrib-
`ute to providing greater bandwidth and improved sys-
`tem reliability.
`
`The Pentium processor also has two.write buffers, one
`corresponding to each pipeline,
`to enhance the per-
`formance of consecutive writes to memory. Write buff-
`ers improve performance by allowing the processor to
`proceed with the next pair of instructions, even though
`one of the current instructions needs to write to memo-
`ry while the bus is busy.
`
`ata Integrity and Error etection
`Features
`
`Protecting important data and ensuring its integrity has
`become increasingly important as mission-critical appli-
`cations continue to proliferate. To ensure the Pentium
`processors’ reliability, Intel ran millions of simulations
`and tests. In addition, designers have added significant
`data integrity and error detection capability. Data pari-
`ty checking is supported on byte-by-byte basis. Address
`parity checking, and internal parity checking features
`have been added along with a new exception, the ma-
`chine check exception.
`
`Internal error detection places parity bits on the inter-
`nal code and data caches, translation look aside buffers,
`microcode, and branch target buffer. This feature helps
`to detect errors in a manner that remains transparent to
`both the user and the system.
`
`Furthermore, the Pentium processors have implement-
`ed functional redundancy checking to provide maxi-
`mum error detection of the processor and the interface
`to the processor. When functional redundancy check-
`ing is used, two Pentium processors act as “master”
`and “checker” respectively. The “checker” is used to
`
`Apple Exhibit 1017
`Page 5 of 5
`
`Apple Exhibit 1017
`Page 5 of 5