" scassss s sasasssaaass lllififiifiifi.’
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`PCI System y
`Architecture
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`Third Edition
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`MINDSHARE, INC.
`
`TOM SHANLEY
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`_
`AND
`_
`DON ANDERSON
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`a E C E I V E 9
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`A
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`VY
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`sages sclfiléfi
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`Addison-Wesley Publishing Company
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`Reading, Massachusetts 0 Menlo Park, California 0 New York
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`Don Mills, Ontario 0 Wokingham, England 0 Amsterdam
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`A Ie Exhibit 1010
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`Apple Exhibit 1010
`Page 1 of 69
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`Many of the designations used by manufacturers and sellers to distinguish their
`products are claimed as trademarks. Where those designations appear in this book,
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`Library of Congress Cataloging-in-Publication Data
`
`ISBN: 0-201-40993-3
`
`Copyright © 1995 by Mindshare, Inc.
`
`All rights reserved. No part of this publication may be reproduced, stored in a
`retrieval system, or transmitted, in any form or by any means, electronic, mechanical,
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`publisher. Printed in the United States of America. Published simultaneously in
`Canada.
`'
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`Sponsoring Editor: Keith Woilman
`Project Manager: Eleanor McCarthy
`Production Coordinator: Lora L. Ryan
`Cover design: Barbara T. Atkinson
`Set in 10 point Palatino by Mindshare, Inc.
`
`1 2 3 4 5 6 7 8 9 -MA- 9998979695
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`First printing, February 1995 '
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`To Nancy and Sheryl, two very understanding 1adje5_
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`Contents
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`Contents
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`_ Acl‘cn_o1_/v1e'¢_:1grr_1‘e_r_l_ts....:..,..L.=.,.,_..,..:,.._....
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`......._....._,.._._......_._.,...............
`
`About This Book
`The MindShare Architecture Series ................................................................................ 1
`
`Organization of This Book ............................................................................................. .. 2
`Who this Book is For ....................................................................................................... .. 2
`
`Prerequisite Knowledge................................;................................................................... 3
`Object Size Designations .........................................................................................'......... 3
`Documentation Conventions.....;.....................................................,................................ 3
`Hex Notation .............. .§.............................................................................................. .. 3
`
`Binary Notation .......................................................................................................... .. 3
`Decimal Notation ....................................................................................................... .. 4
`
`Signal Name Representation ..................................................................................... .. 4
`Identification of Bit Fields (logical groups of bits or signals) ................................... 4
`.
`We Want Your Feedback ................................................................................................. .. 4
`Bulletin Board ............................................................................................................. .. 5
`
`Mailing "Address .........
`
`................_................................................................................ 5
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`Part I: Introduction to the Local Bus Concept
`
`CHAPTER 1: The Problem
`Block-Oriented Devices .'................................................................................................. .. 9
`
`Graphics Interface Performance Requirements ....................................................... .. 9
`SCSI Performance Requirements .............................................................................. .. 10
`Network Adapter Performance Requirements ............................................... .: ....... .. 10
`X—Bus Device Performance Constraints ................................................................... 10
`
`......................................................... .. 13
`Expansion Bus Transfer Rate Limitations ........
`ISA Expansion Bus ..................................................................................................... .. 13
`EISA Expansion Bus.................................................................
`.................................. 13
`Micro Channel Architecture Expansion Bus ............................................................ .. 13
`Teleconferencing Performance Requirements ............................................................. .. 14
`
`
`I
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`CHAPTER 2: Solutions, VESA and PCI
`Graphics Accelerators: Before Local Bus ...................................................................... .. 19
`Local Bus Concept.............................................................................................................. 20
`Direct-Connect Approach...........................................
`........................................:...... 20
`Buffered Approach......................................................§ .............................................. .. 22
`Workstation Approach .............................................................................................. .. 24
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`..............................
`VESA VL Bus Solution ...............................................................
`Logic Cost ............................................. .._. ............................................................. ..
`Performance ........................................... .; ............................................................. ..
`
`—--
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`-—- -— .
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`_
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`_
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`_
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`.......................................... ., ................ ..
`Longevity ...............................................
`_ Teleconferencing Support.....................................................................................
`Electricaflntegrity.';..'.;...:...'..;.............-...........
`..........................
`Add-in Connectors .............................................................................................. ..
`
`__
`
`Auto—Configuration............................................................................................. ..
`Revision 2.0 VL Specification ............................................................................. ..
`PCI Bus Solution ............................................................. ..'........................................ ..
`Market Niche for PCI and VESA VL ........................................................................
`PCI Device .................... ..- ..................................................................................... ..
`
`Specifications Book is Based on ......................................................................... ..
`Obtaining PCI Bus Specification(s) .................................................................... ..
`
`Part II:.Revision 2.1 Essentials
`
`
`CHAPTER 3: Intro to PCI Bus Operation
`Burst Transfer ........................................................................................................... ..
`Initiator, Target and Agents......................................................................................
`_ Single vs. Multi-Function PCI Devices ...................................................................
`PCI Bus Clock........................................................................................................... ..
`Address Phase ...................1...................................................................................... ..
`
`Claiming the Transaction ....................................................................... .:.............. ..
`Data I’hase(s) .............................................................................................................
`Transaction Duration................................................................................................
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`Transaction Completion and Return of Bus to Idle State................................
`"Green" Machine ......................................................................................................
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`CHAPTER 4: Intro to Reflected-Wave Switching
`Each Trace Is a Transmission Line ....................................... .;.............................. ..
`
`Old Method: Incident—Wave Switching .................................................................
`PCI Method: Reflected-Wave Switching ..............................................................
`PCI Timing Characteristics .....................................................................................
`Introduction ...................................................................................................... ..
`
`CLK Signal .................... ..: ................................................................................. ..
`Output Timing .................................................................................................. ..
`‘Input Timing.......................................................................................................
`RST#/REQ64# Timing ....... ..L ........................................................................... ..
`Slower Clock Permits Longer Bus ...................................... ..' ............................... ..
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`Contents
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`CHAPTER 5: The Functional Signal Groups
`Introduction ............................................................................................................
`
`...... 53
`
`.
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`................................ .. 56
`System Signals ..............................................................................
`- .-PCl C‘,1oc1cSignal—(CLI.().... .................. ......... ........................._......... ...............56» —.-—- -
`CLKRUN# Signal ....................................................................................................... .. 57
`General ............................................................................................... .L ................ .. 57
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`—
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`-— .-
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`.— -.__
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`a
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`Reset Signal (RST#) .................................................................................................... .. 58
`AclclresslData Bus.....-.......................................................................................................... 58
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`Preventing Excessive Current Drain.............................................................................. .. 62
`Transaction Control Signals ..........
`...................
`........................................................ .. 63
`Arbitration Signals ....................................................................................................
`64
`Interrupt Request Signals
`...........
`.......
`...............
`..................
`.......................... 65
`Error Reporting Signals ................................................................................................... .. 65
`Data Parity Error .................................................................................................. .L .... .. 65
`System Error ......................................................................................................... .'. .... .. 66
`Cache Support (Snoop Result) Signals ..............................................................
`....
`67
`64-bit Extension Signals .........................................
`................................................. .. 68
`Resource Locking ............................................................................................................. .. 69
`JTAG/Boundary Scan Signals .............................................................
`......................... .. 70
`Interrupt Request Lines ......
`.........
`.........
`..............
`........................
`............. .. 71
`Sideband Signals ............................. ..‘.............................................................................. .. 71
`Signal Types
`............
`........
`.....
`............................................................................ .. 71
`Central Resource Functions ............................................................................................ .. 72
`Subtraclive Decode ..................................................................................................
`..... .. 73
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`Background ................................................................................................................. .. 73
`Tuning Subtractive Decoder...................................................................................... .. 74
`Reading Timing Diagrams .............................................................................................. .. 75
`
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`CHAPTER 6: PCI Bus Arbitration
`Arbiter ................................................................................................................................. 77
`
`........ .. 79
`Arbitration Algorithm ..........................................................................................
`Example Arbiter with Fairness .................
`................
`..........................
`............. .. 80
`Master Wishes To Perform More Than One Transaction ........................................... .. 82
`Hidden Bus Arbitration ..............
`............................................................................. .. 82
`
`Bus Parking......................................................................................................................... 82
`Re questIGrant Timing............................................................§.......................
`............. 34
`Example of Arbitration Between Two Masters ..........................
`............
`........
`55
`Bus Access Latency .......................................................................................................... .. 89
`Master Latency Timer: Prevents Master From Monopolizing Bus ........................ .. 91
`Location and Purpose of Master Latency Timer............................................... .. 91
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`- PCI System Architecture
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`How LT Works .................................................................................................... .. 91
`
`Is Implementation of LT Register Mandatory? ................................................. .. 92
`Can LT Value Be Hardwired (read-only)? '..'.....
`..............
`...... .:...;........... .;.; .... .; 92
`How Does Configuration Software Determine Timeslice To
`Be Allocated To Master? ................................................................................... .. 92
`
`Treatment of Memory Write and Invalidate Command .................................. .. 92
`Limit on Master's Latency .................................................................................. .. 93
`Preventing Target From Monopolizing Bus ............................................................. .. 93
`General ................................................................................................................. .. 93
`
`Target Latency on First Data Phase ................................................................... .. 95
`Options for Achieving Maximum 16 Clock Latency ........................................ .. 95
`Different Master Attempts Access To Device With
`Previously-Latched Request ............................................................................. .. 97
`Special Cycle Monitoring While Processing Request .....................
`................ .. 97
`Delayed Request and Delayed Completion ........................................................ 97
`Handling Multiple Data Phases ......................................................................... .. 97
`Master or Target Abort Handling ...................................................................... .. 97
`Commands That Can Use Delayed Transactions ............................................. .. 98
`Delayed Read Prefetch ..........................
`............................................................ .. 98
`Request Queuing and Ordering Rules ............................................................... .. 98
`Locking, Delayed Transactions and Posted Writes .......................................... .. 103
`Fast Back-to-Back Transactions .................................................................... ., ................ .. 103
`Decision to Implement Fast Back-to-Back Capability ............ ..'............................... .. 106
`Scenario One: Master Guarantees Lack of Contention ........................................... .. 106
`
`How Collision Avoided On Signals Driven By Master .................................... .. 106
`How Collision Avoided On Signals Driven By Target..................................... .. 107
`How Targets Recognize New Transaction Has Begun..................................... .. 108
`Fast Back-to-Back and Master Abort ................................................................. .. 108
`
`Scenario Two: Targets Guarantee Lack of Contention ............................................ .. 110
`State of REQ# and GNT# During RST# ........................................................................ .. 111
`Pullups On REQ# From Add~In Connectors .................................................................. 112
`Broken Master .................................................................................... ..-. ........................... .. 112
`
`CHAPTER 7: The Commands
`Introduction ...................................................................................................................... .. 113
`
`Interrupt Acknowledge Command ................................................................................ ..114
`Introduction ................................
`.............................................................................. .. 114
`
`.................. 114
`Background...............................................................................................
`Host/PCI Bridge Handling of Interrupt Acknowledge Sequence ......................... .. 115
`PCI Interrupt Acknowledge Transaction ................................................................. .. 116
`Special Cycle Command ................................................................................................. .. 119
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`General ........................................................................................................................ .. 119
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`Special Cycle Generation ........................................................................................... .. 121
`Special Cycle Transaction .................................................................................. ., ...... ..121
`Single-Data Phase Special Cycle Transaction......................................................121
`Multiple Data Phase Special Cycle Transaction................................................ .. 122
`1/0 Read and Write Commands ..................................................................................... .. 124
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`'
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`124
`...........
`.....
`" Accessing Memory.."....'...:.........:..:..'.;.Z:..'..... .;.'..'......;.......... .:; .............
`Reading Memory ........................................................... .._ ........................................... .. 125
`Memory Read Command ................................................................................... .. 125
`Memory Read Line Command .................. .; ............ ..'. ........................................ .. 125
`Memory Read Multiple Command .................................................................... .. 125
`Writing Memory......................................L .................................................................. .. 126
`Memory Write Command .................................................................................. .. 126
`Memory Write and Invalidate Command ......................................................... .. 126
`Problem ......................................................................................................... .. 126
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`Description of Memory Write and Invalidate Command ......................... .. 127
`More Information On Memory Transfers ......................................
`.......................... 127
`Configuration Read and Write-Commands .................................................................. .. 128
`Dual-Address Cycle ........................................................................................................... 128
`Reserved Bus Commands ............................................................................................... .. 128
`
`CHAPTER 8: The Read and Write Transfers
`Some Basic Rules ............................................................................................................. .. 129
`
`Parity.................................................................................................................................. ..13o
`Read Transaction.............................................................................................................. .. 130
`
`Description.................................................................................................................. .. 130
`Treatment of Byte Enables During Read or Write................................................... .. 134
`Byte Enable Settings May Vary from Data Phase to Data Phase ....................... 134
`Data Phase with No Byte Enables Asserted ...................................................... .. 135
`Target with Limited Byte Enable Support ......................................................... .. 136
`Rule for Sampling of Byte Enables ..................................................................... .. 136
`Ignore Byte Enables During Line Read.............................................................. ..136
`Prefetching ........................................................................................................... .. 137
`Performance During Read Transactions .................................................................. .. 137
`Write Transaction ............................................................................................................... 139
`
`Description.................................................................................................................. .. 139
`Performance During Write Transactions ................................................................. .. 144
`Posted-Write Buffer ................................................................................................... .. 146
`General .-................................................................................................................ .. 146
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`Combining............................................................................................................ ..146
`Byte Merging ........-................................................................................................. 147
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`PCI System Architecture
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`Collapsing ............................................................................................................ .. 147
`Cache Line Merging ............................................................................................ .. 147
`Addressing Sequence During Memory Burst .............................................................. .. 148
`Linear and Cacheline Wrap Addressing .................................................................. .. 148
`Target Response to Reserved Setting on AD[1 :0] .................................................... .. 150
`Do Not Merge" Processor I10 Writes into Single Burst.I:....I......'.L.‘...'..'.....;;..;.;..-..;;.:.:...-...150‘
`PCI I/0 Addressing.......................................................................................................... .. 150
`General ........................................................................................................................ .. 150
`
`Situation Resulting in Target-Abort.......................................................................... .. 151
`I/ 0 Address Management ........................................................................................ .. 153
`When IIO Target Doesn't Support Multi-Data Phase Transactions ............'................ 153
`AddressfData Stepping ................................................................................................... .. 154
`Advantages: Diminished Current Drain and Crosstalk............... ..'_......................... .. 154
`Why Targets Don't Latch Address During Stepping Process .................................. 155
`Data Stepping ............................................................................................................. ..155
`How Device Indicates Ability to Use Stepping ......................................................... 155
`Designer May Step Address, Data, PAR (and PAR64), and IDSEL ........................ .. 156
`Continuous and Discrete Stepping .......................................
`.................................. .. 156
`Disadvantages of Stepping ........................................................................................ .. 157
`Preemption While Stepping in Progress ................................................................... .. 157
`Broken Master ............................................................................................................ .. 158
`
`Stepping Example ...................................................................................................... .. 159
`When Not to Use Stepping ................................................................. .._ ..................... .. 161
`Who Must Support Stepping? ................................................................................... .. 161
`Response to Illegal Behavior .......................................................................................... ..161
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`_
`CHAPTER 9: Premature Trans action Termination
`Introduction ...................................................................................................................... .. 163
`Master-Initiated Termination ......................................................................................... .. 163
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`Master Preempted ...................................................................................................... .. 164
`Preemption During Timeslice............................................................................. . , 164
`Timeslice Expiration Followed by Preemption ................................................. .. 165
`Master Abort: Target Doesn't Claim Transaction ................................................... .. 167
`Introduction ......................................................................................................... .. 167
`
`Master Abort on Single Data Phase Transaction .............................................. .. 167
`Master Abort on Multi-Data Phase Transaction ............................................... .. 169
`
`171
`Action Taken by Master in Response to Master Abort
`General .......................................................................................................... .. 1'71
`
`Special Cycle and Configuration Access .................................................... .. 171
`Target-Initiated Termination .....................................................................................
`171
`STOP# Signal .............................................................................................................. .. 171
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`Disconnect"; ................................................................................... ..'. .......................... .. 172
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`Description .................................. ._. ....................................................................... .. 172
`Reasons Target Issues Disconnect ...................................................................... .. 173
`Target Slow to Complete Data Phase.......................................................
`173
`Memory Target Doesn't Understand Addressing Sequence .................... .. 173
`" ‘Transfer Crosses Over Target’s Address'B‘ou‘ndary..L.'....
`.... .I........ .. 173 '
`Burst Memory Transfer Crosses Cache Line Boundary ............................ .. 174
`Type ”A" Disconnect: Initiator Not Ready When Target Says STOP ............. .. 174
`Type ”B" Disconnect: Initiator Ready When Target Says STOP ....................... 175
`Retry (Type C) Disconnect ...............................................................
`....................... .. 178
`Description ........................................................................................................... .. 178
`Reasons Target Issues Retry ............................................................................... .. 179 -
`Memory Target Doesn't Understand Addressing Sequence .............
`....... 179
`Target Very Slow to Complete First Data Phase ........................ ..-. ............. .. 179
`Snoop Hit on Modified Cache Line............................................................. ..179
`Resource Busy............................................................................................... .. 180
`Memory Target Locked ............................................ ..' .................................. .. 180
`Retry Example ........................................................................................_............. .. 180
`Host Bridge Retry Counter ................................................................................. .. 182
`Target Abort ....................................... ..I ..................................................................... .. 182
`Description ........................................................................................................... .. 182
`Reasons Target Issues Target Abort .................................................................. .. 183
`Broken Target.......................L ................................................................
`....... 183
`I/O Addressing Error .................................................................................. .. 183
`Address Phase Parity Error ......................................................................... .. 183
`Master's Response to Target Abort.................................................................... .. 183
`Target Abort Example.....................
`................................................................ 183
`How Soon Does Initiator Attempt to Re-Establish Transfer After
`Retry or Disconnect? ................................................................................................ .. 185
`Target-Initiated Termination Summary ................................................................... .. 185
`
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`CHAPTER 10: Error Detection and Handling
`Introduction to PCI Parity............................................................................................... ..187
`PERR# Signal.................................................................................................................... ..189
`Data Parity ........................................................................................................................ ..12.9
`Data Parity Generation and Checking on Read ....................................................... .. 189
`Introduction ......................................................................................................... .. 189
`
`Example Burst Read ............................................................................................ .. 190
`Data Parity Generation and Checking on Write ........................................................ 193
`Introduction ................