`Patent Owner Response
`U.S. Patent No. 7,777,753
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`Apple, Inc.,
`PETITIONER
`
`v.
`Parthenon Unified Memory Architecture LLC
`PATENT OWNER
`___________
`
`Case IPR No: 2016-01114
`Patent No. 7,777,753
`Title: ELECTRONIC SYSTEM AND METHOD FOR SELECTIVELY ALLOWING ACCESS TO
`A SHARED MEMORY
`____________
`PATENT OWNER RESPONSE
`PURSUANT TO 35 U.S.C. § 316 AND 37 C.F.R. §42.120
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`IPR2016-01114
`Patent Owner Response
`U.S. Patent No. 7,777,753
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`TABLE OF CONTENTS
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`I. INTRODUCTION .................................................................................................... 1
`II. THE `753 PATENT ............................................................................................. 2
`III. THE CHALLENGED CLAIMS ARE PATENTABLE ............................................... 3
`A. Bowes, Datasheet, Artieri, and Christiansen [claim 7] ............................... 3
`1. Datasheet and Artieri do not disclose or render obvious “an arbiter
`included in the memory interface circuit of the decoder.” ............................... 3
`2. Bowes does not disclose “an arbiter included in the memory interface
`circuit of the decoder.” ......................................................................................... 4
`3. Bowes does not render obvious “an arbiter included in the memory
`interface circuit of the decoder.” ......................................................................... 5
`4. Bowes in combination with Christiansen does not render obvious “an
`arbiter included in the memory interface circuit of the decoder.” .................. 7
`B. Bowes, Datasheet, Artieri, Christiansen, and Arimilli [claims 8 and 10] . 8
`C. Bowes, Datasheet, Artieri, Christiansen, and Shanley [claim 9] ............... 9
`D. Bowes, Datasheet, Artieri, Christiansen, and Gove [claim 12] .................. 9
`IV. CONCLUSION .................................................................................................. 10
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`TABLE OF AUTHORITIES
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`
`Cases
`In re Fine,
` 837 F.2d 1076 (Fed. Cir.1988) .................................................................... 8, 9, 10
`
`In re Wilson,
` 424 F.2d 1382 (CCPA 1970) .................................................................................. 3
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`
`
`Rules
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`35 U.S.C. § 103 .......................................................................................................... 1
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`iii
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`TABLE OF EXHIBITS
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`Exhibit Description
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`U.S. Patent No. 7,777,753 (“`753 Patent”)1
`U.S. Patent No. 5,546,547 (“Bowes”)
`U.S. Patent No. 5,787,264 (“Christiansen”)
`Declaration of Mitchell A. Thornton (Thornton Decl.”)
`Deposition testimony of Robert Colwell, Ph.D dated February 27,
`2017 (“Colwell Depo.”).
`U.S. Patent No. 5,584,038 (“Papworth”)
`
`
`
`Exhibit
`No.
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`1001
`1005
`1011
`2009
`2010
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`2011
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`1 Ex. 1001, 1005, and 1011 are already of record and not attached to this Response.
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`iv
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`I.
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`INTRODUCTION
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`IPR2016-01114
`Patent Owner Response
`U.S. Patent No. 7,777,753
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`The patent owner Parthenon Unified Memory Architecture LLC (“Patent
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`Owner”) hereby submits the following response to the Petition for Inter Partes
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`review (“Petition”) filed by Apple, Inc. (“Petitioner”) regarding certain claims of
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`U.S. Patent No. 7,777,753 (“`753 Patent”) filed on May 31, 2016 and Decision
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`Granting Institution of Inter Partes Review 37 C.F.R. 42.108 issued on December
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`7, 2016 (“Institution Decision”).
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`The Board instituted an Inter Partes review with respect to the following
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`proposed grounds (collectively “Instituted Grounds”):
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`1. Obviousness of claims 1 and 2 under 35 U.S.C. § 103 over Bowes,
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`Datasheet, Artieri, and Arimilli;
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`2. Obviousness of claim 4 under 35 U.S.C. § 103 over Bowes, Datasheet,
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`Artieri, Arimilli, and Shanley;
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`3. Obviousness of claim 7 under 35 U.S.C. § 103 over Bowes, Datasheet,
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`Artieri, and Christiansen;
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`4. Obviousness of claims 8 and 10 under 35 U.S.C. § 103 over Bowes,
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`Datasheet, Artieri, Christiansen, and Arimilli;
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`5. Obviousness of claim 9 under 35 U.S.C. § 103 over Bowes, Datasheet,
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`Artieri, Christiansen, and Shanley; and
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`6. Obviousness of claim 12 under 35 U.S.C. § 103 over Bowes, Datasheet,
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`U.S. Patent No. 7,777,753
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`Artieri, Christiansen, and Gove.
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`The Board held that claims 1–4 are unpatentable in IPR2015-01501.
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`Therefore, this response is directed to an analysis of grounds 3–6 of the above
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`Instituted Grounds.
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`For
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`the reasons discussed below, Bowes, Datasheet, Artieri, and
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`Christiansen do not render claim 7 obvious. Because they depend on claim 7,
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`claims 8–10 and 12 are allowable for at least the same reasons. The discussion
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`below first discusses the `753 Patent and claims. It then rebuts the adopted grounds
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`of unpatentability on the merits.
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`II. THE `753 PATENT
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`The `753 Patent is generally directed to sharing a memory interface between
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`a video decoder and another device contained in an electronic system. `753 Pat.
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`[Ex. 1001], Abstract; independent claims 1 and 7. Accordingly, the electronic
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`system includes a bus and a main memory coupled to the bus. Id. at claim 1. The
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`main memory has stored therein data corresponding to video images to be decoded.
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`Id. A video circuit is coupled to the bus and receives data from the main memory
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`corresponding to a video image to be decoded. Id. The video circuit outputs
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`decoded video data corresponding to the current video image to be displayed on a
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`display device. Id. The current video image to be displayed is stored in the main
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`memory. Id. In addition to the video circuit, the electronic system includes another
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`device such as, for example, a processor that is coupled to the main memory. Id.
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`An arbiter circuit is coupled to the processor and the video circuit and is
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`configured to receive requests for access to the main memory from the video
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`circuit and the processor and control access to the main memory. Id.
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`III. THE CHALLENGED CLAIMS ARE PATENTABLE
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`A. Bowes, Datasheet, Artieri, and Christiansen [claim 7]
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`Independent claim 7 is not invalid as obvious in view of Bowes, Datasheet,
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`Artieri, and Christiansen because Bowes, Datasheet, Artieri, and Christiansen,
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`alone or in combination, fail to disclose “an arbiter included in the memory
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`interface circuit of the decoder.” See, e.g., In re Wilson, 424 F.2d 1382 1385
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`(CCPA 1970) (“All words in a claim must be considered in judging the
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`patentability of that claim against the prior art”).
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`1. Datasheet and Artieri do not disclose or render obvious “an
`arbiter included in the memory interface circuit of the
`decoder.”
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`Petitioner does not rely on Datasheet or Artieri to disclose or render obvious
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`“an arbiter included in the memory interface circuit of the decoder.” [See Petition
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`at 55–57.] Indeed, Dr. Thornton confirms that Datasheet and Artieri do not
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`disclose or render obvious this limitation. [Ex. 2009, Thornton Decl. at ¶ 35.]
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`Accordingly, Datasheet and Artieri do not disclose or render obvious this
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`limitation.
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`2. Bowes does not disclose “an arbiter included in the memory
`interface circuit of the decoder.”
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`Petitioner argues that Bowes discloses this limitation. [See Petition at 55–
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`56.] Petitioner is incorrect. A POSA would understand that Petitioner’s
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`identification of the decoder’s “memory interface circuit” improperly includes
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`additional elements. [Ex. 2009, Thornton Decl. at ¶ 36.] Specifically, Petitioner
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`alleges that the “memory interface circuit” of DSP 20 in Bowes includes the
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`arbitration logic located in MCA 200. [Petition at 55–56.] From this premise,
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`Petitioner concludes that DSP 20’s “memory interface circuit” includes an arbiter
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`as required by the claim. [Id. at 56–57.] However, a POSA would understand that
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`the “memory interface circuit” of DSP 20 does not include anything in MCA 200
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`because MCA 200 is not part of DSP 20’s path to the memory. [See Ex. 2009,
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`Thornton Decl. at ¶ 36; Ex. 2010, Colwell Depo. at 26:1–10 (identifying I/O
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`drivers as part of the “memory interface circuit” because “they’re in the path”);
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`34:9–13 (identifying bus interface as the “memory interface” because “[t]hat is the
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`path by which microprocessor 100 reaches memory 160”).] In fact, at his
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`deposition, Petitioner’s expert agreed that the “memory interface circuit” of DSP
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`20 does not include anything in MCA 200:
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`[Ex. 2010, Colwell Depo. at 42:11–16; cf. id. at 41:4–7 (explaining the same story
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`regarding CPU 10’s “memory interface circuit,” which also does not include
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`anything in MCA 200).] Accordingly, the “memory interface circuit” of DSP 20
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`does not include the arbitration logic located in MCA 200, and Bowes fails to
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`disclose “an arbiter included in the memory interface circuit of the decoder.”
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`3. Bowes does not render obvious “an arbiter included in the
`memory interface circuit of the decoder.”
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`Petitioner argues that Bowes renders this limitation obvious because
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`“physical integration of arbiter circuits with Bowes’ DSP . . . was one of a handful
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`of obvious design choices for a POSITA.” [Petition at 57.] This is incorrect. A
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`POSA would not co-locate the arbiter with DSP 20. [See Ex. 2009, Thornton Decl.
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`at ¶ 37.] A POSA would understand that the DSP of Bowes is bandwidth limited,
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`and the alleged use of the Bowes DSP for video decoding requires that its
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`resources—including its bus interface and processing power—be reserved
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`exclusively for data and control traffic dedicated to the video decoding process.
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`[See id.; Ex. 1005 at 1:51–53 (“[A] DSP requires a large amount of bandwidth to
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`memory for processing the sheer volume of data required to effectuate real-time
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`computing.”); 2:25–26 (“the high bandwidth required for real-time processing by a
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`DSP”); 3:21–23 (“The arbitration scheme is tuned to maximize accessibility of the
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`memory bus to the DSP which has by far the greatest bandwidth requirements.”);
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`6:35–38 (“Many of these functions are real-time operation and require a
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`tremendous amount of the memory bus bandwidth between the DSP and the
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`DRAM of the main memory subsystem 14.”); 7:31–32 (“In addition to the DSP’s
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`huge requirement for bandwidth on the memory bus . . . .”); see also Ex. 2010,
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`Colwell Depo. at 58:23–59:18 (explaining that “the logic required to implement
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`the arbitration function would take up some of the chip’s resources” when asked
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`about relocating the arbiter in Christiansen).] Indeed, the Bowes system is
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`“optimized” to support the DSP and make sure that it has the resources it needs.
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`[See Ex. 1005 at 8:40–42 (“Because the DSP has the largest bus bandwidth
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`requirement, the system is optimized to meet its need and support its real-time
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`operations.”).] A POSA looking to “optimize” the Bowes system as its inventor
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`intended would therefore not be motivated to include circuitry with the DSP for the
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`purpose of servicing other devices in the system, as such inclusion would cause the
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`DSP’s limited bus bandwidth and processing power to be divided between video
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`decoding and services unrelated to video decoding. [See Ex. 2009, Thornton Decl.
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`at ¶ 37; Ex. 1005 at 7:64–8:3 (explaining that the Bowes bus masters propagate bus
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`request signals to the arbiter over memory bus 110)]. Accordingly, a POSA would
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`not be motivated to co-locate the arbitration logic of MCA 200 with the DSP, and
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`Bowes fails to render obvious “an arbiter included in the memory interface circuit
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`of the decoder.” [Ex. 2009, Thornton Decl. at ¶ 37.]
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`4. Bowes in combination with Christiansen does not render
`obvious “an arbiter included in the memory interface circuit of
`the decoder.”
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`Petitioner argues that Bowes in combination with Christiansen renders this
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`limitation obvious because “Christiansen explicitly teaches that an arbiter can be
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`located anywhere in the system. . . . including co-locating the arbitration logic with
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`the DSP . . . .” [Petition at 57.] This is incorrect. As an initial matter,
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`Christiansen never explicitly discloses co-locating arbitration logic with the DSP.
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`Instead, Christiansen broadly states that “the arbiter 22 can be located anywhere
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`throughout the computer system.” [Ex. 1011 at 5:16–19.] A POSA would not take
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`Christiansen’s statement at face value because a POSA understands that,
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`depending on the system, certain locations are unsuitable for the arbiter. [See Ex.
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`2009, Thornton Decl. at ¶ 39; Ex. 2010, Colwell Depo. at 54:18–55:25 (explaining
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`that the arbiter must be placed somewhere electrically reasonable and that
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`Christiansen is not “literally trying to say in a text that you can stick it out, you
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`know, in a power supply”).] Even if a POSA would interpret Christiansen’s
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`statement to mean that one could always choose to place the arbiter literally
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`anywhere in the system, a POSA would not co-locate the arbitration logic with the
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`DSP in Bowes because, as explained earlier and by Bowes himself, doing so would
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`run counter to optimizing the system. [Ex. 2009, Thornton Decl. at ¶ 39.]
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`B. Bowes, Datasheet, Artieri, Christiansen, and Arimilli [claims 8
`and 10]
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`The Petition alleges that claims 8 and 10 are obvious in view of Bowes,
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`Datasheet, Artieri, Christiansen, and Arimilli. Claims 8 and 10 depend on
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`independent claim 7. As discussed in Section III.A., supra, claim 7 is not invalid
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`as obvious in view of Bowes, Datasheet, Artieri, and Christiansen. The Petition
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`relies on Arimilli only for its alleged disclosure of certain limitations in claims 8
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`and 10. [Petition at 60–65.] Therefore, independent claim 7 is also not obvious in
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`view of the proposed combination of Bowes, Datasheet, Artieri, Christiansen, and
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`Arimilli. Dependent claims 8 and 10 are allowable at least for the same reasons.
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`In re Fine, 837 F.2d 1071, 1076 (Fed. Cir. 1988) (“Dependent claims are
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`nonobvious under § 103 if the independent claims from which they depend are
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`nonobvious”).
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`C. Bowes, Datasheet, Artieri, Christiansen, and Shanley [claim 9]
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`The Petition alleges that claim 9 is obvious in view of Bowes, Datasheet,
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`Artieri, Christiansen, and Shanley. Claim 9 depends on independent claim 7. As
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`discussed in Section III.A., supra, claim 7 is not invalid as obvious in view of
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`Bowes, Datasheet, Artieri, and Christiansen. The Petition relies on Shanley only
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`for its alleged disclosure of certain limitations in claim 9. [Petition at 65–66.]
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`Therefore, independent claim 7 is also not obvious in view of the proposed
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`combination of Bowes, Datasheet, Artieri, Christiansen, and Shanley. Dependent
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`claim 9 is allowable at least for the same reasons. In re Fine, 837 F.2d 1071, 1076
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`(Fed. Cir. 1988) (“Dependent claims are nonobvious under § 103 if the
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`independent claims from which they depend are nonobvious”).
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`D. Bowes, Datasheet, Artieri, Christiansen, and Gove [claim 12]
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`The Petition alleges that claim 12 is obvious in view of Bowes, Datasheet,
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`Artieri, Christiansen, and Gove. Claim 12 depends on independent claim 7. As
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`discussed in Section III.A., supra, claim 7 is not invalid as obvious in view of
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`Bowes, Datasheet, Artieri, and Christiansen. The Petition relies on Gove only for
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`its alleged disclosure of certain limitations in claim 12. [Petition at 66–69.]
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`Therefore, independent claim 7 is also not obvious in view of the proposed
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`combination of Bowes, Datasheet, Artieri, Christiansen, and Gove. Dependent
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`claim 9 is allowable at least for the same reasons. In re Fine, 837 F.2d 1071, 1076
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`(Fed. Cir. 1988) (“Dependent claims are nonobvious under § 103 if the
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`independent claims from which they depend are nonobvious”).
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`IV. CONCLUSION
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`For the foregoing reasons, the Board should find that each of the claims
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`under review is patentable.
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`By: /s/ Masood Anjom
`Masood Anjom, Lead Counsel
`Reg. No. 62,167
`Alisa Lipski, Back-Up Counsel
`Reg. No. 55,386
`Attorney for Patent Owner
`Parthenon Unified Memory
`Architecture, LLC
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`AHMAD, ZAVITSANOS, ANAIPAKOS,
`ALAVI &MENSING, P.C.
`1221 McKinney Street, Suite 2500
`Houston, TX 77010
`Telephone: 713-655-1101
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`Dated: March 9, 2017
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`IPR2016-01114
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`U.S. Patent No. 7,777,753
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`CERTIFICATE OF SERVICE
`I hereby certify that the Patent Owner’s Response Under 35 U.S.C. § 316
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`AND 37 C.F.R. §42.120 was served on this Thursday, March 9, 2016 by electronic
`mail to the following:
`Lead Counsel for Apple Inc.
`David W. O’Brien, Reg. No. 40,107
`HAYNES AND BOONE, LLP
`2323 Victory Avenue, Suite 700
`Dallas, TX 75219
`Email: andy.ehmke.ipr@haynesboone.com
`
`Back-up Counsel for Apple Inc.
`Andrew S. Ehmke, Reg. No. 50,271
`Michael S. Parsons, Reg. No. 58,767
`HAYNES AND BOONE, LLP
`2323 Victory Avenue, Suite 700
`Dallas, TX 75219
`david.obrien.ipr@haynesboone.com
`michael.parsons.ipr@haynesboone.com
`
`David L. Alberti, Reg. No. 43,465
`dalberti@feinday.com
`Yakov Zolotorev
`yzolotorev@feinday.com
`FEINBERG DAY ALBERTI &
`THOMPSON LLP
`1600 El Camino Real, Suite 280
`Menlo Park, CA 94025
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`Dated: March 9, 2017
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`By: /s/ Masood Anjom________
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`Masood Anjom, Lead Counsel
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`Reg. No. 62,167
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`Alisa Lipski, Back-Up Counsel
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`Reg. No. 55,386
`Attorney for Patent Owner
`Parthenon Unified Memory
`Architecture, LLC
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`AHMAD, ZAVITSANOS, ANAIPAKOS,
`ALAVI &MENSING, P.C.
`1221 McKinney Street, Suite 2500
`Houston, TX 77010
`Telephone: 713-655-1101
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