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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`Apple, Inc.,
`Petitioner,
`
`v.
`
`Parthenon Unified Memory Architecture LLC,
`Patent Owner.
`____________
`
`Case IPR2016-01114
`Patent 7,777,753
`____________
`
`Declaration of Mitchell A. Thornton, Ph. D., P.E.
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`I.
`
`Introduction
`1.
`I am over the age of eighteen (18) and otherwise competent to make
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`this declaration.
`
`2. My name is Mitchell Aaron Thornton. I am offering this declaration
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`in the matter listed above on behalf of Parthenon Unified Memory Architecture
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`LLC and at the behest of their attorneys Ahmad, Zavitsanos, Anaipakos, Alavi &
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`Mensing P.C. I am being compensated at my usual rate and my compensation is
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`not dependent on any opinions that I may take in this matter, any testimony, or any
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`intermediate or final resolution in the matter.
`
`3.
`
`I understand that the Board has issued an institution Decision in the
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`above-captioned IPR concluding that the Petitioner has established a reasonable
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`likelihood of success with respect to the following grounds (collectively “Instituted
`
`Grounds”):
`
`a. Obviousness of claims 1 and 2 over Bowes, Datasheet, Artieri, and
`
`Arimilli;
`
`b. Obviousness of claim 4 over Bowes, Datasheet, Artieri, Arimilli, and
`
`Shanley;
`
`c. Obviousness of claim 7 over Bowes, Datasheet, Artieri, and
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`Christiansen;
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`1
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`d. Obviousness of claims 8 and 10 over Bowes, Datasheet, Artieri,
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`Christiansen, and Arimilli;
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`e. Obviousness of claim 9 over Bowes, Datasheet, Artieri, Christiansen,
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`and Shanley; and
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`f. Obviousness of claim 12 over Bowes, Datasheet, Artieri, Christiansen,
`
`and Gove.
`
`4.
`
`I understand that the Board held that claims 1–4 are unpatentable in
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`IPR2015-01501. Therefore, this declaration is directed to an analysis of grounds
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`c–f of the above Instituted Grounds.
`
`II. My Background and Qualifications
`
`5.
`
`I earned a Bachelor of Science degree in Electrical Engineering from
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`Oklahoma State University in 1985. In 1990, I earned a Masters of Science degree
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`in Electrical Engineering from the University of Texas at Arlington. In 1993, I
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`earned a Masters of Science degree in Computer Science from Southern Methodist
`
`University. I earned a Ph.D. in Computer Engineering from Southern Methodist
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`University in 1995. I am a Licensed Professional Engineer in the states of Texas,
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`Mississippi, and Arkansas. I also hold a Commercial General Radiotelephone
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`Operator License (GROL) with Ship Radar endorsement issued by the Federal
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`Communications Commission (FCC).
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`2
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`6.
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`I am currently the Acting Chair of the Department of Computer
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`Science and Engineering at Southern Methodist University. My academic rank is
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`Cecil H. Green Chair of Engineering and Professor in the Department of Computer
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`Science and Engineering and in the Department of Electrical Engineering at
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`Southern Methodist University. Prior to 2002, I served as a faculty member at
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`Mississippi State University in the Department of Electrical and Computer
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`Engineering from 1999 through 2002. I served as a faculty member at the
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`University of Arkansas from 1995 through 1999 in the Department of Computer
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`Systems Engineering. In my university positions, my responsibilities are research,
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`teaching, and providing service in my profession. My teaching and research area of
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`expertise is generally in the area of computer engineering where I specialize in
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`hardware design for information processing systems.
`
`7.
`
`In addition to my academic rank of professor, I am also the Research
`
`Director of the Darwin Deason Institute for Cyber Security at Southern Methodist
`
`University. The Institute mission is to advance the science, policy, application and
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`education of cyber security through basic and problem-driven, interdisciplinary
`
`research. As Research Director, I am responsible for the coordination and oversight
`
`of all research projects within the auspices of this multi-million dollar endowed
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`research Institute that is comprised of several principal investigators and their
`
`associated research teams. In this role, I am routinely involved with several
`
`3
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`different state-of-the-art projects regarding the technical aspects of information
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`processing system processes, methods, software, and hardware.
`
`8.
`
`Prior to my academic career, I was employed in the commercial sector
`
`as an engineer. I was employed full-time at E-Systems, Inc. (now L3
`
`Communications) in Greenville, Texas from 1986 through 1991 and resigned from
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`my position as Senior Electronic Systems Engineer in 1991 to pursue full-time
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`graduate studies in Computer Science and Computer Engineering. My duties at E-
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`Systems involved the design, analysis, implementation, and test of a variety of
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`different electronic systems including various information processing systems
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`centered around signal processing, data transmission and processing, and
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`communications systems. The communications systems I was involved with
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`processed a variety of different types of signals including data, audio, and video
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`systems. These systems were comprised of components such as receivers,
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`transmitters, computers, and special purpose circuitry.
`
`9.
`
`During the time I was in graduate school pursuing the Ph.D. degree, I
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`also worked part-time and full-time during the summer of 1992 at a commercial
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`integrated circuit (IC) design company named the Cyrix Corporation. At Cyrix, I
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`was a member of a design team that ultimately produced a microprocessor that is
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`compatible with the Intel Pentium. My duties included the design of the bus
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`controller and memory interface circuitry for this IC.
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`4
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`10. My practice and research covers a range of topics centered around
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`hardware design and analysis including secure circuit and embedded system
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`design, electronic design automation (EDA) methods, and algorithms for quantum,
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`classical digital systems, and large systems design. I have also maintained an
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`independent professional engineering practice since 1993 as a sole proprietor that
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`is a registered engineering firm in the state of Texas.
`
`11.
`
`I am a named inventor on four (4) issued patents and two (2) patent
`
`applications under consideration at the USPTO. I have authored or coauthored over
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`200 scholarly publications in the fields of electrical engineering and computer
`
`science.
`
`12. My curriculum vitae and testimony list are included in Appendix A to
`
`this declaration, which more fully sets forth my qualifications.
`
`III. Documents Considered
`
`13.
`
`In addition to my knowledge and experience, I have reviewed and
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`relied upon the following materials in performing my analysis:
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`• The `753 Patent (including the publications incorporated therein) and its
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`file history;
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`• Petition for Inter Partes Review of U.S. Patent No. 7,777,753 including
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`the exhibits [IPR2016-01114];
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`• Patent Owner’s Preliminary Response in IPR2016-01114;
`
`5
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`• Decision on Institution in IPR2016-01114;
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`• Declaration of Robert Colwell, Ph.D [Ex. 1003] (“Colwell Decl.”);
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`• U.S. Patent No. 5,546,547 to Bowes [Ex. 1005] (“Bowes”);
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`• AT&T DSP3210 Digital Signal Processor The Multimedia Solution,
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`Data Sheet, AT&T Microelectronics, March 1993
`
`[Ex. 1006]
`
`(“Datasheet”);
`
`• Published European Patent Application EP 0626653 A1 naming Artieri,
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`together with English translation and affidavit attesting to the accuracy
`
`of the translation [Ex. 1007] (“Artieri”);
`
`• U.S. Patent No. 5,787,264
`
`to Christiansen et al. [Ex. 1011]
`
`(“Christiansen”);
`
`• U.S. Patent No. 6,029,217 to Arimilli et al. [Ex. 1008] (“Arimilli”);
`
`• T. Shanley et al., “PCI System Architecture,” Addison-Wedley Publ’g
`
`Co. (3rd ed. Feb. 1995) [Ex. 1010] (“Shanley”);
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`• R. Gove, “The MVP: A Highly-Integrated Video Compression Chip”,
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`IEEE 1994 [Ex. 1009] (“Gove”);
`
`• U.S. Patent No. 5,584,038 to Papworth et al. (“Papworth”);
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`• Deposition testimony of Robert Colwell, Ph.D dated February 27, 2017
`
`(“Colwell Depo.”).
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`IV. Summary of Opinions
`
`6
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`14. As detailed below, it is my opinion that the challenged independent
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`claim is not obvious in view of Bowes, Datasheet, Artieri, and Christiansen and
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`that the challenged dependent claims are also not obvious for at least the same
`
`reasons.
`
`V. Legal Standards
`
`15.
`
`I am not an attorney or patent agent, and thus, I have relied upon
`
`certain legal factors that have been explained to me. Some of these, which form the
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`legal framework for the opinions I am providing, are summarized below.
`
`16.
`
`I understand that claims are to be interpreted from the perspective of
`
`one of ordinary skill in the art. I understand that in determining the level of
`
`ordinary skill in the art, the following factors may be considered: (1) the
`
`educational level of the inventor; (2) type of problems encountered in the art; (3)
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`prior art solutions to those problems; (4) rapidity with which innovations are made;
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`(5) sophistication of the technology; and (6) educational level of active workers in
`
`the field.
`
`17.
`
`I understand from reading the Board’s decision that in this inter partes
`
`review, claim terms are to be given their broadest reasonable construction in light
`
`of the patent specification. I also understand that claim terms are presumed to be
`
`given their ordinary and customary meaning as would be understood by one of
`
`ordinary skill in the art. Furthermore, I understand that an inventor may provide a
`
`7
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`contrary definition of a term in the specification, if it is done with reasonable
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`clarity, deliberateness, and precision. I also understand that care must be taken not
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`to read a particular embodiment appearing in the specification into the claim if the
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`claim language is broader than the embodiment.
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`18.
`
`I understand that a claim may be invalid as anticipated or as being
`
`obvious. I understand that anticipation is not at issue in this IPR and therefore, my
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`analysis is focused on the obviousness issue.
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`19.
`
`I understand that the obviousness standard is defined in the patent
`
`statute (35 U.S.C. § 103(a)). I also understand that a claim is not patentable and is
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`obvious if the differences between a claim and the prior art are such that the
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`claimed subject matter as a whole would have been obvious to a person having
`
`ordinary skill in the art at the time the invention was made. I understand that this
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`inquiry involves examination of number of factors including: (1) determining the
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`scope and content of the prior art; (2) ascertaining the differences between the
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`claim and the prior art; (3) resolving the level of ordinary skill in the prior art; and
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`(4) considering any secondary or objective evidence of non-obviousness. I
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`understand that secondary or objective evidence of non-obviousness include
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`factors such as commercial success, long felt need for the invention, and failure of
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`others.
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`8
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`20.
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`I understand that an obviousness analysis involves comparing a claim
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`to the prior art to determine whether the claimed invention would have been
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`obvious to a Person of Ordinary Skill in the Art (“POSA”) in view of the prior art,
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`and in light of the general knowledge in the art. I also understand when a POSA
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`would have reached the claimed invention through routine experimentation, the
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`invention may be deemed obvious.
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`21.
`
`I also understand that obviousness can be established by combining or
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`modifying the teachings of the prior art to achieve the claimed invention. It is also
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`my understanding that where this is a reason to modify or combine the prior art to
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`achieve the claimed invention, there must also be a reasonable expectation of
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`success in so doing. I understand that the reason to combine prior art references
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`can come from a variety of sources, not just the prior art itself or the specific
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`problem the patentee was trying to solve. And I understand that the references
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`themselves need not provide a specific hint or suggestion of the alteration needed
`
`to arrive at the claimed invention; the analysis may include recourse to logic,
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`judgment, and common sense available to a person of ordinary skill that does not
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`necessarily require explication in any reference. Finally, it is my understanding that
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`obviousness can be established by choosing from a finite number of identified,
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`predictable solutions, with a reasonable expectation of success.
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`9
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`22.
`
`I further understand that a patent composed of several elements is not
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`proved obvious merely by demonstrating that each of its elements was,
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`independently, known in the prior art. I further understand that a showing of a
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`suggestion, teaching, or motivation to combine the prior art references is an
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`essential evidentiary component of an obviousness conclusion. I further understand
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`that a claim is not obvious if the references relied upon in a proposed combination
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`teach away from the claimed combination in a way that would deter any
`
`investigation into such a combination. For instance, it is my understanding that a
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`reference teaches away from a combination when using that combination would
`
`produce an inoperative result.
`
`VI. Level of Ordinary Skill in the Art
`23.
`In formulating my opinions, I have also considered the viewpoint of a
`
`person of ordinary skill in the art (“POSA”) at the time of the filing of the `753
`
`Patent.
`
`24.
`
`I understand that Dr. Colwell has opined that a person of ordinary
`
`skill in the art as of the effective filing date of the `753 Patent would have held a
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`Bachelor of Science degree (or higher degree) in an academic area emphasizing
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`electrical or computer engineering and had three years of relevant industry
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`experience. [Ex 1003, at ¶ 20.]
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`10
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`25. Based upon my knowledge of this field, I conclude that a person of
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`ordinary skill in this art at the time of the filing of the `753 Patent, and for that
`
`matter, at all subsequent times through the present, would have held at least an
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`accredited Bachelor’s degree in electrical engineering, computer engineering, or an
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`equivalent degree in a related discipline from an accredited institution of higher
`
`learning and at least two to three years’ experience in signal and/or image
`
`processing, computer architecture at both the systems and micro-architecture level.
`
`In lieu of two to three years of experience, a person of ordinary skill in the art may
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`hold, in addition to a Bachelor’s degree as described above, a Master’s or other
`
`graduate degree in electrical or computer engineering with a focus in computer
`
`architecture and signal and/or image processing with one year of relevant
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`experience.
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`26. My analysis was performed from the perspective of such a person. If
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`I were to apply the level of ordinary skill as proffered by Dr. Colwell in his
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`declaration, my analysis and conclusions would remain unchanged.
`
`VII. State of the Prior Art and the `753 Patent
`
`27. The computer memory storage requirements of a digital representation
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`of an uncompressed image is dependent on its resolution and color depth. Video
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`files are comprised of sequences of images that are further enhanced with a
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`corresponding audio track to accompany them. As a result, a video file quickly
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`11
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`becomes large in size. The transmission of uncompressed video files is
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`prohibitively expensive.
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`28. Accordingly, video files are typically compressed at a transmitting
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`device. The compressed file is then transmitted to a receiving device where it is
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`decompressed. To that end, an encoder at the transmitter compresses the video file
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`and a decoder decompresses the file received at the receiver in order to retrieve the
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`original video and audio data. In order to ensure compatibility between devices, a
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`number of standards for encoding and decoding video files were developed. One of
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`those standards was developed by the Motion Picture Expert Group (“MPEG”) and
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`has been adapted as a standard for the communication of video.
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`29. Typically, a decoder requires its own dedicated memory. For instance,
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`traditional MPEG decoders require a 2 Mbyte dedicated memory which is utilized
`
`during the decoding process. This dedicated memory is necessary to allow the
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`decoder to decode images in real-time without dropping frames which would result
`
`in a deterioration of the video quality at the receiver. This prior art implementation
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`is shown, for example, in Figure 1c of the `753 Patent.
`
`30.
`
` The `753 Patent discloses an improved system where the decoder and
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`another device (e.g., a microprocessor) share the main system memory. This
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`improved configuration eliminates the need for a dedicated decoder memory and
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`results in a more efficient utilization of main system memory by ensuring that
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`12
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`memory resources not used by the decoder remain available to other system
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`components.
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`VIII. Claim Construction
`
`31.
`
`I understand that the Board has construed the term “decoder” to mean
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`“hardware and/or software that translates data streams into video or audio
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`information.” (Institution Decision, Paper 7, at 12).
`
`32.
`
`I understand that the Board has construed the term “video circuit” to
`
`mean “hardware that translates data streams into video information.” (Institution
`
`Decision, Paper 7, at 13).
`
`33.
`
`I understand that the Board has construed the term “memory interface
`
`circuit” to mean “hardware, including signaling paths to or from a competing
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`device or an arbiter, to coordinate communication via a memory bus.” (Institution
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`Decision, Paper 7, at 13).
`
`34.
`
`I have used the Board’s constructions of the terms “decoder,” “video
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`circuit,” and “memory interface circuit” in performing my analysis. I have used
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`the plain and ordinary meaning of the remaining claim terms when performing my
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`analysis.
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`IX. Analysis of Instituted Grounds
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`A. Claim 7
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`13
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`1) Bowes, Datasheet, Artieri, and Christiansen fail to disclose or render
`obvious “an arbiter included in the memory interface circuit of the
`decoder”
`
`35. Dr. Colwell does not contend that Artieri or Datasheet disclose or
`
`render obvious this limitation. I agree that Artieri and Datasheet do not disclose or
`
`render obvious this limitation.
`
`36. Dr. Colwell contends that Bowes discloses this limitation. [Ex. 1003
`
`at ¶¶ 141–44.] I disagree. A POSA would understand that Dr. Colwell’s
`
`identification of the decoder’s “memory interface circuit” improperly includes
`
`additional elements. Specifically, Dr. Colwell alleges that the “memory interface
`
`circuit” of DSP 20 in Bowes includes the arbitration logic located in MCA 200.
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`[Ex. 1003 at ¶ 144.] From this premise, Dr. Colwell concludes that DSP 20’s
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`“memory interface circuit” includes an arbiter as required by the claim. [Id.]
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`However, a POSA would understand that the “memory interface circuit” of DSP
`
`20 does not include anything in MCA 200 because MCA 200 is not part of DSP
`
`20’s path to the memory. [See also Colwell Depo. at 26:1–10 (identifying I/O
`
`drivers as part of the “memory interface circuit” because “they’re in the path”);
`
`34:9–13 (identifying bus interface as the “memory interface” because “[t]hat is the
`
`path by which microprocessor 100 reaches memory 160”).] Indeed, at his
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`deposition, Dr. Colwell agreed that the “memory interface circuit” of DSP 20 does
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`not include anything in MCA 200:
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`
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`[Id. at 42:11–16; cf. id. at 41:4–7 (explaining the same story regarding CPU 10’s
`
`“memory interface circuit,” which also does not include anything in MCA 200).]
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`Accordingly, the “memory interface circuit” of DSP 20 does not include the
`
`arbitration logic located in MCA 200, and Bowes fails to disclose “an arbiter
`
`included in the memory interface circuit of the decoder.”
`
`37. Dr. Colwell contends that Bowes renders this limitation obvious. [Ex.
`
`1003 at ¶ 145.] I disagree. A POSA would not co-locate the arbiter with DSP 20
`
`to “decrease the number of disparate chips present on the memory bus,” as Dr.
`
`Colwell suggests. [Id.] A POSA would understand that the DSP of Bowes is
`
`bandwidth limited, and the alleged use of the Bowes DSP for video decoding
`
`requires that its resources—including its bus interface and processing power—be
`
`reserved exclusively for data and control traffic dedicated to the video decoding
`
`process. [See Ex. 1005 at 1:51–53 (“[A] DSP requires a large amount of
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`bandwidth to memory for processing the sheer volume of data required to
`
`effectuate real-time computing.”); 2:25–26 (“the high bandwidth required for real-
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`time processing by a DSP”); 3:21–23 (“The arbitration scheme is tuned to
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`maximize accessibility of the memory bus to the DSP which has by far the greatest
`
`bandwidth requirements.”); 6:35–38 (“Many of these functions are real-time
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`operation and require a tremendous amount of the memory bus bandwidth between
`
`the DSP and the DRAM of the main memory subsystem 14.”); 7:31–32 (“In
`
`addition to the DSP’s huge requirement for bandwidth on the memory bus . . . .”);
`
`see also Colwell Depo. at 58:23–59:18 (explaining that “the logic required to
`
`implement the arbitration function would take up some of the chip’s resources”
`
`when asked about relocating the arbiter in Christiansen).] Indeed, the Bowes
`
`system is “optimized” to support the DSP and make sure that it has the resources it
`
`needs. [See Ex. 1005 at 8:40–42 (“Because the DSP has the largest bus bandwidth
`
`requirement, the system is optimized to meet its need and support its real-time
`
`operations.”).] A POSA looking to “optimize” the Bowes system as its inventor
`
`intended would therefore not be motivated to include circuitry with the DSP for the
`
`purpose of servicing other devices in the system, as such inclusion would cause the
`
`DSP’s limited bus bandwidth and processing power to be divided between video
`
`decoding and services unrelated to video decoding. [See Ex. 1005 at 7:64–8:3
`
`(explaining that the Bowes bus masters propagate bus request signals to the arbiter
`
`over memory bus 110)]. Accordingly, a POSA would not be motivated to co-
`
`locate the arbitration logic of MCA 200 with the DSP.
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`38.
`
`I understand that Dr. Colwell contends that the Bowes bus masters
`
`send bus request signals and receive bus grant signals over signal lines separate
`
`from memory bus 110. [Ex. 1003 at ¶ 141.] I disagree. As discussed earlier,
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`Bowes explicitly states that the bus request signals are propagated over memory
`
`bus 110. [See Ex. 1005 at 7:64–8:3.] Additionally, Dr. Colwell relies on Figure 4
`
`to show the presence of these separate physical signal lines. I disagree that the
`
`lines that Dr. Colwell points to correspond to separate physical signal lines. As
`
`described by Bowes himself, these signal lines are part of memory bus 110. I also
`
`note that Figure 4 is a logical representation of the arbiter rather than a physical
`
`representation. [Ex. 1005 at 4:4–6.] Accordingly, a POSA would not conclude
`
`that something illustrated in Figure 4 must physically exist. [See also Colwell
`
`Depo. at 19:10–20:17 (providing example of an illustration in a logical
`
`representation that has “no physical reality corresponding to that”).
`
`39. Dr. Colwell further contends that a POSA would combine Bowes with
`
`Christiansen to consider “co-locating the arbitration logic with the DSP.” [Ex.
`
`1003 at ¶ 146.] I disagree. As an initial matter, Christiansen never explicitly
`
`discloses co-locating arbitration logic with the DSP. Instead, Christiansen broadly
`
`states that “the arbiter 22 can be located anywhere throughout the computer
`
`system.” [Ex. 1011 at 5:16–19.] A POSA would not take Christiansen’s statement
`
`at face value because a POSA understands that, depending on the system, certain
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`locations are unsuitable for the arbiter. [See also Colwell Depo. at 54:18–55:25
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`(explaining that the arbiter must be placed somewhere electrically reasonable and
`
`that Christiansen is not “literally trying to say in a text that you can stick it out, you
`
`know, in a power supply”).] Even if a POSA would interpret Christiansen’s
`
`statement to mean that one could always choose to place the arbiter literally
`
`anywhere in the system, a POSA would not co-locate the arbitration logic with the
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`DSP in Bowes because, as explained earlier and by Bowes himself, doing so would
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`run counter to optimizing the system.
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`B. Claims 8 and 10
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`40.
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`It my understanding that claims 8 and 10 depend on independent
`
`claim 7. As discussed above, Bowes, Datasheet, Artieri, and Christiansen do not
`
`render independent claim 7 obvious. Therefore, it is my opinion that claims 8 and
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`10 are not obvious at least for the same reasons.
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`C. Claim 9
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`41.
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`It my understanding that claim 9 depends on independent claim 7. As
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`discussed above, Bowes, Datasheet, Artieri, and Christiansen do not render
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`independent claim 7 obvious. Therefore, it is my opinion that claim 9 is not
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`obvious at least for the same reasons.
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`D. Claim 12
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`18
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`42.
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`It my understanding that claim 12 depends on independent claim 7.
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`As discussed above, Bowes, Datasheet, Artieri, and Christiansen do not render
`
`independent claim 7 obvious. Therefore, it is my opinion that claim 12 is not
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`obvious at least for the same reasons.
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`X. Conclusion
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`43. For the reasons discussed above, it is my opinion that claim 7 is not
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`obvious over Bowes, Datasheet, Artieri, and Christiansen; claims 8 and 10 are not
`
`obvious over Bowes, Datasheet, Artieri, Christiansen, and Arimilli; claim 9 is not
`
`obvious over Bowes, Datasheet, Artieri, Christiansen, and Shanley; and claim 12 is
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`not obvious over Bowes, Datasheet, Artieri, Christiansen, and Gove.
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`44.
`
`I reserve the right to amend or supplement this declaration based on,
`
`among other things, new evidence presented and/or new positions set forth by the
`
`Petitioners or on their behalf, including but not limited to additional materials
`
`provided to me for analysis in regard to the Petition.
`
`45.
`
`I, Mitchell A. Thornton, do hereby declare and state, that all
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`statements made herein of my own knowledge are true and that all statements
`
`made on information and belief are believed to be true; and further that these
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`statements were made with the knowledge that willful false statements and the like
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`so made are punishable by fine or imprisonment, under Section 1001 of Title 18 of
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`the United States Code.
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`19
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`Executed on: __March 9, 2017___
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`__________________________
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`Mitchell A. Thornton
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`20
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`APPENDIX A
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`APPENDIX A
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`PUMA Exhibit 2009
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`APPLE v. PUMA, |PR2016-01114
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`Page 22 of 43
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`PUMA Exhibit 2009
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`Mitchell Aaron Thornton
`10118 Woodlake Drive
`Dallas, Texas 75243
`mitcht@ieee.org
`
`EDUCATION
`• Ph.D., computer engineering, Southern Methodist University, Dallas, Texas (1995)
`• M.S., computer science, Southern Methodist University, Dallas, Texas (1993)
`• M.S., electrical engineering, University of Texas at Arlington, Arlington, Texas (1990)
`• B.S., electrical engineering, Oklahoma State University, Stillwater, Oklahoma (1985)
`
`
`LICENSES AND CERTIFICATIONS
`• Licensed Professional Engineer: Texas (70202), Mississippi (14477), and Arkansas (9255)
`• Registered Engineering Firm in State of Texas: Mitchell A Thornton, PE; F-6940
`• FCC Licenses: Commercial General Radiotelephone Operator License (GROL) with ship radar
`endorsement, call sign PG00028247; Amateur Radio Operator, Extra Class License, call sign
`KE5CDJ; General Mobile Radio License, call sign WQBX350
`• Electronic Technician diploma, graduate of two-year technical electronics program in the Tulsa
`area Vocational Technical School (1981)
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`EMPLOYMENT
`•
`2017-present, Acting Chair, Dept. of Computer Science and Engineering, Southern Methodist
`University
`2002-present: Cecil H. Green Chair of Engineering, (since Feb. 2015), Professor (Sept. 2006 –
`Jan. 2015), Associate Professor (2002-2006), Department of Computer Science and Engineering,
`and by courtesy, Department of Electrical Engineering, Southern Methodist University.
`Appointed with tenure in August 2002.
`2017-present: Research Director, Darwin Deason Institute for Cyber Security, Southern Methodist
`University.
`2015-2016: Interim Associate Director, Darwin Deason Institute for Cyber Security, Southern
`Methodist University.
`2014-2016: Technical Director, Darwin Deason Institute for Cyber Security, Southern Methodist
`University.
`1999-2002: Associate Professor, Department of Electrical and Computer Engineering, Mississippi
`State University, awarded tenure in May 2001.
`1995 to 1999: Associate Professor (1999), Assistant Professor (1995-99), Department of
`Computer Systems Engineering, and by courtesy, the Department of Electrical Engineering and
`the Department of Computer Science, University of Arkansas, awarded tenure in May 1999.
`1991 to 1995: Teaching Assistant (1991-93), Research Assistant (U.S. Superconducting
`Supercollider laboratories & NSF) (1993-95), Department of Computer Science and Engineering,
`Southern Methodist University
`1992: Design Engineer, Cyrix Corporation (full-time in summer, part time in Fall’92/1993)
`1986-1991: Sr. Electronic Systems Engineer (1990-91), Electronics Systems Engineer (1987-90),
`Engineer Analyst (1985-87), E-Systems, Inc, (now L-3 Communications Systems)
`1982-1984: Research Technician, Amoco Research Center (full-time in summers)
`
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`RESEARCH INTERESTS
`
`EDA/CAD methods and algorithms for quantum, classical digital systems, and large systems
`design including synthesis, verification, asynchronous, security, and disaster and fault tolerant
`circuit techniques. Emphasis on modeling and method development for information technology
`hardware/software, security design/verification, and the mathematical basis of conventional,
`asynchronous, reversible, and quantum logic. Practice a
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`peripheral design, embedded systems, and ASIC/FPGA design and implementation. Hardware,
`software, and firmware design and analysis. Deep familiarity with standards, various high-level
`software languages, numerous assemblers, EDA/CAD tools, and hardware description languages
`(both Verilog and VHDL).
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`FUNDED RESEARCH
`•
`(PI) Design and Implementation of OBDD Variable Ordering/Reordering Methods, National
`Science Foundation, 10/01/96 – 09/30/00, NSF/CISE/CCR/DA-9633085, $105,518.
`(PI) Design and Simulation of a Processing Element Node for a Decoupled Multi-Threaded
`Computer, Arkansas Science and Technology Authority, 10/01/96 - 09/30/97, 97-B-12, $34,133.
`(PI) Infrastructure and Faculty Fellowship Request for Configurable Computing, Arkansas Space
`Grant Consortium/NASA, 10/01/97 – 03/31/99, $5,553.
`(Co-PI) High Speed Parallel Fiber Optic Data Bus Components for NMP, Space Photonics, Inc.,
`07/01/98 – 10/31/98, $58,000.
`(PI) Implementation of ASM using an FPGA Based Co-processor, Acxiom Corporation with
`100% match from the Arkansas Science and Technology Authority, 99-A-01, 09/01/98 –
`08/13/99, $100,000.
`(Co-PI) Developmen