IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`TEXAS INSTRUMENTS INCORPORATED,
`Petitioner,
`
`v.
`
`ADVANCED SILICON TECHNOLOGIES, LLC
`Patent Owner
`
`Case No. To Be Assigned
`Patent No. 8,933,945
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 8,933,945 CHALLENGING CLAIMS 1-11 AND 21
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 et seq.
`
`
`
`
`
`
`
`
`
`
`
`

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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`
`TABLE OF CONTENTS
`
`
`
`I. MANDATORY NOTICES (37 C.F.R. § 42.8(A)(1)) ..................................... 1
`
`A.
`
`B.
`
`C.
`
`D.
`
`Real Party-In-Interest (37 C.F.R. § 42.8(b)(1)) .................................... 1
`
`Related Matters (37 C.F.R. § 42.8(b)(2)) .............................................. 1
`
`Lead and Backup Counsel (37 C.F.R. § 42.8(b)(3)) ............................. 2
`
`Service Information (37 C.F.R. § 42.8(b)(3)) ....................................... 2
`
`II.
`
`FEES (37 C.F.R. § 42.103) .............................................................................. 2
`
`III. REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104 ............................ 3
`
`A. Grounds for Standing (37 C.F.R. § 42.104(a)) ..................................... 3
`
`B.
`
`C.
`
`Prior Art Publications Relied Upon ...................................................... 3
`
`Claims and Statutory Grounds (37 C.F.R. §§ 42.104(b)(1) &
`(b)(2)) .................................................................................................... 3
`
`IV. OVERVIEW OF THE ’945 PATENT ............................................................ 4
`
`A.
`
`B.
`
`C.
`
`Background of the ’945 Patent .............................................................. 4
`
`The solution – and purported invention – of the ’945 Patent is
`tile-based, screen partitioning ............................................................... 6
`
`The prosecution history of the ’945 Patent demonstrates tile-
`based, screen partitioning was known ................................................... 9
`
`1.
`
`2.
`
`3.
`
`U.S. Patent No. 5,794,016 (“Kelleher”) ..................................... 9
`
`U.S. Patent No. 6,864,896 (“Perego”) ...................................... 10
`
`The ’945 Patent issued because the Board determined
`that the examiner did not address how Perego discloses a
`memory shared among the pipelines ........................................ 11
`
`V.
`
`PERSON OF ORDINARY SKILL IN THE ART ........................................12
`- i -
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
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`VI. CLAIM CONSTRUCTION (37 C.F.R. §42.104 (B)(3)) ..............................13
`
`A.
`
`B.
`
`“repeating tile pattern” ........................................................................13
`
`“N×M number of pixels” .....................................................................14
`
`VII. SUMMARY OF THE REFERENCES APPLIED IN THIS
`PETITION .....................................................................................................15
`
`A.
`
`B.
`
`C.
`
`D.
`
`E.
`
`The Balmer Patent ...............................................................................15
`
`The Narayanaswami Patent .................................................................19
`
`Foley ....................................................................................................23
`
`The Furtner Patent ...............................................................................24
`
`The Kelleher Patent .............................................................................24
`
`VIII. THE CHALLENGED CLAIMS ARE UNPATENTABLE ..........................25
`
`A. Ground I: Claims 1, 9, 10, and 21 are obvious in view of the
`combination of Balmer and Narayanaswami ......................................26
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`Rationale for combining Balmer and Narayanaswami ............. 26
`
`Claim 1 Preamble - “A graphics processing circuit:” ............... 30
`
`Claim 1 [1a] - “at least two graphics pipelines on a same
`chip” .......................................................................................... 30
`
`Claim 1 [1b] - “operative to process data in a
`corresponding set of tiles of a repeating tile pattern
`corresponding to screen locations,” .......................................... 33
`
`Claim 1 [1c] - “a respective one of the at least two
`graphics pipelines operative to process data in a
`dedicated tile; and”.................................................................... 36
`
`Claim 1 [1d] - “a memory controller on the chip in
`communication with the at least two graphics pipelines,
`operative to transfer pixel data between each of a first
`pipeline and a second pipeline and a memory shared
`among the at least two graphics pipelines;” .............................. 37
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
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`7.
`
`8.
`
`9.
`
`Claim 1 [1e] - “wherein the repeating tile pattern includes
`a horizontally and vertically repeating pattern of square
`regions.” .................................................................................... 39
`
`Claim 9 - “The graphics processing circuit of claim 1,
`wherein each tile of the set of tiles further comprises a
`16×16 pixel array.” ................................................................... 40
`
`Claim 10 - “The graphics processing circuit of claim 1,
`wherein a second of the at least two graphics pipelines
`processes the data only in a second set of tiles in the
`repeating tile pattern.” ............................................................... 41
`
`10. Claim 21 Preamble - “A graphics processing circuit:” ............. 42
`
`11. Claim 21 [21a] – “at least two graphics pipelines on a
`chip” .......................................................................................... 42
`
`12. Claim 21 [21b] - “operative to process data in a
`corresponding set of tiles of a repeating tile pattern
`corresponding to screen locations,” .......................................... 42
`
`13. Claim 21 [21c] - “a respective one of the at least two
`graphics pipelines operative to process data in a
`dedicated tile,” .......................................................................... 42
`
`14. Claim 21 [21d] - “wherein the repeating tile pattern
`includes a horizontally and vertically repeating pattern of
`regions;” .................................................................................... 42
`
`15. Claim 21 [21e] - “wherein the horizontally and vertically
`repeating pattern of regions include N×M number of
`pixels; and” ............................................................................... 43
`
`16. Claim 21 [21f] - “a memory controller on the chip,
`coupled to the at least two graphics pipelines on the chip
`and operative to transfer pixel data between each of the
`two graphics pipelines and a memory shared among the
`at least two graphics pipelines.”................................................ 44
`
`B.
`
`Ground II: Claim 2 and 3 are obvious in view of the
`combination of Balmer, Narayanaswami, and Furtner .......................44
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`- iii -
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`
`1.
`
`2.
`
`3.
`
`Rationale for combining Balmer, Narayanaswami, and
`Furtner ....................................................................................... 44
`
`Claim 2 - “The graphics processing circuit of claim 1,
`wherein the square regions comprise a two dimensional
`partitioning of memory.” .......................................................... 45
`
`Claim 3 - “The graphics processing circuit of claim 2,
`wherein the memory is a frame buffer.” ................................... 47
`
`C. Ground III: Claims 4-8 and 11 are obvious in view of the
`combination of Balmer, Narayanaswami, and Foley ..........................48
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`Rationale for combining Balmer, Narayanaswami, and
`Foley .......................................................................................... 48
`
`Claim 4 [4a] - “The graphics processing circuit of claim
`1, wherein each of the at least two graphics pipelines
`further includes front end circuitry operative to receive
`vertex data and generate pixel data corresponding to a
`primitive to be rendered” .......................................................... 49
`
`Claim 4 [4b] - “and back end circuitry, coupled to the
`front end circuitry, operative to receive and process a
`portion of the pixel data.” ......................................................... 51
`
`Claim 5 - “The graphics processing circuit of claim 4,
`wherein each of the at least two graphics pipelines further
`includes a scan converter, coupled to the back end
`circuitry, operative to determine the portion of the pixel
`data to be processed by the back end circuitry.” ...................... 53
`
`Claim 6 - “The graphics processing circuit of claim 4,
`wherein the at least two graphics pipelines separately
`receive the pixel data from the front end circuitry.” ................. 56
`
`Claim 7 - “The graphics processing circuit of claim 6,
`wherein a first of the at least two graphics pipelines
`processes the pixel data only in a first set of tiles in the
`repeating tile pattern.” ............................................................... 58
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`- iv -
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`7.
`
`8.
`
`9.
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
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`Claim 8 [8a] - “The graphics processing circuit of claim
`7, wherein the first of the at least two graphics pipelines
`further includes a scan converter, coupled to the front end
`circuitry and the back end circuitry, operative to provide
`position coordinates of the pixels within the first set of
`tiles to be processed by the back end circuitry,” ...................... 59
`
`Claim 8 [8b] - “the scan converter including a pixel
`identification line for receiving tile identification data
`indicating which of the set of tiles is to be processed by
`the back end circuitry.” ............................................................. 61
`
`Claim 11 [11a] - “The graphics processing circuit of
`claim 10, wherein the second of the at least two graphics
`pipelines further includes a scan converter, coupled to the
`front end circuitry and the back end circuitry, operative
`to provide position coordinates of the pixels within the
`second set of tiles to be processed by the back end
`circuitry,” .................................................................................. 62
`
`10. Claim 11 [11b] - “the scan converter including a pixel
`identification line for receiving tile identification data
`indicating which of the set of tiles is to be processed by
`the back end circuitry.” ............................................................. 63
`
`D. Ground IV: Claims 8 and 11 are obvious in view of the
`combination of Balmer, Narayanaswami, Foley, and Kelleher ..........63
`
`1.
`
`2.
`
`3.
`
`Rationale for combining Balmer, Narayanaswami, Foley,
`and Kelleher .............................................................................. 63
`
`Claim 8 [8a] - “The graphics processing circuit of claim
`7, wherein the first of the at least two graphics pipelines
`further includes a scan converter, coupled to the front end
`circuitry and the back end circuitry, operative to provide
`position coordinates of the pixels within the first set of
`tiles to be processed by the back end circuitry,” ...................... 64
`
`Claim 8 [8b] - “the scan converter including a pixel
`identification line for receiving tile identification data
`indicating which of the set of tiles is to be processed by
`the back end circuitry.” ............................................................. 65
`- v -
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
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`4.
`
`5.
`
`Claim 11 [11a] - “The graphics processing circuit of
`claim 10, wherein the second of the at least two graphics
`pipelines further includes a scan converter, coupled to the
`front end circuitry and the back end circuitry, operative
`to provide position coordinates of the pixels within the
`second set of tiles to be processed by the back end
`circuitry,” .................................................................................. 67
`
`Claim 11 [11b] - “the scan converter including a pixel
`identification line for receiving tile identification data
`indicating which of the set of tiles is to be processed by
`the back end circuitry.” ............................................................. 67
`
`IX. CONCLUSION ..............................................................................................68
`
`
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`- vi -
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`

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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`
`TABLE OF AUTHORITIES
`
`
`
`Page(s)
`
`Cases
`Computer Docking Station Corp. v. Dell, Inc.,
`
`519 F.3d 1366 (Fed. Cir. 2008) ......................................................................... 15
`
`In re Translogic Tech., Inc.,
`504 F.3d 1249 (Fed. Cir. 2007) .......................................................................... 13
`
`Statutes
`35 U.S.C. § 102(b) ................................................................................... 3, 26, 48, 63
`
`35 U.S.C. § 103 .......................................................................................................... 4
`
`35 U.S.C. § 314(a) ................................................................................................... 25
`
`35 U.S.C. § 325(d) ............................................................................................ 25, 26
`
`Other Authorities
`37 C.F.R. § 42.100(b) .............................................................................................. 13
`
`
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`- vii -
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`

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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`
`LIST OF EXHIBITS
`
`
`Description
`U.S. Patent No. 8,933,945 (the “’945 patent”)
`File History for U.S. Patent No. 8,933,945
`Declaration of Richard Goodin
`U.S. Patent No. 6,778,177 to Furtner (“Furtner”)
`U.S. Patent No. 5,794,016 to Kelleher (“Kelleher”)
`U.S. Patent No. 6,864,896 to Perego (“Perego”)
`U.S. Patent No. 5,226,125 to Balmer et al. (“Balmer”)
`U.S. Patent No. 5,757,385 to Narayanaswami et al.
`(“Narayanaswami”)
`James D. Foley et al., Computer Graphics: Principles and
`Practice, Second Edition in C, 1997 (“Foley”)
`Carl Mueller, “The Sort-First Rendering Architecture for High-
`Performance Graphics,” Proc. 1995 Sym. on Interactive 3D
`Graphics, Monterey, CA, Apr. 9-12, 1995, pp. 75-84 (“Mueller”)
`Scott Whitman, Multiprocessor Methods for Computer Graphics
`Rendering, 1992 (“Whitman”)
`Curriculum Vitae of Richard Goodin
`
`Exhibit
`Ex. 1001
`Ex. 1002
`Ex. 1003
`Ex. 1004
`Ex. 1005
`Ex. 1006
`Ex. 1007
`Ex. 1008
`
`Ex. 1009
`
`Ex. 1010
`
`Ex. 1011
`
`Ex. 1012
`
`- viii -
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`

`
`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`
`I. MANDATORY NOTICES (37 C.F.R. § 42.8(A)(1))
`A. Real Party-In-Interest (37 C.F.R. § 42.8(b)(1))
`The real party-in-interest for this petition for Inter Partes Review (“IPR”) is
`
`Petitioner Texas Instruments Incorporated.
`
`B. Related Matters (37 C.F.R. § 42.8(b)(2))
`Advanced Silicon Technologies, LLC (“AST”) asserted U.S. Patent No.
`
`8,933,945 (the “’945 patent”) in the following cases in the U.S. District Court for
`
`the District of Delaware:
`
`i) AST v. Volkswagen AG, 1-15-cv-01181; ii) AST v. Toyota Motor Co., 1-
`
`15-cv-01180; iii) AST v. Honda Motor Co., Ltd., 1-15-cv-01179; iv) AST v.
`
`Bayerisch Motoren Werke AG, 1-15-cv-01178; v) AST v. NVIDIA Corp., 1-15-cv-
`
`01177; vi) AST v. Renesas Electronics Corp., 1-15-cv-00176; vii) AST v. Texas
`
`Instruments Inc., 1-15-cv-01175; viii) AST v. Fujitsu Ten Ltd. et al., 1-15-cv-
`
`01174; and ix) AST v. Harman Int’l Industries, Inc., 1-15-cv-01173.
`
`AST has also asserted the ’945 patent in the complaint captioned “Certain
`
`Computing or Graphics Systems, Components Thereof, and Vehicles Containing
`
`Same,” Investigation No. 337-TA-984, filed December 28, 2015 at the U.S.
`
`International Trade Commission, naming, among numerous others, the Petitioner.
`
`In addition, the following inter partes review petitions have been filed for
`
`U.S. Patent No. 8,933,945:
`
`1
`
`

`
`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`
`i) Volkswagen Group of America, Inc. v. Advanced Silicon Technologies,
`
`LLC, IPR2016-00894, filed April 15, 2016.
`
`ii) Unified Patents Inc. v. Advanced Silicon Technologies, LLC, IPR2016-
`
`01060, filed May 19, 2016.
`
`C. Lead and Backup Counsel (37 C.F.R. § 42.8(b)(3))
`Lead Counsel is Gregory S. Discher (Reg. No. 42,488); T: (202) 662-5485;
`
`F: (202) 778-5485; E: gdischer@cov.com. Backup Counsel is David A. Garr (Reg.
`
`No. 74,932); T: (202) 662-5250; F: (202) 778-5250; E: dgarr@cov.com.
`
`Additional Backup Counsel is Andrea G. Reister (Reg. No. 36,253); T: (202) 662-
`
`5141; F: (202) 778-5141; E: areister@cov.com. The postal and hand delivery
`
`address for the foregoing counsel is: Covington & Burling LLP, One CityCenter,
`
`850 Tenth Street, NW, Washington, DC 20001.
`
`Service Information (37 C.F.R. § 42.8(b)(3))
`
`D.
`Service information is provided in the designation of counsel above.
`
`Counsel for Petitioner consents to service of all documents via electronic mail.
`
`II.
`
`FEES (37 C.F.R. § 42.103)
`
`The undersigned authorizes the Office to charge $23,000 ($9,000 request
`
`fee, $14,000 post-institution fee) to Deposit Account No. 50-0740 for the fees set
`
`forth in 37 C.F.R. § 42.15(a) for this Petition for Inter Partes Review. The
`
`undersigned also authorizes payment for any additional fees that might be due in
`
`connection with this Petition to be charged to the Deposit Account.
`2
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`

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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
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`III. REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104
`A. Grounds for Standing (37 C.F.R. § 42.104(a))
`Pursuant to 37 C.F.R. § 42.104(a), Petitioner certifies that the ’945 patent is
`
`available for IPR and that Petitioner is not barred or estopped from requesting an
`
`IPR challenging the ’945 patent on the grounds identified in the present petition.
`
`Prior Art Publications Relied Upon (37 C.F.R. §§ 42.104(b)(2))
`
`B.
`1. U.S. Patent No. 5,226,125, which issued on July 6, 1993 and is prior art
`
`to the ’945 patent under 35 U.S.C. § 102(b). (“Balmer,” Ex. 1007).
`
`2. U.S. Patent No. 5,757,385, which issued on May 26, 1998 and is prior art
`
`to the ’945 patent under 35 U.S.C. § 102(b). (“Narayanaswami,” Ex. 1008).
`
`3. James D. Foley et al., Computer Graphics: Principles and Practice,
`
`Second Edition in C, 1997, which is prior art to the ’945 patent under 35 U.S.C.
`
`§ 102(b). (“Foley,” Ex. 1009).
`
`4. U.S. Patent No. 6,778,177, which issued on August 17, 2004 and is prior
`
`art to the ’945 patent under 35 U.S.C. § 102(e). (“Furtner,” Ex. 1004).
`
`5. U.S. Patent No. 5,794,016, which issued on August 11, 1998 and is prior
`
`art to the ’945 patent under 35 U.S.C. § 102(b). (“Kelleher,” Ex. 1005).
`
`C. Claims and Statutory Grounds (37 C.F.R. §§ 42.104(b)(1) &
`(b)(2))
`Petitioner requests inter partes review of claims 1-11 and 21 because each of
`
`the challenged claims is unpatentable on the following grounds:
`
`3
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`

`
`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`
`Ground I: Claims 1, 9, 10, and 21 are unpatentable under 35 U.S.C. § 103 as
`
`obvious over the combination of Balmer and Narayanaswami.
`
`Ground II: Claims 2 and 3 are unpatentable under 35 U.S.C. § 103 as
`
`obvious over the combination of Balmer, Narayanaswami, and Furtner.
`
`Ground III: Claims 4-8 and 11 are unpatentable under 35 U.S.C. § 103 as
`
`obvious over the combination of Balmer, Narayanaswami, and Foley.
`
`Ground IV: Claims 8 and 11 are unpatentable under 35 U.S.C. § 103 as
`
`obvious over the combination of Balmer, Narayanaswami, Foley, and Kelleher.
`
`IV. OVERVIEW OF THE ’945 PATENT
`The ’945 patent “relates to graphics processing circuitry and, more
`
`particularly, to dividing graphics processing operations among multiple pipelines.”
`
`Ex. 1001, 1:21-23. The ’945 patent states that conventional “graphics processing
`
`systems typically include a host processor, graphics (including video) processing
`
`circuitry, memory (e.g., frame buffer), and one or more display devices.” Id., 1:26-
`
`30. The graphics processing circuitry generates pixel data, which is presented as
`
`an object or a scene on the display screen. Id., 1:41-43.
`
`A. Background of the ’945 Patent
`In the Background section, the ’945 patent states that prior art systems
`
`“partitioned” the screen of a “conventional display device”—and “[i]n like manner,
`
`the frame buffer”—into a series of vertical or horizontal “strips.” Id., 1:44-51.
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`4
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
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`The strips 13-18 are each “typically 1-4 pixels in width.” Id., 1:46. Annotated
`
`Figure 1 shows such a display partitioned into vertical
`
`strips, each strip assigned to a separate graphics
`
`processing circuit. “To decrease processing time, . . .
`
`one graphics processing circuit is responsible for one
`
`vertical strip (e.g. 13) of the frame while another
`
`graphics processing circuit is responsible for another vertical strip (e.g. 14) of the
`
`frame.” Id., 2:5-11.
`
`But, according to the ’945 patent, load balancing is a significant drawback
`
`associated with the vertical (or horizontal) partitioning systems that use a separate
`
`graphics processing circuit for each vertical strip. Id., 2:14-15. “Load balancing
`
`problems occur, for example, when all of the primitives 20-23 [(e.g., triangles)] of
`
`a particular object or scene are located in one strip (e.g., strip 13) as illustrated in
`
`FIG. 1.” Id., 2:15-18. “When this occurs, only the graphics processing circuit
`
`responsible [for] strip 13 is actively processing primitives; the remaining graphics
`
`processing circuits [(e.g., those responsible for strips 14-18, above)] remain idle.”
`
`Id., 2:18-22. The load imbalance amongst the graphics processing circuits “results
`
`in a significant waste of computing resources,” (id., 2:22-23), and the ʼ945 patent
`
`acknowledges approaches, such as reduction in strip width, and frame-based
`
`subdivision, have been employed to improve system performance. Id., 2:27-49.
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`5
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
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`B.
`
`The solution – and purported invention – of the ’945 Patent is tile-
`based, screen partitioning
`
`Rather than assigning graphics processing circuits to process data in vertical
`
`or horizontal strips, the ʼ945 patent employs a conventional technique that
`
`partitions the display (and frame buffer) into a horizontally and vertically repeating
`
`pattern of regions, or tiles. Id., 3:25-26, 2:35-39, 5:48-49. Each independent claim
`
`of the ʼ945 patent recites a “repeating tile pattern,” where the repeating tile pattern
`
`includes a “horizontally and vertically repeating pattern of . . . regions,” where
`
`graphics pipelines “process data in a corresponding set of tiles of the repeating tile
`
`pattern.” Id., 9:66-10:1, 10:9-10, 12:1-2, 12:27-29. Annotated Figure 3
`
`(reproduced below) illustrates this approach:
`
`Figure 3 depicts partitioning the display into a repeating tile pattern of
`
`
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`6
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
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`horizontal and vertical square tiles (or regions) 72-75. Id., 5:46-49. Each tile (or
`
`region) in annotated Figure 3 can be “implemented as a 16×16 pixel array.”1 Id.,
`
`5:51-52. The repeating pattern of tiles (or regions) in the frame buffer corresponds
`
`to the partitioning of the display into tiles (or regions). Id., 5:52-53. The
`
`partitioning pattern is based on the number of and assignment of active graphics
`
`pipelines to the horizontally and vertically arranged regions, and in a “two pipeline
`
`configuration, a ‘checkerboard’ pattern is created for the pipes and the patterns
`
`repeat over the full screen.” Id., 8:58-62.
`
`As shown in annotated Figure 3 (reproduced above), one graphics
`
`processing circuit (or “graphics pipeline”) is responsible for tiles labeled “A,”
`
`whereas a second graphics pipeline is responsible for tiles labeled “B.” Id., 5:45-
`
`65. More precisely, “[w]hen rendering a primitive (e.g. triangle) 80, the first
`
`graphics pipeline 101 processes only those pixels in portions 81, 82 of the
`
`primitive 80 that intersects tiles labeled “A”, for example, 72 and 75” (id., 5:54-57)
`
`
`
`1 The ’945 patent interchangeably uses the terms “tile” or “region,” (see, e.g.,
`
`id. at 3:26-31, 5:46-54, 7:47-49), when referring to a two-dimensional array of
`
`pixels. A tile (or region) can be a square array of pixels (e.g., 8×8, 16×16, or
`
`32×32 pixels) or a non-square array of pixels. Id., 8:42-45.
`
`7
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`

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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
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`and “the second graphics pipeline 102 processes only those pixels in portions 83,
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`84 of the primitive 80 that intersects tiles labeled “B”, for example 73-74.” Id.,
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`5:60-63; Fig. 3.
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`The ’945 patent specification explains how this assignment of graphics
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`pipelines to alternating horizontal and vertical tiles (or regions) addresses the
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`shortcoming over the prior art technique of assigning graphics processing circuits
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`to strips on the screen. Ex. 1001, 5:66-6:9; see id., 3:26-31 (explaining that the
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`subdivision of a frame buffer, coupled to multiple graphics pipelines, into a
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`replicating pattern of square regions (or tiles) such that “each region is processed
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`by a corresponding one” of the multiple graphics pipelines enhances load
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`balancing and texture cache utilization).
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`In other embodiments, the ’945 patent employs a conventional partitioning
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`technique for more than two graphics pipelines. For example, Figure 4 of the ’945
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`patent
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`illustrates a frame buffer partitioned
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`into a repeating pattern
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`to
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`accommodate more than two graphics pipelines. Id., 6:10-15. In annotated
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`Figures 2, 4, and 5 (reproduced below), the relationship between the tiles of the
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`repeating tile pattern and the graphics pipelines that correspond to, as well as
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`process, each tile is illustrated.
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
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`Based on the setting of the pixel identification lines (38, 41, 138, 141) on the
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`respective scan converters (37, 40, 137, 140) in the graphics pipelines (101, 102,
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`201, 202), the back end circuitry in each of the pipelines processes specific tiles in
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`the repeating tile pattern shown in annotated Figure 4. Id., 7:28-46. In this
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`embodiment, the ’945 patent discloses that “substantially equal load balancing
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`between the pipelines” is achieved, as each of the graphics pipelines will be
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`responsible for processing one-fourth of the tiles 92-99 of the repeating tile pattern,
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`and further results in “increased graphics processing performance.” Id., 7:55-65.
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`C. The prosecution history of the ’945 Patent demonstrates tile-based,
`screen partitioning was known
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`The application that gave rise to the ’945 patent was filed on June 12, 2003.
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`The ’945 patent issued on January 13, 2015. During the eleven year prosecution
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`history of the ’945 patent, applicants conceded that at least two prior art references
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`that were applied to the then-pending claims disclose tile-based, screen partitioning.
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`U.S. Patent No. 5,794,016 (“Kelleher”)
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`1.
`In a February 9, 2007 Office Action, the Examiner rejected the pending
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`claims over U.S. Patent No. 5,794,016 to Kelleher. Ex. 1002, 182-98. The
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`examiner stated that Kelleher discloses a graphics processing circuit that is
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`“operative to process data in a corresponding set of tiles (group of pixel blocks 52,
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`Figure 4) of a repeating tile pattern corresponding to screen locations, a respective
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`one of the at least two graphics pipelines operative to process data in a dedicated
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`tile, wherein the repeating tile pattern includes a horizontally and vertically
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`repeating pattern of square regions, as shown in Figure 4 (graphics memory 22 that
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`has been partitioned into a plurality of pixel blocks 52 that are tiled in the x-and y-
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`direction of the graphics memory 22 . . . .).” Id., 186.
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`Effectively conceding that Kelleher disclosed a “repeating tile pattern,”
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`applicants amended claim 1 to include a “memory controller in communication
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`with the at least two graphics pipelines . . . .” Ex. 1002, 203. Applicants
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`“respectfully disagree[d] that Kelleher discloses a memory controller coupled to at
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`least two graphics pipelines.” Id., 301. Applicants did not argue that Kelleher fails
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`to disclose the claimed “repeating tile pattern includes a horizontally and vertically
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`repeating pattern of square regions” recited in claim 1, and similarly recited in
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`claim 21.
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`U.S. Patent No. 6,864,896 (“Perego”)
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`2.
`In an August 28, 2007 Office Action, the Examiner withdrew the rejections
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`based on Kelleher, and instead applied U.S. Patent No. 6,864,896 to Perego. Id.,
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`333-45. The Examiner stated that Perego discloses a graphics processing circuit
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`that is “operative to process data in corresponding set of tiles of repeating tile
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`pattern corresponding to screen locations, respective one of at least two graphics
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`pipelines operative to process data in a dedicated tile (c. 5, ll. 19-27, 38-44) . . . .”
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`Ex. 1002, 239. The Examiner also stated that “[t]he repeating tile pattern includes
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`a horizontally and vertically repeating pattern of regions of square regions, as
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`shown in Figure 5 (c. 5, ll. 19-27, 38-44).” Ex. 1002, 239.
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`In their arguments to overcome Perego, applicants again implicitly conceded
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`that Perego discloses the “repeating tile pattern” limitation, and instead argued that
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`“Perego requires multiple discrete memory modules each with its own rendering
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`engine and each with its own memory and shared main memory.” Id., 357.
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`Applicants did not argue that Perego fails to disclose the claimed “repeating tile
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`pattern includes a horizontally and vertically repeating pattern of square regions”
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`recited in claim 1, and similarly recited in claim 21.
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`3.
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`The ’945 Patent issued because the Board determined that
`the examiner did not address how Perego discloses a
`memory shared among the pipelines
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`After the August 28, 2007 Office Action, applicants and the Examiner
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`exchanged arguments involving Perego for several years. Ex. 1002, 253-497.
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`During this period, the applicants made amendments to claim 1 to require the
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`graphics pipelines and memory controller to be on the same chip (id., 255, 260,
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`385), and the memory is shared among the pipelines (id., 432, 437).
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`Applicants appealed to the Board. Id., 499-535. On appeal, the Board found
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`that the Examiner failed to show that Perego discloses the limitation of “a memory
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`shared among the at least two graphics pipelines” in system claims 1 and 25 (id.,
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`587), which issued as patent claims 1 and 21 (id., 528, 533) and the application
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`issued as the ’945 patent.
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`Thus, the ’945 patent did not issue because it discloses novel and
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`nonobvious tile-based, screen partitioning. Rather, it issued because the examiner
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`failed to establish that the features of condensing circuitry to a single integrated
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`circuit, and a memory shared among graphics pipelines were both known. Ex.
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`1003, ¶¶42-49. These features were well known, and a POSITA would have had
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`reason, the capabilities, and a reasonable expectation of success in using a single
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`integrated circuit with a shared memory controller. Id.
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`V.
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`PERSON OF ORDINARY SKILL IN THE ART
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`With respect to the ’945 patent, a POSITA would have a B.S. degree in
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`electrical engineering, computer science, or an equivalent field as well as at least 2-
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`3 years of academic or industry experience in computer graphics, image processing
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`hardware, general computer architecture, or comparable industry experience.
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`Experience could take the place of some formal training, as domain knowledge
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`may be learned on the job. This description is approximate, and a higher level of
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`education or skill might make up for less experience and vice versa. Ex. 1003,
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`¶50; see also id., ¶¶19-31.
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`VI. CLAIM CONSTRUCTION (37 C.F.R. §42.104 (B)(3))
`A claim subject to IPR is given its “broadest reasonable construction in light
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`of the specification of the patent in which it appears.” 37 C.F.R. § 42.100(b).
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`Under that standard, the Boar