United States Patent
`
`[19]
`
`||||l|||l|||l||||||||l||l|l|||l||||l|llllllllllllllllllllllllllllllllllllll
`US005226l25A
`[11] Patent Number:
`
`5,226,125
`
`
`Balmer et al.
`[45] Date of Patent:
`Jul. 6, 1993
`
`Quicker Than A Wink”, by W. W. Smith, P. Sullivan, in
`Electronic Design, pp. 257-266, (1984).
`“Real Time 3D Object Tracking in a'Rapid Prototyping
`Environment,” by Robert J‘ Gove’ m Electronic Imag-
`‘"3 '33- (1933)-
`“Integration of Symbolic and Multiple Digital Signal
`Processors with the Explorer/Odyssey for Image Pro-
`cessmg. and Understanding Applications , by Robert J.
`Gove, in Proceedings of the IEEE International Sympo-
`sium on Circuits and Systems, pp. 968-971, (May, 1987).
`“The Use of Parallel—Processing Computers in Digital
`Image PT°C¢551ng”. by LEW BFOWII. Publlshed by A1’
`liant Computer Systems Corp., Littleton, Mass.
`“ViTec Parallel C Compiler”, by T. Butler, published
`by Visual Information Technologies, Inc., Plano, Tex.,
`pp. 741-747.
`.
`“A Single Board Image Computer with 64 Parallel
`Processes”, by Stephen Wilson, published in Electronic
`Imaging ’87, International Electronic Imaging Exposi-
`“°“ 3‘ C°‘‘f‘‘’e”°°’ 0987)’ 1-"P' 47°‘745'
`“The Androx Parallel Image Array Processor”, by
`Wayne Threatt, in Electronic Imaging ’87, International
`(List continued on next page.)
`
`Primary Examiner—Robert L. Richardson
`Attorney, Agent, or Firm—Robert D. Marshall, Jr.;
`James C. Kesterson; Richard L. Donalddson
`[57]
`ABSTRACT
`There is disclosed a switch matrix and operational
`method relying upon a high degree of operational logic
`at each matrix crosspoint. In one embodiment,
`the
`.
`.
`.
`.
`switch is used in a multiprocessor system arranged as an
`image and graphics processor. The processor is struc-
`tured with several individual processors all having com-
`munication links to several memories without restric-
`tion_ The switch matrix Serves to esmblish the processor
`.
`.
`.
`-
`.
`.
`memory links and the entire image processor, including
`the individual processors, the crossbar switch and the
`memories and is contained on a single silicon substrate.
`
`24C]ajms 35 D;-awin sheets
`,
`2
`
`I76]
`
`[54] SWITCH MATRIX HAVING INTEGRATED
`CROSSPOINT LOGIC AND METHOD OF
`OPERATION
`Inventors: Keith Balmer, 6 Salcombe Close,
`B df d B df d it
`, E 1
`Mexjzf 381,; N§;’,,j,,;’
`"g and
`Ingsimmons, 74 Lincroft, Oakley,
`Bedford (gedfordshirel England,
`MK43 755; Karl M_ Guttag, 4015 s_
`sandy ct,’ Missouri city (Han-is
`county), Tex 77459; Robert J_ cove,
`1405 Scarborough La., Plano (Collin
`county), Tex 75075
`
`,
`
`121] Appl‘ No‘: 43-L875
`[22] Filed:
`Nov. 17, 1989
`
`C(l?Is ..............................
`3:40/825 7;
`'
`°
`' """"""""""""""""""
`[58] Field of Search .................. 364/DIG. i, DIG: 2;
`_
`.
`340/82179’ 8255’ 82551’ 370/632555/82%’05§'215:
`References Cited
`
`[56]
`
`U‘S' PATENT DOCUMENTS
`3,581,286
`5/1971 Beausoleil
`3,651,473 3/I972 Faber ............
`3,787,818
`1/I974 Arnold et al.
`354/900
`4,058,316 11/1977 M1116! --------
`364/200
`4v195’34‘1 3/1980 Yamazakl -----'
`,. 364/200
`4,562,535 l2/1985 Vincent et al.
`364/900
`4,644,496
`2 1987 A d
`........ ..
`364/200
`4,731,724 32988 M?e,::;"1’Set al.
`,,,,, ,_ 354/zoo
`4,747,043
`5/1933 Rodman
`....... 364/200
`4,905,141
`2/1990 Berenza
`------- 354/513
`4949330 3/1990 Li"1efi€1d -
`4,989,131
`1/1991 Stone ................................. .. 364/200
`5,041,971
`8/1991 Carvey et al.
`.
`
`
`
`.
`
`.. 364/200
`
`OTHER PUBLICATIONS
`lime Connection Machine», by W. D_ Hills’ published
`in The MIT Press, (1985).
`“Handling Real Time Images Comes Naturally to Sys-
`tolic Array Chip”, by Hannaway, Shea, Bishop, in Elec-
`tronic Design, pp. 289-300, (1984).
`“Systolic Array Chip Recognizes Visual Patterns
`V
`
`I" ——————— "_tnTa§u'Et.‘oa'—p'<>E ------- ‘"1,
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`
`TEXAS INSTRUMENTS EX. 1007 - 1/71
`
`TEXAS INSTRUMENTS EX. 1007 - 1/71
`
`

`
`5,226,125
`
`Page 2
`
`OTHER PUBLICATIONS
`
`Electronic Imaging Exposition & Conference, (1987),
`pp. 1061-1064.
`“Design of a Massively Parallel Processor”, by
`Kenneth Batcher, IEEE Transactions on Computers, vol.
`C-29, No. 9, (1980).
`“High Resolution Frame Grabbing and Processing
`Through Parallel Architecture”, by Daniel Crevier
`published by Coreco, Inc., Quebec, Canada.
`“Multiple Digital Signal Processor Environment for
`Intelligent Signal Processing”, by Gass et al., in Pro-
`ceedings of the IEEE, vol. 75, No. 9, (Sep. 1987), pp.
`1246-1259.
`
`“Architecture and Design of the MARS Hardware
`Accelerator”, Agra Wall et al., in 24th ACM/IEEE
`Design Automation Conference, (1987), pp. 101-107.
`“Digital Video & Image Processors”, by O’Brien,
`Mather & Holland, published by Plessey Semiconduc-
`tors, (1989).
`“An Architecture Study, Design and Implementation of
`Digital Image Acquisition, Processing and Display Sys-
`tems with Micro—Processor—Based Personal Computers
`and Charge—Coup1ed Device Imaging Technology", a
`dissertation by Robert J. Gove, S.M.U., (1986).
`“A Medium Grained Parallel Computer for Image Pro-
`cessing”, by R. S. Cok, published by Digital Technol-
`ogy Center, Eastman Kodak Co., Rochester, NY.
`
`TEXAS INSTRUMENTS EX. ‘I007 - 2/71
`
`TEXAS INSTRUMENTS EX. 1007 - 2/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 1 of 35
`
`5,226,125
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`TEXAS INSTRUMENTS EX. 1007 - 3/71
`
`TEXAS INSTRUMENTS EX. 1007 - 3/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 2 of 35
`
`5,226,125
`
`TEXAS INSTRUMENTS EX. 1007 - 4/71
`
`TEXAS INSTRUMENTS EX. 1007 - 4/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 3 of 35
`
`5,226,125
`
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`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 4 of 35
`
`5,226,125
`
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`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 5 of 35
`
`5,226,125
`
`FIG. 13
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`U.S. Patent
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`July 6, 1993
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`Sheet 6 of 35
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`U.S. Patent
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`July 6, 1993
`
`Sheet 9 of 35
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`5,226,125
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`U.S. Patent
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`July 6, 1993
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`Sheet 10 of 35
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`5,226,125
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`U.S. Patent
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`July 6, 1993
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`July 6, 1993
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`Sheet 14 of 35
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`5,226,125
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`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 15 of 35
`
`5,226,125
`
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`

`
`U.S. Patent
`
`July 6, 1993
`
`2
`
`Sheet 16 of 35
`
`5,226,125
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`P010
`3020 III—I
`:
`14;
`5 :5
`_ ___ ____ __ —_ _
`__u
`3003
`'3 '3
`
`4
`
`II
`
`3018
`
`3019
`
`_
`
`
`V
`
`AUGN/
`DWCT
`
`Q»-
`
`V
`
`‘
`
`‘I
`
`3011
`
`3012
`
`3013
`G
`
`PACKET
`
`REQUEST
`
`INTERRUPTS
`
`PA KE,
`
`msmucnon
`
`PORT
`
`3004
`
`3006
`3005
`LOCAL
`GLOBAL
`ADDR/DATA ADDR/DATA
`
`
`
`FIG. 30
`
`TEXAS INSTRUMENTS EX. 1007 - 18/71
`
`TEXAS INSTRUMENTS EX. 1007 - 18/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 17 of 35
`
`5,226,125
`
`III I
`
`PROGRAM FLOW CONTROL UNIT
`
`I
`
`'I”E"31o7
`
`SYNC/£34
`
`5R31o8I
`
`LE3 3118
`
`"""‘I LE2:
`'
`117
`3102'
`—‘_
`\I LEIS115
`
`”‘3124II
`E33121
`“Z20 ”‘2:s123'I
`‘
`E13119
`LR‘3122I
`2—
`31' """""""
`(:4(3
`
`I
`
`IIIIII
`
`E5
`.332
`8%‘
`‘gs
`GU‘)
`
`LSA
`
`ssco
`
`SEG1
`
`V IPPPP
`I mu
`
`PPPP
`
`I I
`
`I
`.__.3114 IL
`3109
`
`I
`
`
`3101
`L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ..__..
`
`2
`L. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
`.
`3115
`n
`ADDRESS
`OPCODE/CACHE-MISS DATA
`
`'”IERR”PT5
`INSTRUCTION BUS
`
`CACHE-MISS
`HANDSHAKE
`
`FIC. 3 1
`
`TEXAS INSTRUMENTS EX. 1007 - 19/71
`
`El"1C7C3C5ZI"1
`
`—..A
`
`II III5
`
`:___313
`I
`
`III
`
`3011
`
`II
`
`TEXAS INSTRUMENTS EX. 1007 - 19/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 18 of 35
`
`5,226,125
`
`ADDRESS UNIT
`
`TEXAS INSTRUMENTS EX. 1007 - 20/71
`
`TEXAS INSTRUMENTS EX. 1007 - 20/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 19 of 35
`
`5,226,125
`
`IMMEDIATE
`
`I-. — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —.--‘
`|
`DATA UNIT
`
`GLOBAL LOAD
`
`LOCAL STORE
`
`LOCAL LOAD
`
`FIG. 34
`
`0
`smus REGISTER‘ (sa)
`31
`llIBMEfififlfllififlfiflliflflfiflflflflflilflll
`
`TEXAS INSTRUMENTS EX. 1007 - 21/71
`
`TEXAS INSTRUMENTS EX. 1007 - 21/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 20 of 35
`
`5,226,125
`
`SIMD’ PAUSE
`
`F]
`
`F
`
`A
`F
`
`Exb
`Anrn
`Fcm
`
`Enm
`
`Fwu
`
`.
`
`.
`
`.
`
`Fpc
`
`Fwp
`
`Etl
`A
`F
`
`E
`A
`F
`
`E
`A
`
`pc+1
`
`pc+1
`
`pc
`
`pc
`
`pc
`
`pc
`
`pc
`
`pc
`
`pc+1
`
`pc+1
`
`Fcm — CACHE-MISS
`Anrn — NO MASTER PHASE OF THE ADDRESS UNTT. THUS NO REGISTER MODIFY.
`Exb - CROSSBAR ACCESS(ES) OCCUR.
`STORES COMPLETE TO MEMORY.
`LOADS
`COMPLETE INTO TEMPORARY LATCHES. MASTER PHASE OF DATA UNIT
`OPERATIONS KIIJ.ED.
`Enm — NO MASTER PHASE OF DATA UNIT.
`Fwa - WAIT FOR CACHE-MISS ACKNOWLEDGE FROM TP.
`Fpc - TRANSFER PC AND SEGMBIT NUMBER TO TP
`Fwp - WAIT FOR SUBSEGMENT PRESENT FLAG TO BECOME SET.
`EtL - TEMPORARY LATCH DATA (LOADS COMPLETE INTO DESIGNATION REGISTER(S).
`DATA UNIT PERFORMS TTS ALU MPY OPERATIONS.
`
`I
`
`FIG. 36
`
`SIMD PAUSE
`
`pc+1
`
`pc+1
`
`pc+1
`
`pc
`
`EgL - CONTENTTON DETECTED ON BOTH GLOBAL AND LOCAL BUSES.
`PHASE IN DATA UNIT.
`PIPE NOT LOADED.
`Fnm - NO MASTER PHASE ON FETCH.
`Eg - CONTENTION DETECTED ON GLOBAL BUS.
`LOCAL BUS TRANSFER OCCURS.
`STORE TO MEMORY. OR LOAD TO TEMP REGISTER.
`NO MASTER PHASE IN
`DATA UNIT.
`EtL»- TEMPORARY LATCH DATA (LOADS) COMPLETE INTO DESTINATION REGISTER(S).
`DATA UNIT PERFORMS TIS ALU/MPY OPERATIONS.
`Anrn - NO MASTER PHASE IN ADDRESS UNTT. ADDRESS REGISTER NOT MODIFIED.
`
`NO MASTER
`
`TEXAS INSTRUMENTS EX. 1007 - 22/71
`
`TEXAS INSTRUMENTS EX. 1007 - 22/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 21 of 35
`
`5,226,125
`
`F
`
`A
`F
`
`E
`A
`Fso
`
`E
`A
`Fer
`
`E
`A
`Fso
`
`E
`A
`Fen
`
`E
`A
`F
`
`E
`A
`
`E
`
`pc+1
`
`lc=2
`pc+1
`c|d=1
`mld=1
`
`pc+1
`
`_
`
`pc=ea
`Ic<>1
`pc:=sa
`Ic:=Ic—1
`cId:=mId
`
`pc+1
`
`pc=eo
`Ic=1
`pc+1
`Ic:=lr
`c|d:=cId-1
`
`pc+1
`
`PC INCREMENTS NORMALLY.
`Fso - START ADDRESS OF LOOP.
`Fer — END ADDRESS, REPEAT LOOP.
`LOOP COUNTER NOT ONE. LOAD PC
`WITH START ADD.
`Fen - END ADDRESS. NO-REPETITION.
`INCREMENTS NORMALLY.
`
`LOOP COUNTER IS ONE.
`
`PC
`
`FIG. 3 7
`
`FIGS. 38
`
`I
`SIMD BRANCH—TAKEN
`
`
`
`LOAD PC WITH BRANCH ADDRESS.
`Epc - COPY PC+1 INTO RET.
`(EITHER Epr‘CAN PUSH THE RETURN ADDRESS).
`Epr - PUSH RET IF A CALL
`Fd1 - DELAY SLOT ‘I
`INSTRUCTION FETCH.
`Fd2 - DELAY SLOT 2 INSTRUCTION FETCH.
`Fba - FETCH INSTRUCTION FROM BRANCH ADDRESS.
`: — INIERRUPTS LOCKED OUT.
`
`TEXAS INSTRUMENTS EX. 1007 - 23/71
`
`TEXAS INSTRUMENTS EX. 1007 - 23/71
`
`

`
`U.S. Patent
`
`July 5, 1993
`
`Sheet 22 of 35
`
`5,226,125
`
`I
`I
`I
`I
`_
`I
`I
`_
`SIMD MASTER’ PP TO SLAVE PP INTERRUPT SIGNAL
`
`SIMD 'SLAVE' PP TO 'MASTER' PP INTERRUPT SIGNAL
`
`
`
`
`
`
`
`
`SIMD PAUSE INACTTVE
`
`“-
`
`F
`
`A
`F
`
`E
`A
`F
`Int
`
`E
`A
`Fpv
`
`Int
`IN
`SLAVE
`PP
`
`E
`Apv
`I-‘pr
`
`Epv
`Apr
`Fps
`
`Epr
`Aps
`$F'In
`
`Eps
`A
`SF
`
`E
`A
`
`E
`
`pc+1
`
`pc+1
`
`pc+1
`
`pc
`
`pc
`
`pc:=vec
`ret:=pc
`
`pc+1
`
`pc+1
`
`Int - INTERRUPT OCCURS.
`(PC TO RET. VECTOR FETCH INTO PC).
`Fpv - PSEUDO INSTRUCTTON.
`Apv - CALCULATE INTERRUPT VECTOR ADDRESS.
`Epv - COPY PC TO RET.
`FETCH INTRRUPT VECTOR INTO PC.
`Fpr - PSEUDO INSTRUCTTON.
`(PUSH RET).
`-
`Apr -' CALCULATE STACK PUSH ADDRESS.
`Epr - PUSH RET ONTO STACK.
`(PUSH SR).
`Fps - PSEUDO INSTRUCTTON.
`Aps - CALCULATE STACK PUSH ADDRESS.
`I AND CLD BITS IN SR.
`Eps - PUSH SR ONTO STACK.
`CLEAR S,
`Fin - FIRST INSTRUCTION OF INTERRUPT ROUTTNE.
`S - SYNC,
`INTERRUPTS AND LOOPING DISABLED UNTTL AFTER SR HAS BEEN PUSHED.
`NEITHER OF FIRST TWO INSTRUCTIONS OF INTERRUPT ROUTTNE MAY BE A LCK.
`
`FIG. 39
`
`TEXAS INSTRUMENTS EX. 1007 - 24/71
`
`TEXAS INSTRUMENTS EX. 1007 - 24/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 23 of 35
`
`5,226,125
`
`SIMD LMASTEIT PPITO "SLAVE PP's INIERRUPIT SIGNIAL
`
`
`
` SIMD SLA PP T0 'MASTER' PP INTERRUPT SIGNAL
`
`F
`
`A
`
`F
`
`E
`
`A
`FId
`
`Enm
`Exb
`Anm .
`.
`.
`Fnm .
`.
`.
`
`EtI
`A
`Fpv
`
`.
`.
`.
`Int
`
`.
`
`E
`Apv
`Fpr
`
`Int
`IN
`Slave
`PP
`
`Epv
`Apr
`Fps
`
`Epr
`Aps
`$F'In
`
`Eps
`A
`F
`
`E
`A
`
`pc+1pc+1pc+1
`
`pc
`
`pc
`
`pc
`
`pc
`
`pc
`
`pc
`
`pc+1
`
`Fid - IDLE INSTRUCTION FETCHED.
`PIPEUNE NOT LOADED.
`Fnm - NO MASTER PHASE ON INSTRUCTION FETCH.
`Anm - NO MASTER PHASE ON INSTRUCTION FETCH. ADDRESS REGISTERS NOT MODIFIED.
`Exb - CROSSBAR ACCESS(ES) OCCUR.
`STORES COMPLETE TO MEMORY.
`LOADS
`COMPLETE INTO TEMPORARY LATCHES. MASTER PHASE OF DATA UNIT OPERATIONS
`KILLED.
`
`Enm - NO MASTER PHASE IN DATA UNIT.
`'
`Int - INTERRUPT OCCURS.
`EtL - TEMPORARY LATCH DATA (LOADS COMPLETE INTO DESTINATION REGISTER(S).
`DATA UNIT PERFORMS ITS ALU MPY OPERATIONS.
`Fpv — PSEUDO INSTRUCTION.
`(PC To REI. VECTOR FETCH INTO PC).
`Apv — CALCULATE INTERRUPT VECTOR ADDR.
`Epv - cow PC TO REI.
`FETCH INTERRUPT VECTOR INTO PC.
`Fpr — PSEUDO INSTRUCTION.
`(PUSH RI-:r).
`Apr - CALCULATE STACK PUSH ADDRESS.
`Epr — PUSH RET omo smcx.
`(PUSH SR).
`Fps — PSEUDO INSTRUCTION.
`Aps - CALCULATE STACK PUSH ADDRESS.
`I AND cw arrs IN SR.
`Eps - PUSH SR omo STACK.
`CLEAR 5,
`I-"In — FIRST INSTRUCTION or INTERRUPT ROUTINE
`3 — smc,
`INTERRUPTS mo LOOPING DISABIJED UNTIL AFTER SR HAS BEEN PUSHED.
`NEITHER or FIRST TWO INSTRUCTIONS or INTERRUPT ROUIINE MAY as A LCK.
`FIG’. 40
`
`TEXAS INSTRUMENTS EX. 1007 - 25/71
`
`TEXAS INSTRUMENTS EX. 1007 - 25/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 24 of 35
`
`5,226,125
`
`FIG. 41
`
`I
`I
`INCOMING SYNC SIGNAL
`
`l"'l
`
`)>l'7'l
`
`A F
`
`Enm
`.
`.
`.
`Fns
`
`.
`.
`
`.
`.
`
`.
`.
`
`Etl
`A
`F
`
` F
`
`A
`F
`
`Exb
`Anrn
`Fns
`
`pc+1
`pc+1
`pc
`pc
`pc
`pc+1
`pc+1
`PC UNALTERED.
`PIPE NOTALOADED.
`Fns - NO SYNC CONDITION.
`Anrn - NO MASTER PHASE IN ADDRESS UNIT. ADDRESS REGISTERS NOT MODIFIED.
`Exb - CROSSBAR ACCESS(ES) OCCUR.
`STORES COMPLETE TO MEMORY.
`LOADS
`COMPLETE INTO TEMPORARY IATCHES. MASTER PHASE OF DATA UNIT
`OPERATIONS KIU.ED.
`Enm — NO MASTER PHASE IN DATA UNIT.
`EtL - TEMPORARY LATCH DATA (LOADS COMPLETE INTO DESIGNATION REGISTER(S).
`DATA UNTT PERFORMS ITS ALU MPY OPERATIONS.
`
`LOADS:
`
`(ASSUMING NO S|GN—EXTENSION)
`
`FIG. 42
`
`SOURCE DATA:
`
`BYTE NO.
`3 2 1 o
`
`0OOOh =
`00O4h =
`
`o c B A
`H c F E
`
`(MEMORY)
`
`DESTINATION
`
`=
`
`9 '2 ? 9
`
`(REGISTER)
`
`fl ADD.
`
`15-arr
`
`LoADs,__
`
`REG VALUE
`
`ADD.
`
`32-on
`
`|_oADs,__
`
`REG VALUE
`
`LD
`LDU
`
`LD
`LDU
`
`Lo
`LDU
`
`Lo
`LDU
`
`O000h OOBA
`OOO2h
`--—-
`
`OOBA
`OOBA
`
`--—B ???B
`O001h
`ooozm ooc— ooco
`
`OO02h oooc
`OOO4h
`--—-
`
`oooc
`oooc
`
`ooo3h ——-o
`OOO5h ooE-
`
`'.>?,?o
`ooEo
`
`U)
`Lou
`
`Lo
`LDU
`
`Lo
`LDU
`
`LD
`LDU
`
`ooooh~ocBA
`OO04h
`--—-
`
`DCBA
`DCBA
`
`?DCB
`0001h -oca
`O0O5h E--— EDCB
`
`OO02h --oc ??oc
`0O06h FE—-
`FEDC
`
`-—--o
`O00.‘5h
`O0O7h GFE-.
`
`???o
`GFED
`
`TEXAS INSTRUMENTS EX. 1007 - 26/71
`
`TEXAS INSTRUMENTS EX. 1007 - 26/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 25 of 35
`
`5,226,125
`
`STORES:
`
`SOURCE DATA; =
`
`D C B A
`
`(REGISTER)
`
`DESTTNATTON DATA; =
`
`3 2 1 0
`
`BYTENO.
`
`? ? ? ?
`OOO0h =
`O0O4h= ????
`
`(MEMORY)
`
`OP.
`
`ST
`
`ADD.
`
`sToREs...
`
`REG VALUE
`
`0OOOh DCBA
`
`STU
`
`OO04h —---
`
`DCBA
`????
`DCBA
`????
`
`91 ADD.
`
`sToREs...
`
`0004h
`
`ST
`
`OOO0h OOBA
`
`STU
`
`0OO2h —---
`
`??BA
`????
`??BA
`????
`
`ST
`
`STU
`
`ST
`
`STU
`
`ST
`
`STU
`
`0001b —--A— ??A?
`????
`?BA?
`????
`
`0003h —B--
`
`0OO2h -A--
`
`?A??
`????
`OOO4h B--- BA??
`????
`
`0003b A---— A???
`????
`O0O5h —-—B A???
`???B
`
`ST
`
`O0O1h CBA-
`
`STU
`
`00O5h
`
`CBA?
`????
`--—D CBA?
`???D
`
`ST
`
`STU
`
`ST
`
`STU
`
`0OO2h BA—- BA??
`'
`????
`--DC BA??
`??DC
`
`O0O6h
`
`0003b A-—— A???
`????
`-DCB A???
`?DCB
`
`0007h
`
`FIG. 43
`
`TEXAS INSTRUMENTS EX. 1007 - 27/71
`
`TEXAS INSTRUMENTS EX. 1007 - 27/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 26 of 35
`
`5,226,125
`
`ADD wrm SATURATE
`
`
`2
`
`MAXIMUM
`
`TRANSPARENCY
`
`ADDM
`MRGM
`
`D0. D1. 02
`D2, D3, D2
`
`susu
`MRGM
`
`D0, D1, D2
`D0. D1, D2
`
`cum D0, D1
`MRGM
`D0, D2, D3
`
`oo=a923cns7
`+01 = 01 AB 45 EF
`
`
`D0=892.'5CD67
`-D1 = o1 AB 45 EF
`
`no=a923cns7.
`(—)D1 = 23 23 23 23
`
`D2: = 8A cs 12 55
`MFLAGS: = 22 22 22 23
`
`D2: = as 6788 67
`MFl.AGS: = 22 22 22 25
`
`(= as 00 8A 44)
`MFl.AGS: = 22 22 22 24
`
`D2=8ACE1256
`D.'5=FFFFFFFF
`
`D0=8923CD67
`D1=O1AB45EF
`
`oo=a923cos7
`n2=s7e54321
`
`D2:=8ACEFFFF
`
`D2=89ABCDEF
`
`o3:=a9s5cos7
`
`COLOUR EXPANSION
`
`COLOUR COMPRESSION
`
`cunozo com
`
`LD mo, muss
`MRGM
`no, D1, D2
`.
`
`MFLAGS = xx xx xx xs
`
`oo=11111111
`D1 = 88 as 8888
`
`D2:=11888811
`
`cum D0, D1, D2
`
`D0 = 39 23 co 57
`(-)D1 = as 89 89 as
`
`emwum
`MFLAGS = 22 22 22 23
`
`'
`
`LD
`MRGM
`
`:AO, MFLAGS
`no, 01, D1
`
`MFLAGS = xx xx xx xc
`
`no=a923cos7
`D1 = 37 as 43 21
`
`D1:=87 55 CD 57
`
`Pun: or 512 1=1xELs—————-I
`
`"FIG. 45
`
`TEXAS INSTRUMENTS EX. 1007 - 28/71
`
`TEXAS INSTRUMENTS EX. 1007 - 28/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 27 of 35
`
`5,226,125
`
`TEXAS INSTRUMENTS EX. 1007 - 29/71
`
`TEXAS INSTRUMENTS EX. 1007 - 29/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 28 of 35
`
`5,226,125
`
`LINE
`
`
`
`4905
`
`
`OBJECT OR
`CCDIS
`DOCUMENT
`
`FOR COPYING
`
`
`
`
`
`
`
`
`PRINT ASSY
`OR ELEMENT
`4910
`X1 ‘
`
`
`copy on
`
`
`FACSIMILE
`PRODUCT
`
`
`
`
`
`4902
`
`coNrRoL
`coNsoLE
`
`I
`
`I
`
`I
`
`A
`
`
`
`4903
`
`I
`
`MEMORY
`ISP &
`
`
`
`49
`
`04
`
`IXD
`ACQUIETIION
`
`CONTROLLER
`
`I ENGINE
`
`IMAGE INFORMATION
`
`5007
`
`
`
`
`
`STATISTICAL
`ACCUMULATED
`ECORDKEEPIN .
`
`
`
`5008
`
`CONTROLLED
`MECHANISM
`
`5°09
`
`FIG. 50
`
`5010
`
`HOST PRINTER
`P0”
`FIG. 51
`I’ ‘ ’ ' ' ‘ ' ‘ ' - " ‘ ' ' -"
`
`FLAT
`PANEL
`
`ISP
`
`
`
`DISPLAY I 51 O1
`
`
`
`TEXAS INSTRUMENTS EX. 1007 - 30/71
`
`TEXAS INSTRUMENTS EX. 1007 - 30/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 29 of 35
`
`5,226,125
`
`
`
`PRINTER
`
`INTERFACE
`
`PRINTER
`
`MECHANIS
`
`5312
`
`5318
`
`uwxcmc
`
`GENERATOR
`
`
`
`ADDRESS
`
`
`5310
`‘T
`
`5314
`
`FIG. 53
`
`5322
`
`TEXAS INSTRUMENTS EX. 1007 - 31/71
`
`TEXAS INSTRUMENTS EX. 1007 - 31/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 30 of 35
`
`5,226,125
`
`o?‘4-‘-N) O) O
`-J (J!--FN) O)U’
`54360
`542§o
`30a E :543o
`U1->maxL»! 4-‘-O
`5432a 5434
`
`0|
`
`A
`3
`
`6
`
`-<
`
`K)
`
`5440
`
`
`
`
`
`U143(N O)-4 (J745N) O) O
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`TEXAS INSTRUMENTS EX. 1007 - 32/71
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`tHetaD;3U
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`July 6, 1993
`
`Sheet 31 of 35
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`5,226,125
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`TEXAS INSTRUMENTS EX. 1007 - 33/71
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`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 32 of 35
`
`5,226,125
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`32-Bf!’ADDRESSBUS
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`TEXAS INSTRUMENTS EX. 1007 - 34/71
`
`TEXAS INSTRUMENTS EX. 1007 - 34/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 33 of 35
`
`5,226,125
`
`mg GENERAL CASE
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`(PRIOR ART)
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`TEXAS INSTRUMENTS EX. 1007 - 35/71
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`TEXAS INSTRUMENTS EX. 1007 - 35/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`’
`
`Sheet 34 of 35
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`5,226,125
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`TEXAS INSTRUMENTS EX. 1007 - 36/71
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`TEXAS INSTRUMENTS EX. 1007 - 36/71
`
`

`
`U.S. Patent
`
`July 6, 1993
`
`Sheet 35 of 35
`
`5,226,125
`
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`TEXAS INSTRUMENTS EX. 1007 - 37/71
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`

`
`1
`
`SWITCH MATRIX HAVING INTEGRATED
`CROSSPOINT LOGIC AND METHOD OF
`OPERATION
`
`5,226,125
`
`TECHNICAL FIELD OF THE INVENTION
`
`This invention relates to switching matrices and more
`particularly to a system and method for constructing
`such a system with operational logic at each matrix
`crosspoint.
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`
`2
`ing on data from different sources. For different opera-
`tions, different configurations are necessary.
`Contention is a problem when several processors, or
`other devices, try to access the same memory space.
`Typically, a central processor or a standalone logic
`circuit, monitors the contending processors and allows
`one processor at a time to have access to a given mem-
`ory space. When time and space is at a premium, this is
`difficult to achieve. In addition, any standalone conten-
`tion system would require connections for moving data
`back and forth and thus would require space for the
`movement of this data thereby compounding the prob-
`lem.
`There is thus a need in the art for a system which
`handles multi-processors having multi-memories such
`that the address space from all of the memories is avail-
`able to one or more processors concurrently even when
`the processors are handling different instruction sets.
`There is a further need in the art for a multi-process-
`ing system which is constructed with a switch capable
`of allowing both SIMD and MIMD operations on an
`interchangeable basis.
`One method of solving the huge interconnection
`problem in complex systems such as the image process-
`ing system shown in one embodiment of the invention is
`to construct the entire processor as a single device.
`Conceptually this might appear easy to achieve, but in
`reality the problems are complicated.
`First of all, an architecture must be created which
`allows for the efficient movement of information while
`at the same time consuming a minmum amount of pre-
`cious silicon chip space in order to achieve a high per-
`formance to cost ratio. The architecture must allow a
`very high degree of flexibility since once fabricated, it
`cannot easily be modified for different applications.
`Also, since the processing capability of the system will
`be high, there is a need for high bandwidth of each data
`input/output signal which moves information on and
`off the chip. This is so since the physical number of
`leads which can attach to any one chip is limited.
`It is also desirable to design an entire parallel proces-
`sor system, such as an image processor, on a single
`silicon chip while maintaining the system flexible
`enough to satisfy wide ranging and constantly changing
`operational criteria.
`It is further desirable to construct such a single chip
`parallel processor chip where the processor memory
`interface is easily adaptable to operation in various
`modes, such as SIMD and MIMD, or both as well as
`adaptable to efficient on-off chip data communications.
`SUMMARY OF THE INVENTION
`
`These problems have been solved by designing a
`multi-processing system to handle image processing and
`graphics and by constructing a crossbar switch capable
`of interconnecting any processor with any memory in
`any configuration for the interchange of data. The sys-
`tem is capable of connecting it parallel processors to m
`memories where m is greater than n.
`The problems inherent with constructing a single
`chip image processor having a high degree of versatility
`have been solved by the architecture of establishing a
`multi-link, multi-bus crossbar switch between the indi-
`vidual processors and the individual memories. This
`architecture, coupled with the design of the high den-
`sity switch allows the system to perform in both the
`SIMD and MIMD modes and allows for full access of
`all processors to all memories. The crossbar switch is
`
`TEXAS INSTRUMENTS EX. 1007 - 38/71
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`All of the following patent applications are cross-
`referenced to one another, and all have been assigned to
`Texas Instruments Incorporated. These applications
`have been concurrently filed and are hereby incorpo-
`rated in this patent application by reference.
`
`U.S. Pat.
`Application
`Ser. No.
`Title
`
`437,591 Multi-Processor With Crossbar Link of
`Processors and Memories and Method of
`Operation
`SIMD/MIMD Reconfigurable Multi-Processor and
`Method of Operation
`Reconfigurable Communications for Multi-
`Processor and Method of Operation
`Reduced Area of Crossbar and Method of
`Operation
`Synchronized MIMD Multi-Processors, System
`and Method of Operation
`Sliced Addressing Multi-Processor and Method
`of Operation
`Ones Counting Circuit and Method of
`Operation
`437,851 Memory Circuit Reconfigurable as Data Memory
`or Instruction Cache and Method of Operation
`437,854 Imaging Computer and Method of Operation
`
`437,858
`
`437,856
`
`437,852
`
`437,853
`
`437,946
`
`437,857
`
`
`
`BACKGROUND OF THE INVENTION
`
`The concept of switching matrices is not new. For
`many years matrices have been used to interconnect
`telephone subscribers to one another and more recently
`they have been used to interconnect processors and
`memories in a computer processor system. In the pro-
`cessor world time and speed become critical. Thus,
`there is a constant effort to combine more and more
`processing power into less and less space.
`As this unrelenting push for small size and increased
`computing power continues, the interconnections be-
`tween system components become more and more so-
`phisticated. One example of the problem arises in imag-
`ing systems which obtain visual images and perform
`various manipulations with respect to the data and then
`control the display of the imaged and stored data inher-
`ently requiring large amounts of computations and
`memory. Such imaging systems are prime candidates
`for multi-processing where different processors per-
`form different
`tasks concurrently in parallel. These
`processors can be working together in the single in-
`struction, multiple data mode (SIMD) where all of the
`processors are operating from the same instruction but
`obtaining data from various sources, or the processors
`can be working together in the multiple instruction,
`multiple data mode (MIMD) where each processor is
`working from a different set of instructions and work-
`
`45
`
`50
`
`55
`
`65
`
`TEXAS INSTRUMENTS EX. 1007 - 38/71
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`

`
`5,226,125
`
`4
`FIGS. 24-27 show details of the sliced addressing
`technique;
`FIG. 28 shows details of the rearrangement of the
`instruction data memory for the SIMD/MIMD opera-
`tional modes;
`FIG. 29 shows details of a master processor;
`FIGS. 30-34 show details of the parallel processors;
`FIGS. 35-45 show figures useful in understanding
`methods of operation of the parallel processor;
`FIGS. 46-48 show an image processor operating as a
`personal computer;
`FIGS. 49-52 show system arrangements for use of
`the imaging system on a local and remote basis;
`FIG. 53 is a functional block diagram of an imaging
`system;
`FIG. 54 is a logic schematic of the ones counting
`circuit matrix;
`FIG. 55 is a logic schematic of a minimized matrix of
`the ones counting circuit;
`FIG. 56 is an example of an application of a ones
`counting circuit;
`FIG. 57 shows a block diagram of the transfer proces-
`sor;
`FIG. 58 shows a block diagram of the parallel proces-
`_sor system used with a VRAM; and
`FIGS. 59-64 show various operational mode rela-
`tionships.
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`Prior to beginning a discussion of the operation of the
`system, it may be helpful to understand how parallel
`processing systems have operated in the prior art.
`FIG. 5 shows a system having parallel processors
`50-53 accessing a single memory 55. The system shown
`in FIG. 5 is typically called a shared memory system
`where all of the parallel processors 50-53 share data in
`and out of the same memory 55.
`FIG. 6 shows another prior art system where mem-
`ory 65-68 is distributed with respect
`to processors
`60-63 on a one-for-one basis. In this type of system, the
`various processors access their respective memory in
`parallel and thus operate without memory contention
`between the processors. The system operating struc-
`tures shown in FIGS. 5 and 6, as will be discussed here-
`inafter, are suitable for a particular type of problem, and
`each is optimized for that type of problem. In the past,
`systems tended to be either shared or distributed.
`As processing requirements become m