IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`TEXAS INSTRUMENTS INCORPORATED,
`
`Petitioner,
`
`v.
`
`ADVANCED SILICON TECHNOLOGIES, LLC
`
`Patent Owner
`
`
`
`Case No. To Be Assigned
`
`Patent No. 8,933,945
`
`
`DECLARATION OF RICHARD GOODIN
`IN SUPPORT PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 8,933,945: CLAIMS 1-11 AND 21
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`TEXAS INSTRUMENTS EX. 1003 - 1/88
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`

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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`Declaration of Richard Goodin
`
`TABLE OF CONTENTS
`
`Background and Qualifications ...................................................................... 2
`
`State of the art and known technology pertaining to three-dimensional
`graphics rendering techniques as of November 2002 .................................... 6
`
`
`
`
`
`I.
`
`II.
`
`III. Overview of the ʼ945 Patent ......................................................................... 12
`
`A.
`
`B.
`
`C.
`
`Background of the ʼ945 Patent ........................................................... 12
`
`The solution – and purported invention – of the ʼ945 Patent is
`tile-based, screen partitioning ............................................................ 14
`
`The prosecution history of the ʼ945 Patent demonstrates tile-
`based, screen partitioning was known ................................................ 18
`
`1.
`
`2.
`
`3.
`
`U.S. Patent No. 5,794,016 (“Kelleher”) .................................. 18
`
`U.S. Patent No. 6,864,896 (“Perego”) ..................................... 19
`
`The ’945 Patent issued because the Board determined
`that the examiner did not address how Perego discloses a
`memory shared among the pipelines ....................................... 20
`
`IV. Level of Ordinary Skill ................................................................................. 21
`
`V.
`
`Claim Construction ....................................................................................... 21
`
`A.
`
`B.
`
`“repeating tile pattern” ....................................................................... 22
`
`“N×M number of pixels” .................................................................... 23
`
`VI. Summary of the Applied Prior Art References ............................................ 25
`
`A.
`
`B.
`
`The Balmer Patent .............................................................................. 25
`
`The Narayanaswami Patent ................................................................ 28
`
`1.
`
`Implementing Narayanaswami on Balmer .............................. 33
`
`C.
`
`Foley ................................................................................................... 35
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`Declaration of Richard Goodin
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`The Furtner Patent .............................................................................. 36
`
`The Kelleher Patent ............................................................................ 36
`
`
`
`D.
`
`E.
`
`VII. The Challenged Claims ................................................................................ 37
`
`A.
`
`Claims 1, 9, 10 and 21 using the combination of Balmer and
`Narayanaswami .................................................................................. 37
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`Rationale for combining Balmer and Narayanaswami ............ 37
`
`Claim 1 Preamble - “A graphics processing circuit:” .............. 41
`
`Claim 1 [1a] - “at least two graphics pipelines on a same
`chip” ......................................................................................... 42
`
`Claim 1 [1b] - “operative to process data in a
`corresponding set of tiles of a repeating tile pattern
`corresponding to screen locations,” ......................................... 45
`
`Claim 1 [1c] - “a respective one of the at least two
`graphics pipelines operative to process data in a
`dedicated tile; and”................................................................... 48
`
`Claim 1 [1d] - “a memory controller on the chip in
`communication with the at least two graphics pipelines,
`operative to transfer pixel data between each of a first
`pipeline and a second pipeline and a memory shared
`among the at least two graphics pipelines;” ............................. 49
`
`Claim 1 [1e] - “wherein the repeating tile pattern includes
`a horizontally and vertically repeating pattern of square
`regions.” ................................................................................... 51
`
`Claim 9 - “The graphics processing circuit of claim 1,
`wherein each tile of the set of tiles further comprises a
`16×16 pixel array. .................................................................... 53
`
`Claim 10 - “The graphics processing circuit of claim 1,
`wherein a second of the at least two graphics pipelines
`processes the data only in a second set of tiles in the
`repeating tile pattern.” .............................................................. 54
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
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`10. Claim 21 [Preamble] - “A graphics processing circuit:” ......... 54
`
`11. Claim 21 [21a] - “at least two graphics pipelines on a
`chip” ......................................................................................... 55
`
`12. Claim 21 [21b] - “operative to process data in a
`corresponding set of tiles of a repeating tile pattern
`corresponding to screen locations,” ......................................... 55
`
`13. Claim 21 [21c] - “a respective one of the at least two
`graphics pipelines operative to process data in a
`dedicated tile,” ......................................................................... 55
`
`14. Claim 21 [21d] - “wherein the repeating tile pattern
`includes a horizontally and vertically repeating pattern of
`square regions;” ........................................................................ 55
`
`15. Claim 21 [21e] - “wherein the horizontally and vertically
`repeating pattern of regions include NxM number of
`pixels; and ................................................................................ 56
`
`16. Claim 21 [21f] - “a memory controller on the chip,
`coupled to the at least two graphics pipelines on the chip
`and operative to transfer pixel data between each of the
`two graphics pipelines and a memory shared among the
`at least two graphics pipelines.”............................................... 57
`
`B.
`
`Claims 2 and 3 using the combination of Balmer,
`Narayanaswami and Furtner ............................................................... 58
`
`1.
`
`2.
`
`3.
`
`Rationale for Combining Balmer, Narayanaswami, and
`Furtner ...................................................................................... 58
`
`Claim 2 - “The graphics processing circuit of claim 1,
`wherein the square regions comprise a two dimensional
`partitioning of memory.” ......................................................... 59
`
`Claim 3 - “The graphics processing circuit of claim 2,
`wherein the memory is a frame buffer.” .................................. 60
`
`C.
`
`Claims 4-8 and 11 using the combination of Balmer,
`Narayanaswami and Foley ................................................................. 61
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`1.
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`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
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`8.
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`Declaration of Richard Goodin
`
`Rationale for Combining Balmer, Narayanaswami, and
`Foley ......................................................................................... 61
`
`Claim 4 [4a] - “The graphics processing circuit of claim
`1, wherein each of the at least two graphics pipelines
`further includes front end circuitry operative to receive
`vertex data and generate pixel data corresponding to a
`primitive to be rendered” ......................................................... 62
`
`Claim 4 [4b] - “and back end circuitry, coupled to the
`front end circuitry, operative to receive and process a
`portion of the pixel data.” ........................................................ 64
`
`Claim 5 [5a] - “The graphics processing circuit of claim
`4, wherein each of the at least two graphics pipelines
`further includes a scan converter, coupled to the back end
`circuitry, operative to determine the portion of the pixel
`data to be processed by the back end circuitry.” ..................... 66
`
`Claim 6 - “The graphics processing circuit of claim 4,
`wherein the at least two graphics pipelines separately
`receive the pixel data from the front end circuitry.” ................ 68
`
`Claim 7 - “The graphics processing circuit of claim 6,
`wherein a first of the at least two graphics pipelines
`processes the pixel data only in a first set of tiles in the
`repeating tile pattern.” .............................................................. 70
`
`Claim 8 [8a] - “The graphics processing circuit of claim
`7, wherein the first of the at least two graphics pipelines
`further includes a scan converter, coupled to the front end
`circuitry and the back end circuitry, operative to provide
`position coordinates of the pixels within the first set of
`tiles to be processed by the back end circuitry,” ..................... 71
`
`Claim 8 [8b] - “the scan converter including a pixel
`identification line for receiving tile identification data
`indicating which of the set of tiles is to be processed by
`the back end circuitry.” ............................................................ 73
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`9.
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`Declaration of Richard Goodin
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`Claim 11 [11a] - “The graphics processing circuit of
`claim 10, wherein the second of the at least two graphics
`pipelines further includes a scan converter, coupled to the
`front end circuitry and the back end circuitry, operative
`to provide position coordinates of the pixels within the
`second set of tiles to be processed by the back end
`circuitry,” ................................................................................. 75
`
`10. Claim 11 [11b] - “the scan converter including a pixel
`identification line for receiving tile identification data
`indicating which of the set of tiles is to be processed by
`the back end circuitry.” ............................................................ 75
`
`D.
`
`Claim 8 and 11 using the combination of Balmer,
`Narayanaswami, Foley and Kelleher ................................................. 76
`
`1.
`
`2.
`
`3.
`
`4.
`
`Rationale for combining Balmer, Narayanaswami, Foley,
`and Kelleher ............................................................................. 76
`
`Claim 8 [8a] - “The graphics processing circuit of claim
`7, wherein the first of the at least two graphics pipelines
`further includes a scan converter, coupled to the front end
`circuitry and the back end circuitry, operative to provide
`position coordinates of the pixels within the first set of
`tiles to be processed by the back end circuitry,” ..................... 77
`
`Claim 8 [8b] - “the scan converter including a pixel
`identification line for receiving tile identification data
`indicating which of the set of tiles is to be processed by
`the back end circuitry.” ............................................................ 77
`
`Claim 11 [11a] - “The graphics processing circuit of
`claim 10, wherein the second of the at least two graphics
`pipelines further includes a scan converter, coupled to
`front end circuitry and back end circuitry, operative to
`provide position coordinates of the pixels within the
`second set of tiles to be processed by the back end
`circuitry,” ................................................................................. 80
`
`5.
`
`Claim 11 [11b] - “the scan converter including a pixel
`identification line for receiving tile identification data
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`Declaration of Richard Goodin
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`indicating which of the set of tiles is to be processed by
`the back end circuitry.” ............................................................ 80
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`Declaration of Richard Goodin
`
`
`Richard M. Goodin, hereby declare and state as follows:
`
`I have been retained as a technical consultant on behalf of Texas
`
`I,
`
`1.
`
`Instruments Incorporated, the petitioner in the present proceeding, and I am being
`
`compensated at my usual and customary hourly rate. I understand that the petition
`
`names Texas Instruments Incorporated as the real party-in-interest. I have no
`
`financial interest in, or affiliation with, the petitioner, real parties-in-interest, or the
`
`patent owner, which I understand to be Advanced Silicon Technologies, LLC. My
`
`compensation is not dependent upon the outcome of, or my testimony in, the
`
`present inter partes review or any litigation proceedings.
`
`2.
`
`I have drafted, reviewed or provided from my own files each of the
`
`documents in the following table (which I am informed are also identified in the
`
`Petition):
`
`Exhibit
`Ex. 1001
`Ex. 1002
`Ex. 1004
`Ex. 1005
`Ex. 1006
`Ex. 1007
`Ex. 1008
`
`Ex. 1009
`
`Ex. 1010
`
`Ex. 1011
`
`Description
`U.S. Patent No. 8,933,945 (the “ʼ945 patent”)
`File History for U.S. Patent No. 8,933,945
`U.S. Patent No. 6,778,177 to Furtner (“Furtner”)
`U.S. Patent No. 5,794,016 to Kelleher (“Kelleher”)
`U.S. Patent No. 6,864,896 to Perego (“Perego”)
`U.S. Patent No. 5,226,125 to Balmer et al. (“Balmer”)
`U.S. Patent No. 5,757,385 to Narayanaswami et al.
`(“Narayanaswami”)
`James D. Foley et al., Computer Graphics: Principles and Practice,
`Second Edition in C, 1997 (“Foley”)
`Carl Mueller, “The Sort-First Rendering Architecture for High-
`Performance Graphics,” Proc. 1995 Sym. on Interactive 3D
`Graphics, Monterey, CA, Apr. 9-12, 1995, pp. 75-84 (“Mueller”)
`Scott Whitman, Multiprocessor Methods for Computer Graphics
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`Declaration of Richard Goodin
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`Description
`Rendering, 1992 (“Whitman”)
`Curriculum Vitae of Richard Goodin
`
`I understand that the application leading to the ʼ945 patent was
`
`Exhibit
`
`Ex. 1012
`
`3.
`
`Application No. 10/459,797, which was filed on June 12, 2003, which claimed
`
`priority to provisional application no. 60/429,641, filed on November 27, 2002.
`
`For purposes of my analysis, I assume the date of the purported invention to be
`
`November 27, 2002.
`
`I.
`
`Background and Qualifications
`
`4.
`
`My background, qualifications, and experience relevant to the issues
`
`in this proceeding are summarized below. My curriculum vitae (“CV”) is
`
`submitted herewith as Ex. 1012.
`
`5.
`
`As set forth in my CV, I have worked for over 35 years in the field of
`
`computer graphics and user interface technology, both graphics hardware and
`
`graphics software.
`
`6.
`
`I am currently the President and Chief Consultant of Goodin &
`
`Associates, Inc. I have worked or consulted for Fortune 500 companies such as
`
`Sperry Univac, Sun Microsystems, Apple Computer, Data General, Tektronix,
`
`Mitsubishi, and nVidia. I have worked in roles ranging from a Developer to Chief
`
`Scientist.
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`Declaration of Richard Goodin
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`My principal focus throughout my career has been in computer
`
`7.
`
`graphics, both hardware and software, in particular in generating photorealistic
`
`imagery. This involves familiarity and implementation of many high quality
`
`rendering algorithms and their implementation in graphics hardware.
`
`8.
`
`At 3Dfx Interactive, I architected and implemented the OpenGL API
`
`for the Voodoo and Banshee products and implemented the hardware VGA core
`
`for Banshee. At ULSI I architected one of the first 2D and 3D graphics
`
`accelerators using on chip embedded DRAM. At Mitsubishi, I was a memory
`
`technology advocate for graphics use of Mitsubishi’s CDRAM products.
`
`9.
`
`Prior to and concurrent with my work at Goodin & Associates, Inc., I
`
`have been employed by various entities in positions that involved computer
`
`graphics hardware and software. For instance, from November 2004 through
`
`October 2006, I was employed by Apple Computer, where I architected software
`
`and wrote code in Objective-C, C++, and C for 2D and 3D graphics at multiple
`
`levels of the OS X (OS ten) operating system during the transition to Intel
`
`processors.
`
`10.
`
`From January 1999 through October 1999, I was employed by
`
`Raydiant, Inc. as a Chief Scientist and lead hardware and software architect for
`
`advanced scalable PC graphics accelerator. My work at Radiant involved
`
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`architecture and design of high quality rendering algorithms and their hardware
`
`implementation.
`
`11.
`
`From April 1988 through January 1990, I was employed by Sun
`
`Microsystems as a Member of Technical Staff/Architect, where I co-architected
`
`and wrote code for the RenderMan compliant, high-quality 3D rendering
`
`component of Sun’s SunVision visualization product (SunART), which produced
`
`photo realistic images of automobiles used by car designers to make style
`
`decisions. I was a member of Pixar’s RenderMan Advisory Council. I also co-
`
`architected and wrote code for Sun’s XGL object oriented proprietary graphics
`
`library. While at Sun, I also wrote code for smaller projects such as the graphics
`
`library and windowing software for a multiprocessor, a visualization accelerator. I
`
`also ported SunPHIGS to Sun’s TAAC-1 application accelerator, and implemented
`
`the curve and surface extensions to the TAAC-1 graphics library.
`
`12.
`
`From November 1981 to March 1985, I was employed at Evans &
`
`Sutherland, where I reported directly to the Director of Advanced Development,
`
`and was responsible for evaluating rendering algorithms and hardware
`
`implementations for high performance commercial and military applications.
`
`13.
`
`From January 1979 to November 1981, I was employed by Sperry
`
`Univac GSD as a project engineer, where I designed hardware and wrote code for
`
`communications, display and other peripheral devices.
`
`4
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`Declaration of Richard Goodin
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`I am a Senior Member of the Institute of Electrical and Electronics
`
`14.
`
`Engineers (IEEE) and a Senior Member of the Association for Computing
`
`Machinery (ACM). The IEEE is a hardware society whose core purpose is to
`
`foster technological innovation and excellence for the benefit of humanity. For
`
`admission to the grade of Senior Member, a candidate shall be an engineer in
`
`IEEE-designated fields for a total of 10 years and have demonstrated 5 years of
`
`significant performance.
`
`15.
`
`The Association of Computing Machinery is the world’s largest
`
`educational and scientific computing society. Senior member is an earned
`
`membership grade awarded to approximately 25% of members who have
`
`demonstrated performance that sets them apart from their peers.
`
`16.
`
`I am a member of the ACM Special Interest Group for Graphics
`
`(SIGGRAPH) and I am a SIGGRAPH Computer Graphics Pioneer. SIGGRAPH
`
`Pioneer is an earned member category created by ACM SIGGRAPH, and is earned
`
`after twenty years of contributions to computer graphics and/or interactive
`
`techniques.
`
`17.
`
`As a result of my experience, I had personal knowledge of the types of
`
`graphics rendering systems, both software and hardware, in use as of November
`
`2002.
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
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`I am licensed as a Professional Engineer in the state of North
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`18.
`
`Carolina, Registration Number 036347. I am also a patent agent, registration
`
`number 63,323.
`
`II.
`
`State of the art and known technology pertaining to three-
`dimensional graphics rendering techniques as of November 2002
`
`19.
`
`In computer graphics the graphics pipeline defines a number of
`
`operations that takes a three dimensional scene and converts the scene into a two
`
`dimensional image, much like a digital camera, which takes an actual 3D scene and
`
`creates a 2D image. This process of converting the scene to an image is referred to
`
`as “rendering”, and can be generally converted into three classes of operations:
`
`“front-end”, “scan conversion” and “back-end”.
`
`20.
`
`The 3D scene is composed of mathematical entities know an
`
`“primitives.” The primitives, typically triangles, represent the surfaces of objects
`
`to be rendered. These triangles are positioned in a 3D coordinate system, known
`
`as world space, which represents the layout and composition of the 3D scene.
`
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
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`21.
`
`The figure above (Plate II.21) from Foley shows a single top and two
`
`side views of primitives representing a scene in world space. Ex. 1009, 6561.
`
`22.
`
`The “front-end” of the graphics pipeline takes the 3D primitives and,
`
`through mathematical computations, determines their position in the resulting
`
`digital image. This includes per vertex lighting, which was the most common form
`
`of lighting at the time. This 2D representation is referred to as screen space.
`
`
`1 Ex. 1009 page number citations are the pdf page numbers.
`
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`The figure above (Plate II.23) from Foley shows a perspective view of
`
`23.
`
`Plate II.21, above. This 2D representative is the equivalent of the scene in screen
`
`space. Ex. 1009, 656.
`
`24.
`
`The “scan conversion” operation takes these 2D primitive
`
`representations and converts them into 2D objects know as fragments. A typical
`
`fragment is composed of color, depth and position within the screen.
`
`8
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
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`25.
`
`Fig. 3.23 from Foley (shown above) shows the conversion of a
`
`polygon to fragments. Ex. 1009, 116.
`
`26.
`
`The “back-end” takes these fragments and converts them into a digital
`
`image composed of pixels. Back end processing also typically includes z buffering
`
`and alpha blending. A pixel is a single color value associates with a two
`
`dimensional position within the image. Plate II.32 is the final shutterbug image as
`
`the output of a graphics pipeline. Ex. 1009, 661.
`
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`Declaration of Richard Goodin
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`27.
`
`The graphics rendering process is what is known in the industry as
`
`“embarrassingly parallel.” This term is used in the computer community to
`
`describe processes that can be easily carved up and processed independently by
`
`multiple processors. When carving up tasks, such as the graphics pipeline, for
`
`parallel processing three factors are generally considered: input data, state, and
`
`output data.
`
`28.
`
`For the graphics pipeline, the input data is the primitives, usually
`
`triangles, as discussed above. Each primitive in the graphics pipeline can be
`
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
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`processed independently and is completely unrelated to every other primitive.
`
`Thus we could divide the entire scene into individual primitives and pass them out
`
`a primitive at a time to multiple processors. More typically, input primitives are
`
`grouped together as small blocks, each block being sent to a separate processor.
`
`29.
`
`For the graphics pipeline, output data is the pixels of the digital image.
`
`Pixels can be processed independently, with each processor performing all the
`
`calculations of the graphics pipeline for that pixel independently of any other pixel.
`
`Thus the processing task can be broken into individual pixels, or, more typically,
`
`into regions of pixels.
`
`30.
`
`For dividing the graphics pipeline task among multiple processors we
`
`must finally look at the state associated with the graphics pipeline. State is
`
`generally composed of attributes that either define the primitives or define how the
`
`graphics pipeline processes the primitives. The graphics pipeline state is also
`
`easily distributed across multiple processors. The graphics pipeline can be
`
`implemented in hardware or software, or just about any combination of both. As
`
`Foley states:
`
`
`Ex. 1009, 928.
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 8,933,945
`Declaration of Richard Goodin
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`At the start of my graphics career in the late 1970’s, most of the
`
`31.
`
`graphics pipeline was implemented in software, this software rendering to a
`
`hardware frame buffer. The evolution of graphics featured the consolidation of the
`
`graphics pipeline to the fixed functional pipeline of early OpenGL, first partially
`
`and eventually completely implemented in graphics hardware. In the current
`
`generation of graphics, hardware programmability has been reintroduced in the
`
`form of programmable shading. The history of graphics is replete with systems
`
`that mixed hardware and software in the graphics pipeline, using each where it
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`made the most sense in terms of performance and flexibility.
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`III. Overview of the ʼ945 Patent
`The ’945 patent “relates to graphics processing circuitry and, more
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`32.
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`particularly, to dividing graphics processing operations among multiple pipelines.”
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`Ex. 1001, 1:21-23. The ’945 patent states that conventional “graphics processing
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`systems typically include a host processor, graphics (including video) processing
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`circuitry, memory (e.g. frame buffer), and one or more display devices.” Id., 1:26-
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`30. The graphics processing circuitry generates pixel data, which is presented as
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`an object or a scene on the display screen. Id., 1:41-43
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`A. Background of the ʼ945 Patent
`In the Background section, the ’945 patent states that prior art systems
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`33.
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`“partitioned” the screen of a “conventional display device”—and “[i]n like manner,
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`the frame buffer”—into a series of vertical or horizontal “strips.” Id., 1:44-51.
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`The strips 13-18 are each “typically 1-4 pixels in
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`width.” Id., 1:46. Annotated Fig. 1 shows such a
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`display partitioned into vertical strips, each strip
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`assigned to a separate graphics processing circuit.
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`“To decrease processing time, . . . one graphics
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`processing circuit is responsible for one vertical strip
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`(e.g. 13) of the frame while another graphics processing circuit is responsible for
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`another vertical strip (e.g. 14) of the frame.” Id., 2:5-11.
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`34.
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`But, according to the ’945 patent, load balancing is a significant
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`drawback associated with the vertical (or horizontal) partitioning systems that use a
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`separate graphics processing circuit for each vertical strip. Id., 2:14-15. “Load
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`balancing problems occur, for example, when all of the primitives 20-23 [(e.g.,
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`triangles)] of a particular object or scene are located in one strip (e.g. strip 13) as
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`illustrated in FIG. 1.” Id., 2:15-18. “When this occurs, only the graphics
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`processing circuit responsible [for] strip 13 is actively processing primitives; the
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`remaining graphics processing circuits [(e.g., those responsible for strips 14-18,
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`above)] are idle.” Id., 2:18-22. The load imbalance amongst the graphics
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`processing circuits “results in a significant waste of computing resources,” id.,
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`2:22-23, and the ʼ945 patent acknowledges approaches, such as reduction in strip
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`width, and frame-based subdivision, have been employed to improve system
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`performance. Id., 2:27-49.
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`B.
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`The solution – and purported invention – of the ʼ945 Patent is tile-
`based, screen partitioning
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`35.
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`Rather than assigning graphics processing circuits to process data in
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`vertical or horizontal strips, the ʼ945 patent employs a conventional technique that
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`partitions the display (and frame buffer) into a horizontally and vertically
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`repeating pattern of regions, or tiles. Id., 3:25-26, 3:35-39, 5:48-49. Each
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`independent claim of the ʼ945 patent recites a “repeating tile pattern,” where the
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`repeating tile pattern includes a “horizontally and vertically repeating pattern of . . .
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`regions,” where graphics pipelines “process data in a corresponding set of tiles of a
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`repeating tile pattern.” Id., 9:66-10:1, 10:9-10, 12:1-2, 12:27-29. Annotated Fig. 3
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`(reproduced below) illustrates this approach:
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`Fig. 3 depicts partitioning the display into a repeating tile pattern of
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`36.
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`horizontal and vertical square tiles (or regions) 72-75. Id., 5:46-49. Each tile (or
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`region) in annotated Fig. 3 can be “implemented as a 16×16 pixel array.”2 Id.,
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`5:51-52. The repeating pattern of tiles (or regions) in the frame buffer corresponds
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`to the partitioning of the display into tiles (or regions). Id., 5:52-53. The
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`partitioning pattern is based on the number of and assignment of active graphics
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`pipelines to the horizontally and vertically arranged regions, and in a “two pipe
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`configuration, a ‘checkerboard’ pattern is created for the pipes and the patterns
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`repeat over the full screen.” Id., 8:58-62.
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`37.
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`The ’945 patent interchangeably uses the terms “tile” or “region,” see,
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`e.g., id., 3:26-31, 5:46-54, 7:47-49, when referring to a two-dimensional array of
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`pixels. A tile (or region) can be a square array of pixels (e.g., 8×8, 16×16, or
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`32×32 pixels) or a non-square array of pixels. Id., 8:42-45.
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`38.
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`As shown in annotated Fig. 3 (reproduced above), one graphics
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`processing circuit (or “graphics pipeline”) is responsible for tiles labeled “A,”
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`2 The ’945 patent interchangeably uses the terms “tile” or “region,” see, e.g., id.,
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`3:26-31, 5:46-54, 7:47-49, when referring to a two-dimensional array of pixels. A
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`tile (or region) can be a square array of pixels (e.g., 8×8, 16×16, or 32×32 pixels)
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`or a non-square array of pixels. Id., 8:42-45.
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`whereas a second graphics pipeline is responsible for tiles labeled “B.” Id., 5:45-
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`65. More precisely, “[w]hen rendering a primitive (e.g. triangle) 80, the first
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`graphics pipeline 101 processes only those pixels in portions 81, 82 of the
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`primitive 80 that intersects tiles labeled “A”, for example, 72 and 75” (Id., 5:54-57)
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`and “the second graphics pipeline 102 processes only those pixels in portions 83,
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`84 of the primitive 80 that intersects tiles labeled “B”, for example 73-74.” Id.,
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`5:60-63; Fig. 3.
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`39.
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`The ’945 patent specification explains how this assignment of
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`graphics pipelines to alternating horizontal and vertical tiles (or regions) addresses
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`the shortcoming over the prior art technique of assigning graphics processing
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`circuits to strips on the screen. Id., 5:66-6:9; see Id., 3:26-31 (explaining that the
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`subdivision of a frame buffer, coupled to multiple graphics pipelines, into a
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`replicating pattern of square regions (or tiles) such that “each region is processed
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`by a corresponding one” of the multiple graphics pipelines enhances load
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`balancing and texture cache utilization).
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`40.
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`In other embodiments, the ’945 patent employs a conventional
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`partitioning technique for more than two graphics pipelines. For example, Fig. 4
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`of the ’945 patent illustrates a frame buffer partitioned into a repeating pattern to
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`accommodate more than two graphics pipelines. Id., 6:10-1