IPR2016-01060
`U.S. Patent No. 8,933,945 B2
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`________________
`
`UNIFIED PATENTS INC.,
`Petitioner,
`
`v.
`
`ADVANCED SILICON TECHNOLOGIES LLC
`Patent Owner
`________________
`
`Case IPR2016-01060
`U.S. Patent No. 8,933,945 B2
`________________
`
`PATENT OWNER’S PRELIMINARY RESPONSE
`PURSUANT TO 37 C.F.R. § 42.107(a)
`
`

`
`IPR2016-01060
`U.S. Patent No. 8,933,945 B2
`
`TABLE OF CONTENTS
`
`IV.
`
`PAGE
`Introduction & Summary of Arguments..........................................................1
`I.
`The ’945 Patent Discloses Improved Graphics Pipelines ...............................3
`II.
`III. Unified’s Petition.............................................................................................7
`A.
`The Challenged Claims .........................................................................8
`B.
`The Asserted References.....................................................................10
`1.
`Narayanaswami.........................................................................10
`2.
`Perego........................................................................................13
`3.
`Seiler .........................................................................................15
`The Correct Claim Construction of Material Disputed Terms......................17
`A.
`The Controlling Claim Construction Standard ...................................17
`B.
`The Only Material Claim Construction Issue Facing the Board
`Is The Correct Construction of “memory controller” .........................19
`1.
`The correct construction of “memory controller” ....................19
`2.
`Unified provides no construction for “memory
`controller” and no support for its application of “memory
`controller” to Seiler...................................................................20
`a. Unified neither alleges nor proves that its implicit
`construction is the ordinary meaning of the claimed
`“memory controller” .........................................................21
`b. Unified neither alleges nor proves that its implicit
`construction is some purported special definition of the
`claimed “memory controller”............................................22
`The Remaining Claim Construction Dispute Is Not Material
`and Should Not Be Decided By the Board..........................................25
`All Challenged Claims: Seiler Cannot Cure The Admitted
`Deficiencies Of Perego And Narayanaswami ...............................................25
`A.
`Seiler Does Not Disclose The Claimed Memory Controller ..............26
`B.
`Unified Has Failed To Identify Evidence Sufficient To Meet Its
`Burden Of Proving That It Would Have Been Obvious To
`Combine Seiler With Either Perego Or Narayanaswami....................28
`
`C.
`
`V.
`
`ii
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`

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`1.
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`IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`2.
`
`Ground I: Unified Has Not Shown That It Would Have
`Been Obvious To Combine Seiler With Perego .......................29
`Ground II: Unified Has Not Shown That It Would Have
`Been Obvious To Combine Seiler With Narayanaswami ........31
`a. Unified identifies no explanation for how a person of
`ordinary skill would have combined Seiler and
`Narayanaswami .................................................................33
`b. Unified fails to establish a reasonable likelihood of proving
`why a person of ordinary skill would have combined
`Narayanaswami and Seiler................................................35
`VI. All Challenged Claims: Unified Has Failed To Meet Its Burden Of
`Identifying A Pipeline “operative to process data in a dedicated tile”..........37
`1.
`Unified Has Not Shown That Narayanswami Discloses A
`Pipeline “operative to process data in a dedicated tile”............38
`Unified Has Not Shown That Perego Discloses A
`Pipeline “operative to process data in a dedicated tile”............42
`VII. Dependent Claims 2 and 3: Unified Has Failed To Meet Its Burden Of
`Identifying “a two dimensional partitioning of memory”.............................44
`VIII. Conclusion .....................................................................................................46
`
`2.
`
`iii
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`IPR2016-01060
`U.S. Patent No. 8,933,945 B2
`
`TABLE OF AUTHORITIES
`
`Page(s)
`
`Cases
`ACTV, Inc. v. Walt Disney Co.,
`346 F.3d 1082 (Fed. Cir. 2003) ..........................................................................22
`
`Aventis Pharma S.A. v. Hospira, Inc.,
`675 F.3d 1324 (Fed. Cir. 2012) ....................................................................19, 23
`
`Becton, Dickinson and Co. v. One StockDuq Holdings, LLC,
`IPR2013-00235, Paper 30 (PTAB Sept. 25, 2014).......................................18, 23
`
`Ericcson, Inc. v. Intellectual Ventures I LLC,
`IPR2014-00921, Paper 8 (PTAB Dec. 16, 2014) .........................................18, 23
`
`Hill-Rom Services, Inc. v. Stryker Corporation,
`755 F.3d 1367 (Fed. Cir. 2014) ..............................................................18, 19, 23
`
`Hockerson-Halberstadt, Inc. v. Converse Inc.,
`183 F.3d 1369 (Fed. Cir. 1999) ..........................................................................22
`
`Intellectual Ventures Mgmt, LLC, v. Xilinx, Inc.,
`IPR2012-00019, Paper 33 (PTAB February 10, 2014) ......................................18
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) ..........................................................18
`
`Universal Remote Control, Inc. v. Universal Electronics, Inc.,
`IPR2013-00127, Paper 32 (PTAB June 30, 2014) .............................................18
`
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
`200 F.3d 795 (Fed. Cir. 1999) ............................................................................19
`
`Wellman, Inc. v. Eastman Chem. Co.,
`642 F.3d 1355 (Fed. Cir. 2011) ..........................................................................19
`
`Wowza Media Sys., LLC v. Adobe Systems Inc.,
`IPR2013-00054, No. 12 (PTAB Apr. 8, 2013)...................................................18
`
`iv
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`IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`Other Authorities
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`77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012) .........................................................17
`
`37 C.F.R. §100(b) ....................................................................................................17
`
`v
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`IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`TABLE OF EXHIBITS
`
`Exhibit
`2001
`
`Description
`Declaration of John C. Hart, Ph.D. In Support Of Patent Owner
`Advanced Silicon Technologies LLC’s Preliminary Response
`
`vi
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`

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`Case IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`I.
`
`Introduction & Summary of Arguments
`
`Unified’s Petition fails to establish the required likelihood that it will prove
`
`that the challenged claims of Advanced Silicon’s U.S. Patent No. 8,933,945 are
`
`unpatentable for at least the following reasons.
`
` Seiler cannot cure Perego’s and Narayanaswami’s admitted deficiencies
`
`Unified concedes that its primary references (Perego in Ground I and
`
`Narayanaswami in Ground II) fail to disclose a number of limitations found in
`
`every challenged claim, including the claimed “memory controller.” Unified
`
`argues that combining these references with the Seiler reference would cure these
`
`admitted deficiencies, but Unified’s argument must fail because:
`
`1. Under the correct construction of “memory controller”—and the only
`
`proposed construction before the Board—there is no evidence that Seiler
`
`discloses the “memory controller” admittedly missing from Perego and
`
`Narayanaswami; and
`
`2. As a threshold matter, Unified has failed to identify any evidence
`
`showing that it is likely to meet its burden of proving that it would have
`
`been obvious to combine Seiler with either Perego or Narayanaswami.
`
`Each of these failures provides an independent basis for denying Unified’s
`
`Petition in its entirety.
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`U.S. Patent No. 8,933,945 B2
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` graphics pipeline “operative to process data in a dedicated tile”
`
`Each challenged claim requires a graphics pipeline “operative to process
`
`data in a dedicated tile.” Unified’s Ground I asserts that Perego discloses this
`
`limitation, while Ground II asserts that it is disclosed by Narayanaswami. But
`
`Unified’s assertions are wholly unsupported: Unified has identified no claim
`
`construction for this term, and it has failed to identify any evidence that either
`
`Narayanaswami or Perego discloses any such pipeline. Instead, Unified merely
`
`argues that the purported pipelines are “assigned” to or “own” particular tiles,
`
`without actually addressing whether they are “operative to process data in a
`
`dedicated tile” as required by each challenged claim.
`
`This failure is yet another independent reason for denying the Petition in its
`
`entirety.
`
` “a two dimensional partitioning of memory”
`
`Finally, challenged dependent claims 2 and 3 each require “a two
`
`dimensional partitioning of memory.” Unified’s Ground I asserts that this
`
`limitation is taught by Perego, but improperly relies on Perego’s dividing of a
`
`graphical rendering surface, not of a memory. This failure of proof provides
`
`another reason the Petition should be denied with respect to challenged claims 2
`
`and 3.
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`U.S. Patent No. 8,933,945 B2
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`II.
`
`The ’945 Patent Discloses Improved Graphics Pipelines
`
`The ‘945 Patent is entitled “Dividing Work Among Multiple Graphics
`
`Pipelines Using a Super-Tiling Technique” and describes a “graphics processing
`
`circuit” consisting of multiple graphics pipelines on the same chip.
`
`When multiple graphics pipelines operate in parallel, an important goal for
`
`efficient graphics processing is “load balancing,” which means all of the graphics
`
`pipelines remain busy and none lay idle, such that the graphics processing unit can
`
`produce an image as quickly as possible. (See Hart Decl.1 ¶ 16.)
`
`The ‘945 Patent illustrates such parallel graphics pipelines in Figure 2,
`
`which has been reproduced below, and annotated using a red rectangle to identify
`
`one of the plurality graphics pipelines:
`
`1 Advanced Silicon is providing the Declaration of John C. Hart, Ph.D. In Support
`
`Of Patent Owner Advanced Silicon Technologies LLC’s Preliminary Response as
`
`Exhibit 2001.
`
`3
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`As depicted above, a graphics pipeline may contain front-end circuitry. Such
`
`front-end circuitry “generates the pixel data 36 by performing, for example,
`
`clipping, lighting, spatial transformations, matrix operations and rasterizing
`
`operations on the primitive data.” (’945 Patent2 at 4:39-42.) For example, the
`
`front end circuitry would convert the vertices of a triangle from their 3-D XYZ
`
`positions on the sphere to their corresponding 2-D XY positions on the display
`
`screen, as shown below. The “rasterizing operations” include computing vertex
`
`values useful for the next scan converter stage. (See Hart Decl. ¶ 18.)
`
`2 Unified previously provided the ’945 Patent as Exhibit 1001.
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`Z
`
`XYZ
`
`XYZ
`
`XYZ
`
`Y
`
`X
`
`XY
`
`XY
`
`X
`
`Y
`
`XY
`
`The graphics pipeline may also include a scan converter. “The scan
`
`converter 37 of the first graphics pipeline 101 receives the pixel data 36 and
`
`sequentially provides the position (e.g. x, y) coordinates 60 in screen space of the
`
`pixels to be processed by the back end circuitry 39[.]” (’945 Patent at 4:45-48.)
`
`For example, as shown below, a scan converter accepts a triangle described by
`
`three vertices and produces a collection of pixels designed to fill the triangle. (See
`
`Hart Decl. ¶ 19.)
`
`XY
`
`XY
`
`Y
`
`XY
`
`X
`The graphics pipeline may also include back-end circuitry. “Back end
`
`circuitry 39 may include, for example, pixel shaders, blending circuits, z-buffers or
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`any other circuitry for performing pixel appearance attribute operations (e.g. color,
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`texture blending, z-buffering) on those pixels located, for example, in tiles…”
`
`(’945 Patent at 4:66-5:3.) As illustrated below, the back end circuitry determines
`
`the colors of the pixels produced by the scan converter. (See Hart Decl. ¶ 20.)
`
`In order to provide better load balancing of the available graphics pipelines,
`
`the ‘945 Patent divides the screen up into tiles (below left), such that each tile can
`
`be assigned to one graphics pipeline for graphics processing. For example, as
`
`illustrated in below right, tiles shaded in red are assigned to one graphics pipeline
`
`while tiles shaded in blue are assigned to the other. (See Hart Decl. ¶ 21.)
`
`As illustrated below, the graphics pipelines are in communication with a
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`memory controller, which is operative to transfer pixel data between each of the
`
`pipelines and a shared memory. For example, as depicted below, memory
`
`controller 46 accepts pixels 43 and 44 generated by back end circuitry A 39 and B
`
`42 and writes pixels from both sources into the same graphics memory. This
`
`memory controller 46 may also manage the transfer of pixel data 49 and 50 from
`
`the shared graphics memory to the display 51 and back to the pipelines. (Hart
`
`Decl. ¶ 22.)
`
`III. Unified’s Petition
`
`Unified’s Petition asserts the following Grounds:
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`Ground
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`References
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`Basis
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`Challenged Claims
`
`I
`
`II
`
`Seiler and Perego
`
`§ 103(a)
`
`1-3, 9, 10, and 21
`
`Narayanaswami and Seiler
`
`§ 103(a)
`
`1, 9, 10, and 21
`
`These Grounds overlap substantially, with each Ground challenging claims
`
`1, 9, 10, and 21. Despite this redundancy, United has not even asserted, much less
`
`established, the required meaningful distinction between its overlapping Grounds.
`
`Therefore, as a threshold matter, a redundancy rejection is appropriate. See, e.g.,
`
`ScentAir Techs., Inc. v. Prolitec, Inc., IPR2013-00180, Paper 18 at 3 (PTAB Aug.
`
`26, 2013) (“To avoid a determination that a requested ground of review is
`
`redundant of another requested ground, a petitioner must articulate a meaningful
`
`distinction.”); LaRose Industries, LLC, et al. v. Cipriola Corp., IPR2013-00120,
`
`Paper 20 at 4 (PTAB Jul. 22, 2013).
`
`A.
`
`The Challenged Claims
`
`Unified challenges independent claim 1, its dependent claims 2-3, 9, 10, and
`
`independent claim 21. As illustrated by exemplary claim 1 reproduced in full
`
`below, each challenged claim describes a graphics processing circuit having at
`
`least two graphics pipelines, at least one of which can “process data in a dedicated
`
`tile.” The claims additionally require a “memory controller” that is operative “to
`
`transfer pixel data between each of” the first pipeline, the second pipeline, and a
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`memory shared by the two. The claims further require that the pipelines and the
`
`memory controller be on the “same chip.”
`
`A graphics processing circuit, comprising:
`1.
`least two graphics pipelines on the same chip
`at
`operative to process data in a corresponding set of tiles of a
`repeating tile pattern corresponding to screen locations, a
`respective one of
`the at
`least
`two graphics pipelines
`operative to process data in a dedicated tile; and
`a memory controller on the chip in communication
`with the at least two graphics pipelines, operative to transfer
`pixel data between each of a first pipeline and a second
`pipeline and a memory shared among the at least two graphics
`pipelines;
`wherein the repeating tile pattern includes a horizontally
`and vertically repeating pattern of square regions.
`
`(’945 Patent at claim 1 (emphasis added); see also claims 2-3, 9, 10, 21.)
`
`Also relevant to this Preliminary Response are the additional limitations of
`
`dependent claim 2. Challenged claim 2 depends from claim 1 and adds the
`
`requirement of a partitioning of memory:
`
`The graphics processing circuit of claim 1, wherein
`2.
`the square regions comprise a two dimensional partitioning of
`memory.
`
`(’945 Patent at claim 2.)
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`B.
`
`The Asserted References
`
`Narayanaswami
`1.
`Narayanaswami3 is directed to a graphics processing circuit and in
`
`particular, a method and apparatus for managing a graphical workload across
`
`multiple processors. (See Hart Decl. ¶¶ 30-32.) Narayanaswami is designed to
`
`provide a “computer graphics systems” capable of rendering multiple objects into a
`
`frame buffer with the purpose of displaying those objects as quickly as possible.
`
`(Narayanaswami at 1:15-17.) (See Hart Decl. ¶¶ 31 and 33.) Narayanaswami was
`
`purportedly designed to respond to a rendering process that had become “more
`
`complex and computationally intensive as users demand more detailed results
`
`using more objects rendered more quickly, including providing realtime motion,
`
`while using more computationally intensive processing techniques such as color,
`
`texture, lighting, transparency and other rendering techniques.” (Id. at 1:17-24.)
`
`(See Hart Decl. ¶ 32.)
`
`Narayanaswami describes graphics adapter processors 220, depicted in Fig.
`
`1 below. (See Hart Decl. ¶ 34.) Unified asserts that each of these processors is one
`
`of the claimed “graphics pipelines.” (Pet. at 61.)
`
`3 Unified previously provided the Narayanaswami reference as Exhibit 1004.
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`Narayanaswami describes (and illustrates in Fig. 6 below) the preferred
`
`method steps to be performed by each processor: “FIG. 6 is a flowchart illustrating
`
`a preferred method for each processor to handle the graphics workload while
`
`determining ownership of pixels or regions. (See Hart Decl. ¶ 35.) This process
`
`may be executed concurrently and in parallel by all processors.” (Narayanaswami
`
`at 6:66 – 7:3.) (See Hart Decl. ¶ 35.)
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`As depicted in Figure 6 and the accompanying description, each
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`Narayanaswami processor processes all pixels, whether they are in a particular
`
`region or not. (Narayanaswami at 7:21-28.) (See Hart Decl. ¶ 36.) To illustrate,
`
`step 610 of Narayanaswami requires each processor to scan convert the subobject.
`
`(See id.) Narayanaswami describes the processor as completing this step before
`
`determining which pixels are “owned by the processor,” resulting in the processor
`
`scan converting and processing all of the pixels, not just those in a particular
`
`region:
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`In step 615, the subobject is then scan converted into
`pixels, In step 620, each pixel is checked to see if it is owned by
`the processor by comparing the identifier of the processor with
`the identifier stored in the pixel ownership buffer or the region
`ownership list for that pixel.
`If yes in step 620, indicating that the processor owns the
`pixel, then the processer processes the pixel.
`
`(Id. at 7:21-28.) (See Hart Decl. ¶ 36.)
`
`Perego
`2.
`Perego4 discloses a system architecture that “provid[es] scalability option to
`
`higher levels of aggregate memory bandwidth.” (Perego at 2:53-57.) (See Hart
`
`Decl. ¶ 27.) As illustrated In Figure 3 below, in Perego, “a system has been
`
`described that provides multiple discrete memory modules coupled to a common
`
`memory controller. Each memory module includes a computing [or ‘rendering’]
`
`engine and a shared memory.” (Perego, col. 7:35-42. ) (See Hart Decl. ¶ 26.)
`
`Unified asserts that each engine is one of the claimed “graphics pipelines.” (E.g.,
`
`Pet. at 37).
`
`4 Unified previously provided the Perego reference as Exhibit 1003.
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`Perego’s scalable architecture is the key feature of Perego’s invention. (See
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`Hart Decl. ¶ 27.) As a result, Perego does not use a memory shared among
`
`different pipelines operating in parallel. (See id. ¶ 28.) Rather, as illustrated in
`
`Figure 3 above, each rendering engine 312 has a dedicated memory that it shares
`
`with the CPU/Memory Controller 302 but not with any other rendering engines
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`312. (E.g., Perego at 4:53-57.) (See Hart Decl. ¶ 26.) Perego’s use of dedicated
`
`memory for each rendering engine is the essence of Perego’s purported innovation:
`
`by having a dedicated memory for each rendering engine/module, Perego is able to
`
`achieve its goal of providing a scalable modular system in which individual
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`engines/modules can be added or removed as needed. (See Perego at 2:61-65.)
`
`(See Hart Decl. ¶ 27.)
`
`In addition to teaching away from the claimed shared memory, Perego also
`
`fails to disclose a pipeline that is “operative to process data in a dedicated tile” as
`
`required by each of the challenged ’945 Patent claims. (See Hart Decl. ¶ 28-29.)
`
`Although Perego states generally that certain tiles may be assigned to a particular
`
`rendering engine, Perego does not describe how this assignment and any
`
`corresponding processing is done. (See Perego at 5:19-27.) (See Hart Decl. ¶ 29.)
`
`Perego does not describe a system in which a rendering engine only processes the
`
`pixels in the particular tile or tiles assigned to that engine. (See id.)
`
`Nor is such a system inherent in light of the assignment described in Perego
`
`because such assignment can be achieved without the rendering engines only
`
`processing the pixels in a particular tile. (See Hart Decl. ¶ 30.) For example, as
`
`described below, the Narayanaswami reference describes a system in which the
`
`rendering of certain tiles is assigned to a particular processor, but each processor
`
`processes pixel data that is not within the tiles assigned to that processor. (See id.)
`
`3.
`
`Seiler
`
`Unified’s Grounds I and II attempt to rely on the Seiler reference to provide
`
`the claim limitations that United concedes are not disclosed by Perego or
`
`Narayanaswami, including the claimed “memory controller,” the claimed “memory
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`shared among the at least two graphic pipelines,” and the pipelines and memory
`
`controller being “on a same chip.” (Pet. at 17-18 and 68-69.)
`
`Seiler5 discloses a specialized system used for volume rendering, e.g. for
`
`medical data imaging of CT and MRI scan data stored as a 3-D voxel array. (See
`
`e.g., Seiler ¶¶ 3 and 10-12.) While competitive graphics processors like
`
`Narayanaswami would have used specialized circuity including a scan converter
`
`and a texture unit (for example, Narayanaswami at 1:22 and 38-39), Seiler used an
`
`alternative to scan conversion known as ray casting. (Seiler ¶ 6.) (See Hart Decl. ¶
`
`23.) Ray casting determines for each pixel, which triangle(s) affect it, and is
`
`viewed as the inverse approach of scan conversion. (See Hart Decl. ¶ 23.)
`
`Seiler describes a “memory interface 210 [that] implements all accesses to
`
`the rendering memory 160, arbitrates the requests of the bus logic 220 and the
`
`controller 400, and distributes array data across the modules and the rendering
`
`memory 160 for high bandwidth access and operation.” (Seiler ¶ 16.) Seiler does
`
`not describe memory interface 210 as transferring processed pixel data (or any
`
`data) from one pipeline to another. (See Hart Decl. ¶ 25.)
`
`For example, Seiler’s Figure 2 (reproduced below) shows that memory
`
`interface 210 acts as an interface for data transfers between rendering memory 160,
`
`5 Unified previously provided the Seiler reference as Exhibit 1002.
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`on the other hand, and either the bus logic 220 or controller 400, on the other.
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`Figure 2 and the Seiler reference does not describe or depict memory interface 210
`
`as transferring data from one pipeline to another. (See Hart Decl. ¶ 25.)
`
`IV. The Correct Claim Construction of Material Disputed Terms
`
`The Controlling Claim Construction Standard
`A.
`The broadest reasonable interpretation standard applies in an inter partes
`
`review of a patent that, like the ‘945 Patent, will not expire prior to the Final
`
`Written Decision. 37 C.F.R. §100(b); Office Patent Trial Practice Guide, 77 Fed.
`
`Reg. 48,756, 48,766 (Aug. 14, 2012). Applying the broadest reasonable
`
`interpretation, claim terms are given their ordinary and customary meaning, as
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`would be understood by a person of ordinary skill in the art at the time of the
`
`invention, in light of the language of the claims, the specification, and the
`
`prosecution history of the record. E.g., Wowza Media Sys., LLC v. Adobe Systems
`
`Inc., IPR2013-00054, No. 12 at 5 (PTAB Apr. 8, 2013); Intellectual Ventures
`
`Mgmt, LLC, v. Xilinx, Inc., IPR2012-00019, Paper 33 at 9 (PTAB February 10,
`
`2014); see also Phillips v. AWH Corp., 415 F.3d 1303, 1313-1317 (Fed. Cir. 2005)
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`(en banc); Hill-Rom Services, Inc. v. Stryker Corporation, 755 F.3d 1367, 1371
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`(Fed. Cir. 2014).
`
`Under this test, “[t]here is a “heavy presumption’ that a claim term carries its
`
`ordinary and customary meaning.” See Intellectual Ventures, IPR2012-00019,
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`Paper 33 at 9; Wowza, IPR2013-00054, No. 12 at 6; Universal Remote Control,
`
`Inc. v. Universal Electronics, Inc., IPR2013-00127, Paper 32 at 6 (PTAB June 30,
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`2014). This heavy presumption is overcome in specific and limited circumstances:
`
`a claim term may be construed contrary to its ordinary meaning only where there is
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`clear and unambiguous evidence that the patentee, as lexicographer, provided a
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`special definition for the claim term, or the patentee otherwise disavowed the full
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`scope of the claim term either in the specification or during prosecution. Ericcson,
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`Inc. v. Intellectual Ventures I LLC, IPR2014-00921, Paper 8, at 8 (PTAB Dec. 16,
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`2014); Becton, Dickinson and Co. v. One StockDuq Holdings, LLC, IPR2013-
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`00235, Paper 30 at 6 (PTAB Sept. 25, 2014); see also Aventis Pharma S.A. v.
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`Hospira, Inc., 675 F.3d 1324, 1330 (Fed. Cir. 2012); Hill-Rom, 755 F.3d at 1371.
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`B.
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`The Only Material Claim Construction Issue Facing the Board Is
`The Correct Construction of “memory controller”
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`The Board should only construe terms to the extent such construction is
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`necessary to resolve a controversy material to the Petition. See, e.g., Wellman, Inc.
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`v. Eastman Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir. 2011); Vivid Techs., Inc. v.
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`Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). Based on the Petition
`
`and this Response, the only material claim construction issues currently facing the
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`Board concerns the terms “memory controller.”
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`1.
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`The correct construction of “memory controller”
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`The claimed “memory controller” is a limitation of every challenged claim.
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`For example, each challenged claim requires:
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`a memory controller … operative to transfer pixel data between each
`of a first pipeline and a second pipeline and a memory shared among
`the at least two graphics pipelines.
`
`(’945 Patent at independent claim 1, independent claim 21.)
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`Consistent with the plain and ordinary meaning of the foregoing explicit
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`claim language, the claimed “memory controller” should be construed to mean a
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`“logic circuit operative to transmit and receive processed pixel data to and from the
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`first pipeline, the second pipeline, and the first and second pipelines’ shared
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`memory.”
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`2.
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`Unified provides no construction for “memory controller”
`and no support for its application of “memory controller”
`to Seiler
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`The claimed “memory controller” is a key limitation; indeed, Unified relies
`
`on Seiler primarily because it admits that the “memory controller” is missing from
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`each of its primary references, Perego and Narayanaswami. (Pet. at 17 and 58.)
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`Despite this focus on “memory controller,” Unified’s Petition fails to provide any
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`claim construction for the term. Instead, Unified just generally asserts that the
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`term should be given its “broadest reasonable interpretation” without identifying
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`what Unified contends that “broadest reasonable interpretation” actually is. (Pet. at
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`19.) This failing alone means that Unified has not met its burden of proof and
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`Unified’s Petition should be denied. See Jiawei Tech. (HK) Ltd. v. Richmond,
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`IPR2014-00938, Paper 20 at 17 (PTAB Dec. 16, 2015) (it “is Petitioner’s burden to
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`explain how the challenged claims are to be construed and how they read on the
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`prior art.”).
`
`According to Unified’s summary of the ‘945 Patent, the “[m]emory
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`controller 46 controls the flow of data to the memory 48.” (Pet. at 8.) But to the
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`extent this is deemed an attempt to implicitly construe “memory controller,”
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`Unified’s Petition presents no analysis or evidence supporting its attempt to
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`broaden the meaning of the claimed “memory controller” to something that simply
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`controls the flow of data to a memory. (Pet. at 8.) For example, Unified does not
`
`state that it is applying the ordinary meaning of the claimed “memory controller”
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`nor does it allege that the term should be based on some special definition
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`purportedly provided in the ’945 Patent. (Id.) It also fails to support either such
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`possible theory. Unified has therefore failed to meet its burden on this limitation
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`and, as a result, on its entire Petition.
`
`a.
`
`Unified neither alleges nor proves that its implicit
`construction is the ordinary meaning of the claimed
`“memory controller”
`
`Unified’s implicit construction is not the ordinary meaning and it does assert
`
`otherwise. (Pet. at 18-20). Nor could Unified reasonably assert that its implicit
`
`construction is the ordinary meaning because the plain language of the claims
`
`explicitly states that the claimed memory controller is “operative to transfer pixel
`
`data between each of a first pipeline and a second pipeline and a memory shared
`
`among the at least two graphics pipelines.” (’945 Patent at independent claim 1,
`
`dependent claims 2-11, and independent claim 21) (emphasis added.)
`
`Unified’s implicit construction ignores the ordinary meaning of this explicit
`
`claim language, requiring merely that the memory controller transfer data to and
`
`from a memory, while ignoring the additional requirements concerning the claimed
`
`first and second pipelines. (See e.g., Pet. at 21-22 and 44.) This is improper as a
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`matter of law. See, e.g., Hockerson-Halberstadt, Inc. v. Converse Inc., 183 F.3d
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`1369, 1374 (Fed. Cir. 1999) (“proper claim construction ... demands interpretation
`
`of the entire claim in context, not a single element in isolation.”); ACTV, Inc. v.
`
`Walt Disney Co., 346 F.3d 1082, 1088 (Fed. Cir. 2003) (“While certain terms may
`
`be at the center of the claim construction debate, the context of the surrounding
`
`words of the claim also must be considered....”).
`
`In contrast, Advanced Silicon’s proposed construction is consistent with and
`
`based on the plain and ordinary meaning of the explicit claim language requiring
`
`that the memory controller be operative between the shared memory and between
`
`the first and second pipelines. Under Advanced Silicon’s proposed construction,
`
`“the claimed memory controller” is a “logic circuit operative to transmit and
`
`receive processed pixel data to and from the first pipeline, the second pipeline,
`
`and the first and second pipelines’ shared memory.”
`
`b.
`
`Unified neither alleges nor proves that its implicit
`construction is some purported special definition of
`the claimed “memory controller”
`
`Unified’s implicit construction also is not based on some special definition
`
`provided in the ’945 Patent, and Unified does assert otherwise. (Pet. at 18-20.)
`
`Unified cites to no passages from the ’945 Patent’s specification that would
`
`support limiting the claimed “memory controller” to something that only transfers
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`data to and from a memory. Indeed, Unified does not even argue that there was
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`any clear and unambiguous special definition or disavowal, much less prove one.
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`(Pet. at 16-18.) Therefore, “memory controller” must be construed to have its
`
`ordinary meaning. Ericcson, Inc. v. Intellectual Ventures I LLC, IPR2014-00921,
`
`Paper 8, at 8 (PTAB Dec. 16, 2014); Becton, Dickinson and Co. v. One StockDuq
`
`Holdings, LLC, IPR2013-00235, Paper 30 at 6 (PTAB Sept. 25, 2014); see also
`
`Aventis Pharma S.A. v. Hospira, Inc., 675 F.3d 1324, 1330 (Fed. Cir. 2012); Hill-
`
`Rom, 755 F.3d at 1371.
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`Indeed, this ordinary meaning and Advanced Silicon’s corresponding
`
`proposed construction are consistent with the manner in which the ʼ945 Patent uses
`
`the term “memory controller.” The ’945 Patent’s specification describes that each
`
`pipeline includes back end circuitry for processing pixel data. (’945 Patent at 4:5-
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`15, 4:66 – 5:7, 5:28-36.) As illustrated in Fig. 2 (reproduced below), the
`
`specification describes pipeline 101 including back end circuitry 39 and pipeline
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`102 as including back end circuitry 42.