IPR2016-01060 Petition
`Patent 8,933,945
`
`DOCKET NO.: 2211726-00125
`Filed on behalf of Unified Patents Inc.
`By: David L. Cavanaugh, Reg. No. 36,476
`Daniel V. Williams 45,221
`Wilmer Cutler Pickering Hale and Dorr LLP
`1875 Pennsylvania Ave., NW
`Washington, DC 20006
`Tel: (202) 663-6000
`Email: David.Cavanaugh@wilmerhale.com
`
`Jonathan Stroud, Reg. No. 72,518
`Unified Patents Inc.
`1875 Connecticut Ave. NW, Floor 10
`Washington, DC, 20009
`Tel: (202) 805-8931
`Email: jonathan@unifiedpatents.com
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________________________________
`
`UNIFIED PATENTS INC.
`Petitioner
`
`v.
`
`ADVANCED SILICON TECHNOLOGIES, LLC
`Patent Owner
`
`IPR2016-01060
`Patent 8,933,945
`
`PETITION FOR INTER PARTES REVIEW OF
`US PATENT NO. 8,933,945
`CHALLENGING CLAIMS 1-3, 9, 10, AND 21
`UNDER 35 U.S.C. § 312 AND 37 C.F.R. § 42.104
`
`
`
`

`
`TABLE OF CONTENTS
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`IPR2016-01060 Petition
`Patent 8,933,945
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`Page
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`I. 
`
`MANDATORY NOTICES ............................................................................. 1 
`
`A. 
`B. 
`C. 
`D. 
`
`Real Party-in-Interest ............................................................................ 1 
`Related Matters ...................................................................................... 1 
`Counsel .................................................................................................. 2 
`Service Information, Email, Hand Delivery and Postal ........................ 2 
`
`II. 
`
`CERTIFICATION OF GROUNDS FOR STANDING .................................. 2 
`
`III.  OVERVIEW OF CHALLENGE AND RELIEF REQUESTED .................... 2 
`
`A. 
`
`Prior Art Patents and Printed Publications ............................................ 3 
`
`1. 
`
`2. 
`
`3. 
`
`European Patent Application No. 1 195 717 (filed on August
`21, 2001 based on priority date of October 4, 2000;
`published on April 10, 2002) (“Seiler” (EX1002)), which is
`prior art under 35 U.S.C. § 102(a) .............................................. 3 
`US Pat. 6,864,896 (filed on May 15, 2001; published on
`November 21, 2002) (“Perego” (EX1003)), which is prior
`art under 35 U.S.C. § 102(e) ....................................................... 3 
`US Pat. 5,757,385 (filed on January 30, 1996, claiming
`priority to July 21, 1994; published on May 26, 1998)
`(“Narayanaswami” (EX1004)), which is prior art under 35
`U.S.C. § 102(b) ........................................................................... 3 
`
`B. 
`
`Grounds for Challenge .......................................................................... 3 
`
`IV.  TECHNOLOGY BACKGROUND ................................................................. 4 
`
`V.  OVERVIEW OF THE ’945 PATENT ............................................................ 8 
`
`A. 
`B. 
`C. 
`
`Summary of the Alleged Invention ....................................................... 8 
`Level of Ordinary Skill in the Art ....................................................... 12 
`Prosecution History ............................................................................. 12 
`
`VI.  CLAIM CONSTRUCTION .......................................................................... 18 
`
`A. 
`
`“graphics pipeline” .............................................................................. 19 
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`IPR2016-01060 Petition
`Patent 8,933,945
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`VII.  SPECIFIC GROUNDS FOR PETITION ...................................................... 20 
`
`A.  Ground I: Claims 1-3, 9, 10, and 21 are rendered obvious by Seiler in
`view of Perego .................................................................................... 20 
`
`Overview of Seiler .................................................................... 20 
`1. 
`Overview of Perego .................................................................. 29 
`2. 
`3.  Motivation to combine Seiler and Perego ................................ 32 
`Claim 1 is obvious in view of Seiler and Perego ..................... 34 
`4. 
`Claim 2 is obvious in view of Seiler and Perego ..................... 48 
`5. 
`Claim 3 obvious in view of Seiler and Perego ......................... 49 
`6. 
`Claim 9 is obvious in view of Seiler and Perego ..................... 49 
`7. 
`Claim 10 is obvious in view of Seiler and Perego ................... 50 
`8. 
`Claim 21 is obvious in view of Seiler and Perego ................... 51 
`9. 
`
`B. 
`
`Ground II: Claims 1, 9, 10, and 21 are rendered obvious by
`Narayanaswami in view of Seiler........................................................ 54 
`
`Overview of Seiler .................................................................... 54 
`1. 
`Overview of Narayanaswami ................................................... 54 
`2. 
`3.  Motivation to combine Narayanaswami and Seiler ................. 58 
`Claim 1 is obvious in view of Narayanaswami and Seiler ....... 60 
`4. 
`Claim 9 is obvious in view of Narayanaswami and Seiler ....... 75 
`5. 
`Claim 10 is obvious in view of Narayanaswami and Seiler ..... 75 
`6. 
`Claim 21 is obvious in view of Narayanaswami and Seiler ..... 76 
`7. 
`
`VIII.  CONCLUSION .............................................................................................. 80 
`
`
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`IPR2016-01060 Petition
`Patent 8,933,945
`
`I. MANDATORY NOTICES
`A. Real Party-in-Interest
`Pursuant to 37 C.F.R. § 42.8(b)(1), Unified Patents Inc. (“Unified” or
`
`“Petitioner”) certifies that Unified is the real party-in-interest, and further certifies
`
`that no other party exercised control or could exercise control over Unified’s
`
`participation in this proceeding, the filing of this petition, or the conduct of any
`
`ensuing trial. In this regard, Unified has submitted voluntary discovery. See
`
`EX1015 (Petitioner’s Voluntary Interrogatory Responses).
`
`B. Related Matters
`US Pat. No. 8,933,945 (“’945 Patent” (EX1001)) is owned by Advanced
`
`Silicon Technologies, LLC (“AST” or “Patent Owner”). On December 21, 2015,
`
`AST filed lawsuits in the US District Court for the District of Delaware against
`
`multiple companies, claiming that these companies’ products and/or services
`
`infringe the ’945 Patent. AST also filed a Section 337 Action in the International
`
`Trade Commission on December 27, 2015 against multiple companies, seeking to
`
`exclude from
`
`importation certain components and products
`
`incorporating
`
`computing and graphics systems that allegedly infringe the ’945 Patent.
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`IPR2016-01060 Petition
`Patent 8,933,945
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`C. Counsel
`David L. Cavanaugh (Reg. No. 36,476) will act as lead counsel; Jonathan
`
`Stroud (Reg. No. 72,518) and Daniel Williams (Reg. No. 45,221) will act as back-
`
`up counsel.
`
`Service Information, Email, Hand Delivery and Postal
`
`D.
`Unified consents to electronic service at david.cavanaugh@wilmerhale.com
`
`and jonathan@unifiedpatents.com. Petitioner can be reached at Wilmer Cutler
`
`Pickering Hale and Dorr, LLP, 1875 Pennsylvania Ave., NW, Washington, DC
`
`20006, Tel: (202) 663-6000, Fax: (202) 663-6363, and Unified Patents Inc., 1875
`
`Connecticut Ave. NW, Floor 10, Washington, DC 20009, (650) 999-0899.
`
`II. CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies pursuant to Rule 42.104(a) that the patent for which
`
`review is sought is available for inter partes review and that Petitioner is not
`
`barred or estopped from requesting an inter partes review challenging the patent
`
`claims on the grounds identified in this Petition.
`
`III. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`Pursuant to Rules 42.22(a)(1) and 42.104(b)(1)–(2), Petitioner challenges
`
`claims 1-3, 9, 10, and 21 of the ’945 Patent.
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`2
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`IPR2016-01060 Petition
`Patent 8,933,945
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`Prior Art Patents and Printed Publications
`
`A.
`The following references are pertinent to the grounds of unpatentability
`
`explained below:1
`
`1.
`
`2.
`
`3.
`
`European Patent Application No. 1 195 717 (filed on August
`21, 2001 based on priority date of October 4, 2000; published
`on April 10, 2002) (“Seiler” (EX1002)), which is prior art
`under 35 U.S.C. § 102(a)
`US Pat. 6,864,896 (filed on May 15, 2001; published on
`November 21, 2002) (“Perego” (EX1003)), which is prior art
`under 35 U.S.C. § 102(e)
`US Pat. 5,757,385 (filed on January 30, 1996, claiming priority
`to
`July 21, 1994; published on May 26, 1998)
`(“Narayanaswami” (EX1004)), which is prior art under 35
`U.S.C. § 102(b)
`B. Grounds for Challenge
`This Petition, supported by
`
`the declaration of Professor Sudhakar
`
`Yalamanchili (“Yalamanchili Declaration” or “Yalamanchili” (EX1005)), requests
`
`cancellation of challenged claims 1-3, 9, 10, and 21 as unpatentable under 35
`
`U.S.C. § 103. See 35 U.S.C. § 314(a).
`
`
`1 The ’945 patent issued from a patent application filed prior to enactment of the
`
`America Invents Act (“AIA”). Accordingly, pre-AIA statutory framework applies.
`
`3
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`IPR2016-01060 Petition
`Patent 8,933,945
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`IV. TECHNOLOGY BACKGROUND
`When the ’945 patent was filed, computer graphics systems often included a
`
`host processor or central processing unit (CPU), graphics processing circuitry, and
`
`memory. Such systems relied on peripheral processors and dedicated peripheral
`
`memory units to perform various processing operations. For example, peripheral
`
`graphics processors may have been used to render graphics images.
`
`It was known to provide memory in separate units, such as main memory
`
`and a dedicated graphics memory. The main memory provides fast access to data
`
`for the CPU. Dedicated graphics memory provides fast access to graphics data for
`
`the graphics processor or graphics processing circuitry. CPUs and graphics
`
`processors are typically connected to their memory through a memory controller.
`
`The high cost of using multiple memory units drove many systems to use a single
`
`unified memory system that can be shared by multiple processors in the system
`
`without transferring data between multiple dedicated memory units. (Yalamanchili
`
`¶ 12 (EX1005)). A frame buffer, which is a form of memory, is typically a portion
`
`of RAM containing information that is driven to a video display. The information
`
`in the frame buffer may include, for example, color values for pixels on the screen.
`
`(Id. ¶ 12 (EX1005)).
`
`In 2000, a graphics accelerator called KRYO was released and described in a
`
`“Product Overview.” (KYRO at p. 1 (EX1006)). As shown below in a figure from
`
`4
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`IPR2016-01060 Petition
`Patent 8,933,945
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`the product overview, KYRO discloses a “single chip” device having “twin high-
`
`performance texturing pipeline” for processing image data. (KYRO at 3
`
`(EX1006)). The graphics accelerator is a “single chip” device. (KYRO at 3
`
`(EX1006)).
`
`
`Graphics information rendered by the twin pipelines is sent through a memory
`
`controller, i.e., SDRAM/SGRAM Interface, to a frame buffer. (KYRO at 3
`
`(EX1006)). The frame buffer is a “single memory.” (KYRO at 1 (EX1006)). The
`
`KYRO device is described as performing processing steps, including tak[ing] a
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`IPR2016-01060 Petition
`Patent 8,933,945
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`whole scene of data to be rendered” and “partition[ing] the data into screen
`
`tiles….” (KYRO at 5 (EX1006)).
`
`Moreover, well before the alleged November 2002 effective filing date of
`
`the ’945 patent, it was known to process data in a tiled format and to use multiple
`
`graphics pipelines or rendering engines. (Yalamanchili ¶ 15 (EX1005)). For
`
`example, U.S. Pat. No. 6,781,588 (“Margittai”), filed in September 2001, discloses
`
`to use multiple pipelines that share a common memory. Margittai further teaches
`
`to balance graphics processing operations between the pipelines to improve
`
`efficiency.
`
`U.S. Pat No. 6,657,635, filed in August 2000 based on a provisional
`
`application filed in September 1999, discloses to place a rendering engine on the
`
`same chip as a memory controller for processing image data in a tile format. U.S.
`
`Pat. No. 6,801,202, filed in June 2001 based on a provisional application filed in
`
`June 2000, discloses to use multiple graphics rendering unit on a single chip. U.S.
`
`Pat. No. 6,819,321, filed in March 2000, discloses to use multiple rendering
`
`engines on a single chip for processing data in tiled format. U.S. Pat. No.
`
`6,952,214 (“Naegle”), filed in July 2002, also discloses to use multiple rendering
`
`pipelines on the same chip to process data. Naegle further discloses to organize
`
`data into an array of spatial bins that define a rectangular window in a virtual
`
`screen space and perform texturing on the resultant visible pixels.
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`IPR2016-01060 Petition
`Patent 8,933,945
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`Multiple papers also make clear that it was well known to perform graphics
`
`processing using tiling and mapping of tiles to rendering engines based on screen
`
`area. For example Fuchs2 describes the partitioning of screen area in to square
`
`patches that are allocated to distinct rendering engines operating in parallel (Fuchs,
`
`Figure 1) and sharing a common frame buffer (Fuchs at Figure 2). (Yalamanchili ¶
`
`17 (EX1005)). Similarly Crockett3 describes an overview of parallel rendering
`
`algorithms as having “been applied to virtually every image generation technique
`
`used in computer graphics….” (Crocket at 820). (Yalamanchili ¶ 17 (EX1005)).
`
`He goes on to provide the advantages of using square regions of the image (tiles)
`
`for image parallel algorithms (Crockett at Figure 6). (Yalamanchili ¶ 17
`
`(EX1005)). Foley4 is a seminal text on computer graphics. Figure 18.17 of Foley
`
`explicitly discloses the mapping of square regions (tiles) in the frame buffer to
`
`
`2 Fuchs, Henry et al.; Pixel-Planes 5: A Heterogeneous Multiprocessor Graphics
`
`System Using Processor-Enhanced Memories; Computer Graphics; vol. 23, No. 3;
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`Jul. 1989; pp. 79-88.
`
`3 Crockett, Thomas W.; An introduction to parallel rendering; Elsevier Science
`
`B.V.; 1997; pp. 819-843.
`
`4 Foley, James et al.; Computer Graphics, Principles and Practice; Addison-Wesley
`
`Publishing Company; 1990; pp. 873-899.
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`IPR2016-01060 Petition
`Patent 8,933,945
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`rendering engines. (Id. ¶ 17 (EX1005)). These references reveal that partitioning
`
`the image space into tiles as discussed in the ’945 patent and mapping tiles to
`
`parallel rendering engines (equivalently graphics pipelines) was well known in the
`
`prior art. (Id. ¶ 17 (EX1005)).
`
`V. OVERVIEW OF THE ’945 PATENT
`A.
`Summary of the Alleged Invention
`The ’945 patent is directed to dividing work among multiple graphics
`
`pipelines. (’945 patent at 4:5-15 (EX1001)). These pipelines are shown below in
`
`Figure 2, which has color added, as elements 101 and 102. (’945 patent at 4:5-15
`
`(EX1001)); (Yalamanchili ¶ 18 (EX1005)). The pipelines are part of a “graphics
`
`processing circuit 34.” (’945 patent at 4:5-13 (EX1001)). The pipelines are
`
`described as operating independently of one another to process data for sets of tiles
`
`that correspond to screen locations on a display device. (Id. at 4:5-13, 5:66-6:5
`
`(EX1001)). A memory 48 is provided to store pixel data corresponding to the tiles.
`
`(Id. at 5:46-53 (EX1001)). A memory controller 46 controls the flow of data to the
`
`memory 48. (Id. at 5:4-7, Figure 2 (EX1001)). The memory 48 may be a “frame
`
`buffer.” (Id. at 6:15-16, 10:14-15 (EX1001)).
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`IPR2016-01060 Petition
`Patent 8,933,945
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`The ’945 patent acknowledges that it was known to use multiple pipelines
`
`for processing data corresponding to different regions of a display. (’945 patent at
`
`2:5-13 (EX1001)); (Yalamanchili ¶ 19 (EX1005)). For example, Figure 1 of ’945
`
`patent, reproduced below, provides a “display device 10, having a screen 12
`
`partitioned into a series of vertical strips 13-18.” (’945 patent at 1:44-45
`
`(EX1001)).
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`IPR2016-01060 Petition
`Patent 8,933,945
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`The ’945 patent explains that “the frame buffer of conventional graphics
`
`processing systems is partitioned into a series of vertical strips having the same
`
`screen space width.” (Id. at 1:46-49 (EX1001)). The ’945 patent also discloses
`
`that it was known to partition a buffer for corresponding screen locations into a
`
`series of horizontal strips. (Id. at 1:49-51 (EX1001)); (Yalamanchili ¶ 20
`
`(EX1005)).
`
`The alleged invention of the ’945 patent is to partition the screen into a tiled
`
`format, instead of strips, as shown below in Figure 3. (’945 patent at 5:66-6:9
`
`(EX1001)); (Yalamanchili ¶ 21 (EX1005)). The respective pipelines 101 and 102,
`
`10
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`

`
`shown in Figure 2, are responsible for processing data for the tiles. (’945 patent at
`
`5:66-6:5 (EX1001)).
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`IPR2016-01060 Petition
`Patent 8,933,945
`
`
`Although claim 1 includes limitations such “on a same chip” and “memory
`
`[that is] shared”, these features are not directly related to the purported inventive
`
`advancement, i.e., the tiling feature, and (2) the “same chip” and shared memory
`
`features were well-known in the art, as discussed below in more detail.
`
`(Yalamanchili ¶ 22 (EX1005)). The shared memory aspect was vigorously argued
`
`during prosecution as not being taught or suggested by the prior art. However, the
`
`’945 patent does not provided details on how this “shared memory” advances the
`
`purported invention. (Id. ¶ 22 (EX1005)). In fact, the term “shared memory” or
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`IPR2016-01060 Petition
`Patent 8,933,945
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`even “shared” is not found in the detailed description of the ’945 patent. (Id. ¶ 22
`
`(EX1005)).
`
`Level of Ordinary Skill in the Art
`
`B.
`A person of ordinary skill in the art at the time of filing the provisional
`
`application for the ’945 patent, i.e., November 27, 2002, would be familiar with
`
`computer graphics and have at least the equivalent of a Bachelor of Science degree
`
`in electrical or computer engineering, with multiple years of experience in the field
`
`of computer hardware architecture design, development, or evaluation.
`
`(Yalamanchili ¶ 34 (EX1005)). A higher level of education may make up for less
`
`experience. (Id. ¶ 34 (EX1005)).
`
`Prosecution History
`
`C.
`The ’945 Patent issued from US Pat. Appl. No. 10/459,797, which was filed
`
`on June 12, 2003 (File History, Application (6/12/03) (EX1007)), and allegedly
`
`claims priority to November 27, 2002 based on Provisional application No.
`
`60/429,641. (’945 Patent at 1:5–9 (EX1001)). Ten Office Actions on the merits
`
`were issued during prosecution of the ’945 Patent. Salient portions of the file
`
`history are discussed below in detail.
`
`In an Office Action dated August 28, 2007, the Examiner set forth a new
`
`ground of rejection using Perego to show that the claimed tiling feature was
`
`known.
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`IPR2016-01060 Petition
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`“As per Claims 1 and 25, Perego teaches graphics
`
`processing circuit (300, Fig. 3; Col. 3, ll. 61-63) having at
`
`least two graphics pipelines (312) operative to process
`
`data in corresponding set of tiles of repeating tile pattern
`
`corresponding to screen locations, respective one of at
`
`least two graphics pipelines operative to process data in a
`
`dedicated tile (c. 5, ll. 19-27, 38-44)….”
`
`(File History, Non-Final Office Action at 4 (8/28/2007 (EX1008)).
`
`In an effort to distinguish over Perego, Applicants amended claims 1 and 25
`
`to require that the “at least two graphics pipelines” are “on the same chip,” as
`
`shown below in the image reproductions from the file history. Claim 1 further
`
`required that the “memory controller” also be “on the chip.”
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`(File History, Amendment at 3, 8 (11/28/07) (EX1009). To support the
`
`amendment, Applicants argued as follows.
`
`“Perego does not describe multi-graphics pipeline
`
`circuitry on a same chip nor a memory controller on the
`
`same chip but
`
`instead describes discrete memory
`
`modules having separate and single graphics engines
`
`thereon. In addition, the memory controller described in
`
`Perego is not on a same chip nor is it part of the memory
`
`module as described in Perego. As such, the Perego
`
`reference does not anticipate Applicants’ claimed subject
`
`matter.”
`
`(Id. at 10 (11/28/2007 (emphasis added) (EX1009)).
`
`The Examiner was not convinced and issued a new grounds or rejection
`
`relying on Perego and two secondary references, U.S. Pat. No. 6,778,177
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`IPR2016-01060 Petition
`Patent 8,933,945
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`(“Furtner”) and U.S. Pat. No. 6,570,579 (“MacInnis”). Furtner and MacInnis were
`
`applied for cumulatively teaching that it was known to place multiple graphics
`
`pipelines on the same chip as a memory controller. (File History, Final Office
`
`Action at 3, 4 (2/4/08) (EX1010)). Multiple Requests for Continued Examination
`
`were filed without the claims being allowed.
`
`In July 2009, the claims remained rejected, but instead of the Examiner
`
`relying on the combination of Perego, Furtner and MacInnis, the Examiner applied
`
`a combination of only MacInnis and Perego against the independent application
`
`claims 1 and 25. (File History, Non-Final Office Action at 6, 7 (7/23/09)
`
`(EX1011)). Perego was still applied for disclosing the claimed tile related
`
`features. (Id. at 7 (7/23/09) (EX1011)).
`
`In response, on January 25, 2010, Applicants amended independent
`
`application claims 1 and 25 to require a “memory shared among the at least two
`
`graphics pipelines” and argued that these features were not taught by the prior art.
`
`(File History, Amendment at 2, 7, 9-11 (1/25/10) (EX1012)). To support the
`
`amendments, Applicants argued as follows
`
`“Applicants have amended claims to indicate what is
`
`believed to be inherent subject matter, that the memory
`
`controller that is on chip with the at least two graphics
`
`pipelines transfers pixel data between each of the first
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`and second pipelines and a memory that is shared among
`
`the at least two on chip pipelines.”
`
`(Id. at 9 (1/25/10) (emphasis added) (EX1012)). Applicants further argued that
`
`“MacInnis is a conventional graphics processing circuit that includes a single
`
`pipeline and corresponding memory controller on chip.” (Id. (1/25/10) (EX1012)).
`
`The claims were not amended further after the January 25, 2010 Amendment.
`
`Applicants filed a Notice of Appeal on July 22, 2010.
`
`Applicants argued that the graphics pipelines of Perego, which are shown as
`
`rendering engines, do not “access the same memory” and instead each have
`
`“separate, dedicated memory.” (File History, Appeal Brief at 18 (EX1013).
`
`Applicants conceded that the memory in Perego is shared, but argued that there is
`
`no explicit disclosure of the rendering engines sharing memory. Instead,
`
`Applicants argued that the memory is shared between a CPU and a single graphics
`
`pipeline. (Id. at 17 (EX1013) (“[t]he Perego teachings instead describe main
`
`memory of a CPU that is shared with a single graphics pipeline. Multiple pipelines
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`IPR2016-01060 Petition
`Patent 8,933,945
`in Perego do not share the same graphics memory.”))5 The Applicants maintained
`
`the same position in its Reply Brief. (File History, Reply Brief at 1-2 (EX1014)).
`
`The only dispositive issue set for by the Patent Trial and Appeal Board
`
`(“Board”) with respect to application claims 1 and 25 was “Did the Examiner err in
`
`finding that the combination of MacInnis and Perego teach a memory shared
`
`among the graphics pipelines?” (File History, Decision on Appeal at 3 (6/26/2014)
`
`(EX1015)). The Board reversed the Examiner based on the shared memory
`
`limitation, resulting in application claims 1 and 25 being allowed. (Id. at 4-6
`
`(6/26/2014) (EX1015)).
`
`The Board’s decision was necessitated in part by MacInnis’s disclosure
`
`being limited to a single rendering engine. In particular, the Board noted that
`
`“[t]he Examiner has not found that MacInnis teaches this feature,” i.e., memory
`
`that is shared between individual rendering engines. (Id. at 4 (6/26/2014)
`
`(EX1015)). The Board further asserted that “[t]he Examiner has not found that
`
`Kelleher, Furtner, Kent, or Hamburg teaches the shared memory as recited in
`
`independent application claims 1 [and 25]. Accordingly, we similarly will not
`
`
`5 One of ordinary skilled in the art would have considered the individual rendering
`
`engines of Perego to each be a single “graphics pipeline,” which is consistent with
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`Applicants’ explicit comments in the Appeal Brief.
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`sustain the Examiner's rejection ….” (Id. at 5 (emphasis added) (6/26/2014)
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`(EX1015)). The Notice of Allowability issued on September 4, 2014 with no
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`statement regarding the reasons for allowance. Application claim 25 issued as
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`independent claim 21. However, the use of multiple graphics pipelines that share
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`memory was well known in the art before the priority date of the ’945 patent.
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`(Yalamanchili ¶ 33 (EX1005)). Further, it was well known to put these features
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`onto a single chip, as discussed below in more detail. (Id. ¶ 33 (EX1005)).
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`Unfortunately, the Examiner and the Board did not have possession of this prior art
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`during prosecution.
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`VI. CLAIM CONSTRUCTION
`Claim terms of an unexpired patent in inter partes review are given the
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`“broadest reasonable construction in light of the specification.” 37 C.F.R. §
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`42.100(b); In re Cuozzo Speed Techs., LLC 778 F.3d 1271, 1279–81 (Fed. Cir.
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`2015). Any claim term that lacks a definition in the specification is therefore given
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`a broad interpretation.6 In re ICON Health & Fitness, Inc., 496 F.3d 1374, 1379
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`(Fed. Cir. 2007). Under the broadest reasonable interpretation standard, claim
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`6 Petitioner applies the “broadest reasonable construction” standard as required by
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`the governing regulations. 37 C.F.R. § 42.100(b). Petitioner reserves the right to
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`pursue different constructions in a district court, where a different standard is
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`applicable.
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`terms are given their ordinary and customary meaning, as they would be
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`understood by one of ordinary skill in the art, in the context of the disclosure. In re
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`Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). Any special
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`definition for a claim term must be set forth in the specification with “reasonable
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`clarity, deliberateness, and precision.” In re Paulsen, 30 F.3d 1475, 1480 (Fed.
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`Cir. 1994).
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`The following proposes a construction and offers support for that
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`construction. Any claim terms not included should be given their broadest
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`reasonable interpretation in light of the specification, as commonly understood by
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`those of ordinary skill in the art. Should the Patent Owner, to avoid the prior art,
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`contend that a claim term has a construction different from its broadest reasonable
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`interpretation, the appropriate course is for the Patent Owner to seek to amend the
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`claim to expressly correspond to its contentions in this proceeding. See 77 Fed.
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`Reg. 48764 (Aug. 14, 2012).
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`“graphics pipeline”
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`A.
`The claims recite the term “graphics pipeline.” In the context of the ’945
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`patent, a person of ordinary skill in the art would have understood this term to
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`mean “hardware including one or more circuits that process graphics data in a
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`pipelined manner.”
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` (Yalamanchili ¶ 43 (EX1005)).
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` The ’945 patent’s
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`specification discloses that the claimed graphics pipeline includes one or more
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`circuits. (Id. ¶ 43 (EX1005)). Further, the preambles of independent claims 1 and
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`21 describe a “graphics processing circuit.” (’945 patent at 9:65, 12:22-36
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`(EX1001)); (Yalamanchili ¶ 43 (EX1005)).
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`VII. SPECIFIC GROUNDS FOR PETITION
`Pursuant to Rule 42.104(b)(4)–(5), the following sections (as confirmed in
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`the Yalamanchili Declaration ¶¶ 44–167 (EX1005)) detail the grounds of
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`unpatentability, the limitations of the challenged claims of the ’945 Patent, and
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`how these claims were therefore obvious in view of the prior art.
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`A. Ground I: Claims 1-3, 9, 10, and 21 are rendered obvious by
`Seiler in view of Perego
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`Seiler is not of record in the ’945 patent. Perego was applied by the
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`Examiner during prosecution of the ’945 patent, but is hereby being applied in a
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`new light.
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`1.
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`Overview of Seiler
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`Seiler claims priority to U.S. Application No. 09/679,315, which was filed
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`on October 4, 2000. Seiler is directed to an integrated circuit for rendering graphic
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`data with multiple parallel graphics pipelines. (Seiler at ¶¶ 2, 14 (EX1002));
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`(Yalamanchili ¶ 42 (EX1005)). As shown below in annotated Figure 1, the
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`integrated circuit includes a rendering subsystem 200 having rendering pipelines
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`240, a memory interface 210, and rendering memory 160. (Seiler at ¶ 14
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`(EX1002)). Seiler discloses that “[a]s an advantage, the rendering subsystem is
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`fabricated as a single [application specific integrated circuit] ASIC.” (Seiler at ¶
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`14 (EX1002)); (Yalamanchili ¶ 42 (EX1005)). One of ordinary skill in the art
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`would have understood that an “integrated circuit” is a single chip configuration.
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`(Yalamanchili ¶ 42 (EX1005)).
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`Seiler discloses that the memory interface 210 “implements all accesses to
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`the rendering memory 160, arbitrates the requests of the bus logic 220 and the
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`controller 400, and distributes array data across the modules and the rendering
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`memory 160 for high bandwidth access and operation.” (Seiler at ¶ 16 (EX1002)).
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`Seiler further discloses that “[t]he memory interface 210 controls eight double data
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`rate (DDR) synchronous DRAM channels that comprise an off-chip rendering
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`memory 160.” (Seiler at ¶ 16 (emphasis added) (EX1002)). Thus, the memory
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`interface is a memory controller. (Yalamanchili ¶ 46 (EX1005)).
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`The memory controller 210 controls lines of communication between the
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`graphics pipelines 240 and the memory 160. (Seiler at ¶ 16 (EX1002) (“The
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`memory interface 210 controls eight double data rate (DDR) synchronous DRAM
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`channels that comprise an off-chip rendering memory 160.”)); (Yalamanchili ¶ 47
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`(EX1005)). One of ordinary skill in the art would understand that the multiple
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`channels are used to increase the bandwidth between the memory 160 and the
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`memory controller 210. (Id. ¶ 47 (EX1005)).
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`The rendering memory 160 is disclosed as being “off-chip” and providing “a
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`unified storage for all data 211 needed for rendering volumes, i.e., voxels, pixels,
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`depth values, look-up tables, and command queues.” (Seiler at ¶ 16 (EX1002)).
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`Thus, one of ordinary skill in the art would have understood that the rendering
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`memory 160 is shared by all of the pipelines 240. (Yalamanchili ¶ 48 (EX1005)).
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`One of ordinary skill in the art would have understood that a “rendering” pipeline
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`would have also been called a graphics pipeline. (Id. ¶ 48 (EX1005)).
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`Figure 2 of Seiler is reproduced below, with annotations, to show the
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`graphics pipelines in more detail. The pipelines (A, B, C, and D) operate
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`independent of each other and form the core of the rendering engine. (Seiler at ¶
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`15 (EX1002)). The term “rendering engine” covers embodiments including
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`multiple graphics pipelines, as shown in Seiler, and covers embodiments including
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`a single graphics pipeline. (Yalamanchili ¶ 49 (EX1005)). A pipeline controller
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`400 receives image data from memory 160. (Id. ¶ 49 (EX1005)). The controller
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`400 also sends control information to the individual graphics pipelines and receives
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`output data and status about the rendering operations. (Seiler at ¶ 19 (EX1002)).
`
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`Similar to the ’945 patent, the memory controller 210 is position between the
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`memory 160 and the pipelines. (Yalamanchili ¶ 50 (EX1005)). The pipeline
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`controller 400 determines what data to fetch from the memory 160 and dispatches
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`that data to the four pipelines. (Seiler at ¶ 19 (EX1002)). The rendering memory
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`160 is shared by the pipelines and is called “a unified storage for all data 211
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`needed for rendering….” (Seiler at ¶ 16 (EX1002)); (Yalamanchili ¶ 50
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`(EX1005)). In use, the memory controller 210 passes information back and forth
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`between the shared memory 160 and the pipelines. (Seiler at ¶ 33, 35 (EX1002));
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`(Yalamanchili ¶ 50 (EX1005)).
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`Figure 3