IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES
`
`In re application of:
`Mark M. Leather‘ et al.
`
`Examiner: Joni Hsu
`
`Application No.; 10/459,797
`
`Group A1“: Unit: 2628
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`Filed: June 12, 2003*
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`iDocket.No.: 0()100.02.0053
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`‘For: DIVIDING WORK AMONG
`' MULTIPLE GRAPHICS
`PIPELINES USING A SUPER-
`
`TXLING TECHNIQUE
`
`APPEAL BRIEF FURSUANT TO 37 C.F.R.
`
`
`‘ 41.37
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`
`
`Dear Sir:
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`A_pp‘el1ants submit this brief further to the Pre-Appeal Brief Request for Review filed
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`Ju1_‘y'22‘, 2010, and the Notice of Panel Decision from P1te~Appea»1 Brief Review dated July 30,
`
`2010 in. the eaboveddentified app1ic*ation.. Appel.1ants_petition.for a four month extension of time.
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`Ci~II(.‘AG()if!2l59628.i
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`U N I Fl ED 1 O1 3
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`UNIFIED 1013
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`"TABLE OF CONTENTS
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`..... ..3
`....................
`REAL PARTY IN INTEREST .........................................................
`RELATED APPEALS AND INTERFERENCES .........
`............
`...........
`......
`........... .......4
`
`.... ..5
`....................
`......
`..........................
`....
`....
`STATUSOFCLAIMS,....
`............... ...;.6
`........
`STATUS OFAMENDMENTS...............
`........
`.....
`......................
`.........
`SUMMARY ‘OF CLAIMED SUEJECTM. .. TER.._ ...............
`GROUNDS OF RE_JECTIONTO BE REVIEWED ON APPEAL ............
`............ ..I.s
`
`‘1.
`II.
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`.111;
`IV.
`V.
`V11.
`
`VII.
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`THE PEREGO REFERENCE ‘DOES NOT TEACH ‘WHAT IS-
`ALLEGED THEREFORE THE .35 U.S..C._
`§ 103 REJECTION OF
`CLAIMS 1-7, 10.22,. 2.4 AND 25 MUST BE REVERSED...., ...........
`.....
`THE REFERENCES DO NOT TEACH WHAT IS ALLEGED
`THEREFORE THE 35 U.S.C. §I1_03(A) REJECTION OF CLAIMS 5», IS.
`AND24MUST.EEREvERSED...I ....
`.......
`....
`..............
`....
`THE REFERENCES DO NOT TEACH W’ AT IS ALLEGED
`THEREFORE THE 35 U.S.C. § '103(A) REJECTION OF CLAIMS 6
`AND .17 MUST BE:
`THE REFERENCES DO NOT TEACH WHAT IS ALLEGED
`THEREFORE THE 35 USC. (S 103(A) REJECTION OF CLATIMS ‘II,
`13,1.5‘AND;16 MUST BE REVERSED ...............
`.............
`..........
`THE REFERENCES DO NOT TEACH WHAT IS ALLEGED
`THEREFORE THE 3.5 U.S.C. § Io3(A) REJECTION OF CLAIM I9
`MUST BEREVERSED ........
`.....
`.............
`...........
`..........
`....
`THE PEREGO REFERENCE DOES NOT TEACH WHAT IS.
`ALLEG?ED- THEREFORE THE 35 U.S.C. §'
`Io3(A_) REIECTION OF
`27
`CLAIMS 20.22 MUST EEREVERSED
`.... .29
`........
`...........
`....
`.....
`.......
`VIII. CONCLUSION .......................
`................
`..........
`CLAIMS APPENDIX/CLAIMS ON APPEAL ....................................................... ..APPENDIX A
`EVIDENCE APPENDIX ....................................
`..............................................
`APPENDIX B
`RELATED PROCEEDINGS...._.........
`...............
`.........................
`........
`........... ...APPENDIXC
`
`16
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`22
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`23
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`_
`23
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`CHICAGO/'#'2l59628,l
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`1'.
`
`REAL PARTY IN’ INTEREST
`
`ATI Technologies ULC is the real party in interest in this appeal by Virtue of an executed
`
`assignment from the named inventors of their entire interest to ATI llnternationcal, SRL and an
`
`executed name change. The assignment evincing such ownership iriterest was recorded on June
`
`12, 2003, in the United. States Patent and Trademark Officeat Reel 014176, Frame 0613.. The
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`Name Change was recorded on December 30, .2010, in the United States Patent and Trademark
`
`Office at Reel 025573, Frame 0443.
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`Cl-IIC‘./A\G(')/.#2J 59623.1
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`DJ
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`II.
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`RELATED APPEALS AND INTERFERENCES
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`To Appellants’ knowledge, tllere» arena related Appeals or Interferences filed, pending,
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`or decided.
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`CH](:‘/\G()/‘#2159628.1
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`111,
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`STATUS OF CLAIMS
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`Claims 1-7, 10-22, 24 and 25 are pending. Claims 1-7, 10-22, 24 and 25 stand rejected.
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`The; originally filed Application contained claims 1-24. Claims 25 and 26 were added during
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`prosecutioli of the present application. Claims 8, 9, 23 and 26 were canceled during prosecution
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`ofthe present. application. -Claims 1, 10, 12, 13, 20, 24 and 25 were amended during prosecution.
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`of the present application. Claims 1-7, 10-22, 24 and 25 are being appealed. Ofthe pending
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`appealed claims, 1, 20, 24‘ and 25 are independent.
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`CH1 Cf‘AG()i#2l59628.l
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`IV.
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`STATUS’ OF AMENDMENTS
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`A Pre-Appeal Brief Request for Review was filed -on July 22, 2010, in response to the
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`Final Office Action mailed on April 22, 2010. N0 amendments were made to the c1.aims,
`
`howevei, subsequent to the Final Office Action. The claims listed in Appendix A reflect the
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`claims as they stood at the time the Final Office Action was mailed.
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`V.
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`V
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`SUMMARY OF CLAIMED SUBJECT MATTER
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`Computer graphics systems, set top box systems or. other graphics processing systems
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`typically include a host processor, graphics (including video) processing circuitry, memory (e. g.
`
`frame buffer), and one or more display devices. The host processor
`
`have a graphics
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`application running thereon, which provides vertex data for a primitive (e.g. triangle) to be
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`rendered on the one or more display devices to the graphics processing circuitry. The display
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`"device, for example, a CRT display includes a pl'u1'aiity of scan lines comprised of a series of
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`0 pixels. When appearance attributes (erg; color, brightness, texture) are applied to the pixels, an
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`object or scene is presented on the display device. The graphics‘ processing circuitry receives the
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`vertex data and generates pixel data including the appearance attributes which may be presented
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`on the display device'accordin‘g_ to a particular protocol. The pixel data is typically stored in the
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`frame buffer in a nlanner that corresponds: to the pixels location on the display device (at least
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`110003)}
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`In a ‘conventional display device,» a screen may be partitioned into a series of vertical.
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`strips, The strips are typically 1-4. pixels in width.
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`In like manner,
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`the frame buffer of
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`conventional graphics processing systems is partitioned into a series of vertical strips having the
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`same screen space width. Alternatively, the frame buffer and the display device may be
`
`partitioned into a series of horizontal strips. Graphics calculations, for example, lighting, color,
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`texture and user viewing information are performed by the graphics processing circuitry on each
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`of the primitives provided by the host. Once all calculations have been performed on the
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`primitives, the pixel data representing the object to be displayed is written into the frame buffer.
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`Once the graphics calculations have been repeated for all primitives associated with a specific
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`frame, the data stored in the frame buffer is rendered to create a video signal that is provided to
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`the display device (at least ‘H 0004).
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`(‘_fI»IIC‘AG(')/#2159628.1
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`The. amount’ of time ‘taken for an entire’ frame of information to be calculated and
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`provided to the -frame buffer becomes a bottleneck in graphics systems as the calculations
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`- -associated with the graphics become more complicated.
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`Contributing to the increased
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`complexity of the graphics calculation is the increased need for higher resoiutioii video, as well
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`as the need for more complicated video, such as 3-D video. The video’ image observed by the
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`human eye becomes distorted or choppy when the amount of time taken to render an entire frame
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`of video exceeds the amount of time in which the display‘ device must be refreshed with a new
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`‘graphic or frame in order to avoid perception by the human eye. To decrease -processing timer,
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`graphics processing systems typically‘ divide primitive processing among several graphics
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`processing, circuits where, for example, one graphics processing circuit is responsible for one
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`vertical. strip of the frame while another graphics _processing circuit is "responsible for another"
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`"vertical ‘strip of the frame‘,
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`In this manner-, the pixel data is provided to the ‘frame buffer within
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`the required refresh time (at least 1] 0005).
`
`Load balancing is a- significant drawback associated with the partitioning systems as
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`~ described above. Load balancing problems occur, for example, when all of the primitives ofea
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`particular object or scene are located in one strip. When this occurs, only the graphics
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`processing circuit responsible strip 13 is actively processing primitives; the remaining graphics
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`processing circuits are idle. This results in a significant waste of computing resources as at most
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`only half of the graphics processing circuits are operating. Consequently, graphics processing
`
`system performance is decreased as the system is only operating at a maximum of fifty percent"
`
`capacity (at least 11 0006).
`
`In contrast, according to an aspect of Appellants’ present disclosure, the same frame
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`buffer is shared among multiple pipelines that are on a single chip. The shared frame buffer is
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`CHICAGO/‘#2159628. l
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`configured such that the primitive data is written in the tiles bei'n'g’processed by the first graphics
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`pipeline and the tiles being processed by the second graphics pipeline will be substantially equal
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`in size, notwithstanding the primitive orientation. Thus, the amount of p_roces_sing performed by
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`the first graphics pipeline and the second graphics pipeline, respectively, are silbstaiitially equal;
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`thereby, effectively eliminating the load balance problems exhibited by conventional techniques.
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`(at least ‘H 10030).
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`As to. independent claim 1 and also referring to FIGS». 2 and 3., yeproduced below for
`
`convenience,
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`F18. -3
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`a -graphics processing circuit (34), including at least two graphics pipelines (102, 102) on a ‘same
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`chip are operative to process data in a corresponding set. of tiles (72, 73 respectively) of a
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`repeating ‘tile pattern corresponding to screen. locations, a respective one of the at least two
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`graphics pipelines are operative to process ‘data in a dedicated tile. The graphics processing
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`circuit 34 also includes a memory controller 46 on. the chip in communication with the at least
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`two graphics pipelines (A101, 102), and is operative.to'transfer pixel data (43, 44) between each of
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`a first pipeline and a second pipeline and a memory (48) shared among the atleast two graphics
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`pipelines (l0l, 102), wherein the repeating tile pattern includes a horizontally and vertically
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`repeating pattern of square regions (FIG. 2,. FIG. 3, at least W 0018-0030).
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`Dependent claim 4 is directed to the graphics processing circuit (34), wherein each of the
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`at least two graphics pipelines (l0l, .102) further includes front end circuitry (35) (at least W
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`("IiI(L‘ACi()./#2 .| 59628.1
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`10’
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`0022, 0023) 0.peratis/.6 to receive vertex data (31) and generate pixel data (e.g.,
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`corresponding
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`to a primitive to be rendered, and back end circuitry (39, 42), coupled to the front -end circuitry,
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`operative‘ to .receive. and process a portioniof the pixel data (at least W 0022, 0025, 0027).
`
`Dependent claim Sis directed to the graphics processing circuit, wheifeiii each of the at
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`least two: graphics pipelines further includes a scan converter (37, 40), coupled to the back end
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`circuitry, operative to determine the portion of the pixel data to be processed by the back end
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`circuitry" (at least 1l1l 0024-0026).
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`Dependent claim 11 is directed. to the «graphics processing circuit of claim 10., wherein the
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`.fiI'SlC» ofthe at least two graphics pipelines (101) further includes _a scan. converter (37), coupled to
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`the front end circuitry and the back end circuitry, operative to provide position coordinatesiof the
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`pixels within the first set of tiles to be processed by the ‘back end circuitry '.(39.),
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`the scan
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`converter (37) including a pixel identificati‘on line for receivingtiie identification data (38, 41')
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`indicating, which of the set of tiles is to bevprocessed by the back end circuitry (at. least.‘H‘fl 0022-
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`.0026).
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`Dependent claim 13 is directed to the graphics processing circuit, wherein the second of
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`the at least two graphics pipelines (102) further includes a scan. converter (40), coupled to front.
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`_ end» circuitry -and back end circuitry (42), operative to provide position coordinates of the pixels
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`within the second set of tiles to be processed by the back end circuitry, the scan converter
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`including a pixel identification line for receiving tile identification data (41) indicating which of
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`the set of tiles is to be processed by the back end circuitry (at least fifil 0022-0026).
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`Dependent claim 14 is directed to a third graphics pipeline (201) and a fourth graphics
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`pipeline (202), wherein the third graphics pipeline includes front end circuitry (135) operative to '
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`receive Vertex data and generate pixel data corresponding to a primitive to be rendered, and back
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`Cl'II(f‘.’\G()./fl2l59628.l
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`110
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`i
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`end circuitry, coupled to the fifont end circuitry, operative ‘to receive and process the pixel data in
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`a third set of tiles in the repeating tile pattern, and wherein the fourth graphics pipeline includes
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`front end circuitry operative to receive vertex data and generate pixel data corresponding_ to a
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`primitive to be rendered, and back end circuitry, coupled to the front end circuitry, operative to
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`receive and process the pixel data in a fourth set of tiles in the repeating tile pattern (FIG. 2, FIG.
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`.5, at least 11110'031—0035').
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`Dependentuclairn _l5 is directed to a graphics. processing circuit, wherein the third
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`graphics pipe1ine(2011) further includes a scan. converter (137), coupledxto the front end circuitry
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`(135) and the back end circuitry (139), operative to provide position coordinates of the pixels
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`‘within the third set of tiles to. be processed. by the back end circuitry (139), the scan converter
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`(137) including a pixel identification line for receiving ‘tile i‘de:ntification. data (138) indicating
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`which of the sets of tiles‘ is to be processed by the back end circuitry (FIG-. 5, at ‘least 1111 0l)22-
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`. 0026, 0037-0039).
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`Dependent claim 16 is directed to a graphics prccessinig circuit, wherein. the fourth
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`graphics pipelin.e (202) further includes a scan converter (140), coupled to the front’ end circuitry
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`(135) and the back end circuitry (142), operative to provide position coordinates of the pixels
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`w_ithin the fourth set of tiles to be processed by the back end circuitry, the scan converter
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`including a pixel identification line for receiving tile identification data (141) indicating which of
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`the sets of tiles is to be processed by the back end circuitry. (Fig. 5 at least 111] 0032-0039)‘
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`Dependent claim 19 is directed to a graphics processing circuit wherein the data‘ includes ‘
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`a polygon and wherein each separate chip creates a bounding box (Fig. 7) around the polygon
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`and wherein each corner of the bounding box ischecked against a super tile that belongs to each
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`separate chip and wherein if the bounding box does not overlap any of the super tiles associated
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`with a separate chip, then. the processing circuit rej ects. the whole polygon and processes. a next
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`one. (Fig. 3, Fig. 7, Fig. 8, at least 1i‘fl0049~005 1)
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`Independent claim 20 is directed. to a graphics processing method, including receiving.
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`vertex data. for a primitive to be rendered (100), generating pixel data in response to the vertex
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`data (102), passing the same pixel data to both of the at least two graphics pipelines on a saine
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`chip, deteiminingj the ‘pixels within a set oftiles (72, 73) of a repeating tile pattern corresponding
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`to screen locations to be pr.ocessed by corresponding one of the at least two graphics pipelines
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`on a‘ same chip» in response" to the pixel data, the repeating tile pattern including a horizontally
`and vertically repeating pattern of‘ square regions (Fig. 3), pertorming pixel operations on the
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`pixels within the determined set of tiles by the corresponding one of the at least two. graphics
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`pipelines (108),. an.d transniitting the processedpixels to a memory controller (146),. wherein the
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`at least two graphics pipelines share the memory controller wherein the memory controller
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`transfers pixel data fiorn ‘each of the at least two pipelines, to a shared memory.
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`(Fig. 6, at least.
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`‘[11]’ 0040-0045, 0027-0030)
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`Independent claim 24 is directed to a graphics processing circuit (34),. including front end
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`circuitry (35) on a chip operative to generate -pixel data in response to primitive data ‘for a
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`prirnjitive to be rendered, first back end circuitry (39) on the chip, coupled to the front end
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`circuitry, operative to process a first portion. of the pixel data in response to position coordinates,
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`a first scan converter (37) on the chip, coupled between the front end circuitry and the first back
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`end circuitry, operative to determine which set of tiles of a repeating tile pattern are to be
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`processed by the first back end circuitry, the repeating tile pattern including a horizontally and
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`vertically repeating pattern of square regions, and operative to provide the position coordinates to
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`the first back end circuitry in response to the pixel data, second back end circuitry (42) on the
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`Cl~II(."./—\G()/#2 .l 59628.1
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`chip, coupled to the front end circuitry (35), operative to process a second. portion of the pixel.
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`V
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`data in response to position coordinates, a second scan converter (42). on the chip, Coupled.
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`between the front end circuitry (35)
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`and the second back end circuitry (42), operative to
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`determine which set of‘tiles of the repeating tile pattern are to be processed by the S-ecoI.1di'bac’k
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`end circuitry, and operative to provide the position coordinates to. the second back end circuitry
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`in response to the pixel data, and a memory controller (146) on the chip, coupled to the first and
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`seoond back end circuitry operative to transmit and receive ‘the processed pixel data.
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`(Fig. 2, at
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`least 1]11eoi*s'—oo3 0)
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`Independent claim 25 is directed to a graphics» processing circuit (34), including at least
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`two graphics pi_pel.ines (101,102) on a :chip operative to process data in a ‘corresponding set of
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`tiles of a repeating. tile pattern corresponding to screen locations, a respective one of the at least
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`‘two. graphics pipelines e_perative to process data in a dedicated tile, wlierein the repeating tile
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`:patt;ern~ includes a horizontally and vertically repeating pattern of‘ regions, wherein the
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`horizontally and vertically repeating pattern of regions include NXM number of pixels; and a
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`memory controller (.46) on the chip, coupled to the at least two graphics pipelinesonthe chip and
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`‘operative to transfer pixel data between each of the tvvo graphics pipelines and a memory’ (48)
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`shared among the at least two graphics pipelines.
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`((F_lG. 2, FIG. 3, at least 111] 0018-0030).
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`GROUNDS OF REJECTION TO BE REVIEWED ON APPEAL -
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`Claims 1——4, 7, 10, 12, 1.4 and 25 stand rejected under‘ 3.5 U.S.C. § 103(a) as being
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`unpatentable over U.S. Patent No. 6,570,579 (Maclnnis) in View of U.S. Patent No. 6,864,896
`(Perego). H
`8
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`Claims 5, 18 and 24 stand rejected under 35 U.S.C. '§ 103(a) as beingunpatentable over
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`US. ‘Patent No. 6,570,579 (Maclnnis) in View of US. Pa_tent— No. 6,864,896 (Perego), further in.
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`View of U.S. Patent No. 5,794,016 (Kelleher).
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`Claims 6 and 127 standrejected. under 35 U.S.C. Ȥ 103(a) as being unpatentable over US...
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`Patent No. 6,570,579 (Maclnnis) in View of US. Patent No. 6,864,896 (Peerego), further in view‘
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`of US. ‘Patent No. 6,778,177 (Furtner).
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`Claims 11, 13, 15 and, 16 stand rejected under 35 U.S.C. _§ 103(a) as beinglunpatentable
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`over‘ US, Patent No. 6,570,579 (1\/Iaclnnis) in View of US. Patent No. 6,864,896 (Perego),
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`-futlher in View of U.S. Patent No. 5,794,016. (Kelleher), further in View of U.S. Patent No.
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`‘ 5,905,506 (Hamburg-_).
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`Claim 19 stands rejected under 35 U.S.C. § 103(a;) as being unpatentable over U.S. Patent
`
`No. 6,570,579 (Maclnnis) in View of Patent No. 6,864,896 (Perego), further in View of U.S.
`
`Patent No, 6,778,177 (Furtner), further in View of U.S._ Publication No. 2003/0.1164830 (Kent).
`Claims 2022 Stand rejected under 35 U.S.C. § 103(a). as being unpatcntable over U.S.
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`Patent No. 6,864,896 (Perego).
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`V] .
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`ARGUMENT
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`The references and claim language cannot be mischaracterized in an effort to render a
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`claim unpatentable (See e.g., In Re Roztf/‘er, 1.49 F. 3d. 1350, 47 USAPQ 2d 1453 (Fed. Circ. 1998,
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`In Re‘ Fine, 837 F.2d 1071)). Claims cannot be interpreted in a vacuum but must be reasonabbz
`interpreted in light of’the specification as it would be interpreted. by one of ordinary skill in the
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`art. PI'ziIlij).s' V. /i_WH Corp, 75 .USPQ2d 1321 (en banc‘) (Fed. Cir. 2003). (see also MPEP 2111
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`and Cited cases. incorporated by reference herein). Claims must be interpreted to be consistent-
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`with the claims themselves and with the Specification. Also, if a reference does not teach what —
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`is alleged, a prima facie case has not been made. (See MPEP sections 2142-2.14.4 and cited cases
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`‘
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`incorporated by reference herein). Graham v-John Deere C0,, 383 U.S. 1 (1966), (see also, KSR
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`_In2‘er1mri022al.Co. v. Teieflex Inc. at al., 127 S. Ct. 1727 (2007). For one orrnore of these reasons
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`4 the rejections must bereversed and the claims should be allowed.
`
`1.
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`THE PEREGO REFERENCE DOES NOT TEACH WHAT IS ALLEGED
`THEREFORE THE 35 tinge 103 REJECTION on CLAIMS 1-7,. 1992, 24
`AND .25 MUST BE. REVERSED
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`Claims 1—4., 7, 10, 12, 14 and 25 stand. rejected under 35 U.S.C.
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`§. l03(a) as being
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`unpatentablet over US. Patent No, 6,570,579 (Maclnnis) in View of
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`Patent No. 6,864,896 H
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`(Perego). Maclnnis is a conventional grapliics processing circuit that includes a single ‘pipeline
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`and corresponding memory controller on chip.
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`It is admitted that Maclnnis does not teach at
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`least two graphics pipelines on a same chip that process data in a corresponding set of tiles for a.
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`repeating_ tile pattern corresponding to screen locations. Nor does it teach a plurality of graphics
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`pipelines and associated memory controller on the same chip in communication with the at least
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`two graphics pipelines wherein the memory controller transfers pixel data between each of the
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`two pipelines and a memory that is shared among the at least two graphic on chip pipelines. The
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`office action alleges that Perego teaches this subject matter.
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`1
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`Perego is directed to a scalable unified CPU and graphics memory .architecture and
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`employs independent, groups of memory modules 304 that
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`-are coupled to a memory
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`contr.oller/graphics ‘controller (col. 3, his. 63-67). Perego describes eachvmemory module 304 as
`
`.i11cluding a rendering engine 312 and a dedicated corresponding shared memory 314 such that
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`shared 1T1€II10’l‘.y 314 is shared between :a CPU andthe rendering engine 3.l2. As described by
`Perego, the shared memory may be madeup of multiple memory devices however, the shared
`
`memory 314 is still only sharcdbetweenc the rendering engine on the particular memory module
`
`and -the CPU. The shared memory of Perego is not shared between mu/lti
`
`le rend.erin V en‘ ines
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`;on different modules or shared’ between multiple rendering engines on a single module.
`
`C'la.i_ms 1 states, inter alia,
`
`a memory controller on the chip in communication with the at least two graphics
`pipelines, operative to transfer pixel data between each of a first pipeline and a
`second pipeline and a memo
`shared anion.
`the at least two rahics Vi elines
`
`
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`As .claimed., the shared memory’ is shared. among at least two graphics pipelines on. the
`
`same chip. Appellants respectfully submit that the Perego reference has been misapprehended,
`
`as it does not‘. teach what is alleged and is directed to a different operation and structure from that
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`claimed by Appellants. The Perego teachings instead describe main memory of a CPU that is
`
`shared with a single graphics pipeline. Multiple pipelines in Pcrego do not share the same
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`graphics memory. The final office action alleges on pages 6—7 that:
`
`Perego teaches...memory controller (310, Fig. 3) in communication. with at least
`2 graphics pipelines 312, operative to transfer pixel data between. each of l. st
`pipeline and 2nd pipeline and shared memories 314 (col. 3, lines 65-67; Col. 4,
`lines l—l0,48—65). Shared memories 314 are each part of main memory (col. l,
`
`
`lines 44-54; col. 3, lines 3—6)_, and so are considered to be one rnemor
`that is
`shared among the at least two ggaphics mpelincs (emphasis added).
`
`6
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`The final office action further alleges on page 4 that:
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`CHI(.‘AGO/1!"2l 596231
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`l7
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`Perego describes "The shared memory 3l4 typically includes multiple memory
`devices ‘coupled together to form a .block. of storage 312%" (col. 4, lines 8~l0).
`‘ Thus, the block ofistorage space is considered to be a memory shared among the
`two graphics pipelines (emphasis added).
`
`Appellants respectfully submit that the final Aoftice action. misinterprets the term “shared
`
`memory” as used. by Perege. As best understood by Appellants, the final office action interprets
`
`the term “shared memory” as 'memory_sha1'ed between graphics pipelines.
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`‘However, Perego
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`instead defines “shared memory” as memo
`
`. devices
`
`
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`artitioned- for use as both CPU “main
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`
`
`
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`shared between two: or morenot as memo ra 7l1lCS
`
`
`
`
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`pipelines. Furthermore, “main memory” is described as memory used only by the CPU, not
`
`memory used for graphics. Perego states:
`
`Each .mem0r_y'module 304 includes a rendering engine 312 and a shared memory
`
`314 (Le. main memoir
`and
`auhies memory). The main memory typically
`"
`A
`.‘
`’.
`t;._i'eallp
`A
`
`contains instructions and/or data used to
`render or otherwise handle
`
`graphical images ggraphical inferrnation. (c.‘olumn.4, lines (1 «.6; e.mphasi.s added)
`
`
`
`roe-ess
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`_
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`Peregc uses the term “shared memory” because a‘p(;)1‘l;l011.- of the memory on each separate
`
`- memory module is used by the CPU while the remainder is used as graphics memory.
`
`In. other
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`words, the physical memory devices are ‘‘shared?’ between the CPU and a rendering engine.
`
`However, the memory used for graphics processing is separate from the memory used by the
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`CPU. Perego explicitly states that, “the graphics memory is statically or dynamically partitioned
`
`gfi from the main memory pool” (column 1, lines 46-47; emphasis added).
`
`Additionally, Appellants respectfully submit that at no point does Perego teach that
`
`multiple rendering engines (alleged by the final office action to teach Appellants’ multiple
`
`graphics pipelines) access the same memory.
`
`In fact, Perego teaches each rendering engine as
`
`having se arate dedicated memor . Perego’s FIG. 8 (reproduced below) shows two separate
`
`
`rendering engines (802 and 810), each associated with their own dedicated group of memogy
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`Cl'llC‘.AG()/#2159628.1
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`l8
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`devices (m.em_o_ry devices 804 and 812, respectively) using distinct mem_Q_13/ interconnects (806
`
`g and 8.14, respectively 1. These separate groups of memory are each. comprised of multiple
`
`memory devices that are coupled together into" separate discrete blocks of storage.
`
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`Additionally or alternatively, Appellants respectfully submit that Perego teaches away
`from Appellants’ claimed design wh.ere a single/memory controller. shares. a single memory
`
`between multiple graphics pipelines. Perego explicitly states the advantages of having distinct
`
`memory devices tied to individual rendering engines:
`
`The architecture of FIG. 3 allows the memory controller/graphics controller 310
`to issue ‘high level primitive commands to the various rendering engines 3112,
`thereby reducing the volume or bandwidth of data that must be communicated
`between the controller 310 and the memory modules 304. Thus, the partitioning
`o5 BE. S 5 B("DB9
`of memo e
`'
`‘
`‘modules 304 im roves
`rra hical data
`
`throughput relative to systems in which a single gr_apliics controller performs all
`processing tasks and reduces bandwidth contention with the CPU. This bandwidth
`reduction occurs becausethe primitive commands typically contain significantly
`less data than the amount of data referenced when rendering the primitive.
`Additionally,
`the system partitioning described allows aggregate bandwidth
`between the renderin r en ines and the memor devices to be much hi her than
`
`
`
`the bandwidth between the controller and memory modules. Thus, effective
`0 system bandwidth is increased for processing graphics tasks (column 4, lines 47-
`65; emphasis added).
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`C’HIC‘AG()i#2159628.1
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`l9
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`In other words, bandwidth is increased by having each distinct rendering engine utilize its
`
`own dedicated memory present on the same memory module as the rendering engine. Assuming
`
`for the sake of argument that Perego did share graphics memory between rendering engines, no
`
`bandwidth gain would be attained as graphics data would necessarily be transferred through the
`
`memory/graphics controller to another memory module — exactly the scenario Perego seeks to
`
`avoid; Perego places. rendering engines on separate memory modules specifically to prevent the
`
`bottleneck created. by passing data through the memory controller during parallel processing.
`
`Accordingly, Perego -does not teach the claimed subject matter and. the ‘rejection should. be
`
`reversed.
`
`As to independent claim 25, the Examiner rejected,-this claim for the same reasons as
`
`claim 1 as being similar in scope andrrejected it by stating that it is “rejected under the same
`
`rationale” as claim .1 (final action, page 10).
`
`-Accordingly, Appellants respectfully .reasse‘rt; the
`
`relevant remarks made with respect to claim 1.. The rejection should be reversed for the same
`
`reasons as to claim 1.
`
`Dependent claims 2 and 3 for purposes of this Appeal only, stand or fall together with
`
`independent claim 1.
`
`As per dependent claim 4, they claim requires that each of the graphicspipelines each
`
`further include front end circuitry that receive vertex data and generate pixel data corresponding
`
`to the primitive to be rendered, and back end circuitry, coupled to the front end circuitry
`
`operative to receive and process a portion of the pixel data. The final rejection cites Perego as
`
`allegedly teaching pipeline front end circuitry as being element 308 in FIG. 3. The office action -
`
`cites col. 3, ln. 64 to col. 4, ln. 2; col.i5, lns. 19-44. However as shown_ below and reproduced
`
`FIG. 3, element 308 is actually a “CPU” and is not a pixel pipeline which the Examiner has
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`(.'Jl'll(,i‘A(ii()./#2159628.1
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`20
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`

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`already asserted is actually graphics pipeline 31-2 in the rejection of claim l. Appellants
`
`respectfully submit that it is logically impossible to have the CPU 308 as described in Perego as
`being separate‘ from rendering engine 312 as actually being in rendering engine 3l2 as alleged by
`
`the Examiner. [For example, plugging in E,X.aminer’s contention that the rendering engine 312 in
`
`Perego (as set forth in‘ the rejection of claim 1) corresponds to the claimed graphics pipelines and
`
`substituting ‘element 308 as allegedly corresponding to the claimed front. end circuitry, such a
`
`substitution results in an allegation that Perego teaches. that the rendering engine 312 contains the
`
`CPU 308 since the claim requires that each: of the ‘graphics pipeline include‘ the front end
`
`circuitry. Perego clearly does not teach that the CPU'is part of the rendering engine 312 and
`
`actually requires that they be separate. processors. Accordingly, Appellants respectfully submit
`
`that the rejection must be reversed.
`
`It is also» alleged as to claim 4 that the “CPU is operative to... generate pixel data
`
`‘corresponding to a Aprimitive. to be rendered (col. 5, his. 19-27; col. 1, ins. 18.-2.1)” (page 9 of
`
`final rejection). However, the cited portions do not describe what is alleged since the CPU in
`
`Perego does not generate pix_el data. To the contrary, the cited portion instead states as is well
`
`known in the art, that CPUS may sort primitive data which may be then submitted to, for
`
`example, the rendering pipeline. The CPU does not generate pixel data as alleged, since the
`
`rendering engine must generate pixel data. Also, the ‘citation as to col. 1 also fails to describe the
`
`CPU generating any pixel data corresponding to a primitive to be re