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`Applicants: Mark M. Leather et al.
`Serial No.: 10/459,797
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`Examiner: Joni Hsu
`Art Unit: 2628
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`Filing Date: June 12, 2003
`Confirmation No.: 4148
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`Our File No.: 00l00.02.0053
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`Title: DIVIDING WORK AMONG MULTIPLE GRAPHICS PIPELINES USING
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`A SUPER-TILING TECHNIQUE
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`Mail Stop Amendment
`Commissioner for Patents
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`P.O. Box 1450
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`Alexandria, VA 22313-1450
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`Dear Sir:
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`AMENDMENT AND RESPONSE
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`In response to the Office Action mailed July 23, 2009, Applicants petition for a three
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`month extension of time and respond as follows:
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`Amendments to the Claims begin on page 2 of this paper.
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`Remarks begin on page 9 of this paper.
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`CHICAGO/#2018275.1
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`l
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`UNIFIED 1012
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`UNIFIED 1012
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`Amendments to the Claims:
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`Re-write the claims as set forth below. This listing of claims will replace all prior versions and
`listings of claims in the application:
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`Listing of Claims:
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`1. (currently amended) A graphics processing circuit, comprising:
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`at
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`least
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`two graphics pipelines on a same chip operative to process data in a
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`corresponding set of tiles of a repeating tile pattern corresponding to screen locations, a
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`respective one of the at least two graphics pipelines operative to process data in a dedicated tile;
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`and
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`a memory controller on the chip in communication with the at
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`least two graphics
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`pipelines, operative to transfer pixel data between each of a first pipeline and a second pipeline
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`and a memory shared among the at least two graphics pipelines;
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`wherein the repeating tile pattern includes a horizontally and vertically repeating pattern
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`of square regions.
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`2.
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`(original) The graphics processing circuit of claim 1, wherein the square regions
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`comprise a two dimensional partitioning of memory.
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`3.
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`(original) The graphics processing circuit of claim 2, wherein the memory is a frame
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`buffer.
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`4.
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`(original) The graphics processing circuit of claim 1, wherein each of the at least two
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`graphics pipelines further includes front end circuitry operative to receive vertex data and
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`generate pixel data corresponding to a primitive to be rendered, and back end circuitry, coupled
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`to the front end circuitry, operative to receive and process a portion of the pixel data.
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`CHICAGO/#2018275.1
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`2
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`5.
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`(original) The graphics processing circuit of claim 4, wherein each of the at least two
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`graphics pipelines further includes a scan converter, coupled to the back end circuitry, operative
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`to determine the portion of the pixel data to be processed by the back end circuitry.
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`6.
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`(original) The graphics processing circuit of claim 1, wherein each tile of the set of
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`tiles further comprises a 16x16 pixel array.
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`7. (original) The graphics processing circuit of claim 4, wherein the at least two graphics
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`pipelines separately receive the pixel data from the front end circuitry.
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`8. (canceled)
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`9. (canceled)
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`10.
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`(previously presented) The graphics processing circuit of claim 7, wherein a first of
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`the at least two graphics pipelines processes the pixel data only in a first set of tiles in the
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`repeating tile pattern.
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`ll.
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`(original) The graphics processing circuit of claim 10, wherein the first of the at
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`least two graphics pipelines further includes a scan converter, coupled to the front end circuitry
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`and the back end circuitry, operative to provide position coordinates of the pixels within the first
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`set of tiles to be processed by the back end circuitry, the scan converter including a pixel
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`identification line for receiving tile identification data indicating which of the set of tiles is to be
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`processed by the back end circuitry.
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`CHICAGO/#2018275.1
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`3
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`12.
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`(previously presented) The graphics processing circuit of claim 1, wherein a second
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`of the at least two graphics pipelines processes the data only in a second set of tiles in the
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`repeating tile pattern.
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`13.
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`(previously presented) The graphics processing circuit of claim 12, wherein the
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`second of the at least two graphics pipelines further includes a scan converter, coupled to front
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`end circuitry and back end circuitry, operative to provide position coordinates of the pixels
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`within the second set of tiles to be processed by the back end circuitry, the scan converter
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`including a pixel identification line for receiving tile identification data indicating which of the
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`set of tiles is to be processed by the back end circuitry.
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`14.
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`(original) The graphics processing circuit of claim l
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`including a third graphics
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`pipeline and a fourth graphics pipeline, wherein the third graphics pipeline includes front end
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`circuitry operative to receive vertex data and generate pixel data corresponding to a primitive to
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`be rendered, and back end circuitry, coupled to the front end circuitry, operative to receive and
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`process the pixel data in a third set of tiles in the repeating tile pattern, and wherein the fourth
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`graphics pipeline includes front end circuitry operative to receive vertex data and generate pixel
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`data corresponding to a primitive to be rendered, and back end circuitry, coupled to the front end
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`circuitry, operative to receive and process the pixel data in a fourth set of tiles in the repeating
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`tile pattern.
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`15.
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`(original) The graphics processing circuit of claim l4, wherein the third graphics
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`pipeline further includes a scan converter, coupled to the front end circuitry and the back end
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`circuitry, operative to provide position coordinates of the pixels within the third set of tiles to be
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`processed by the back end circuitry, the scan converter including a pixel identification line for
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`CHICAGO/#2018275.1
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`4
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`
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`receiving tile identification data indicating which of the sets of tiles is to be processed by the
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`back end circuitry.
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`16.
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`(original) The graphics processing circuit of claim 14, wherein the fourth graphics
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`pipeline further includes a scan converter, coupled to the front end circuitry and the back end
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`circuitry, operative to provide position coordinates of the pixels within the fourth set of tiles to
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`be processed by the back end circuitry, the scan converter including a pixel identification line for
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`receiving tile identification data indicating which of the sets of tiles is to be processed by the
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`back end circuitry.
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`17.
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`(original) The graphics processing circuit of claim 14, wherein the third and fourth
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`graphics pipelines are on separate chips.
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`18.
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`(original) The graphics processing circuit of claim 14, further including a bridge
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`operative to transmit vertex data to each of the first, second, third and fourth graphics pipelines.
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`19.
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`(original) The graphics processing circuit of claim l7 wherein the data includes a
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`polygon and wherein each separate chip creates a bounding box around the polygon and wherein
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`each comer of the bounding box is checked against a super tile that belongs to each separate chip
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`and wherein if the bounding box does not overlap any of the super tiles associated with a
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`separate chip, then the processing circuit rejects the whole polygon and processes a next one.
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`20. (currently amended) A graphics processing method, comprising:
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`receiving vertex data for a primitive to be rendered;
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`generating pixel data in response to the vertex data;
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`passing the same pixel data to both of the at least two graphics pipelines on a same chip;
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`CHICAGO/#2018275.1
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`5
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`
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`determining the pixels within a set of tiles of a repeating tile pattern corresponding to
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`screen locations to be processed by a corresponding one of ‘th_eat least two graphics pipelines on
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`a same chip in response to the pixel data, the repeating tile pattern including a horizontally and
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`vertically repeating pattern of square regions;
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`performing pixel operations on the pixels within the determined set of tiles by the
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`corresponding one of the at least two graphics pipelines; and
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`transmitting the processed pixels to a memory controller, wherein the at
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`least two
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`graphics pipelines share the memory controller wherein the memogv_ controller transfers pixel
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`data from each of the at least two pipelines, to a shared memoLv_.
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`21.
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`(original) The graphics processing method of claim 20, wherein determining the
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`pixels within a set of tiles of the repeating tile pattern to be processed further comprises
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`determining the set of tiles that the corresponding graphics pipeline is responsible for.
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`22.
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`(original) The graphics processing method of claim 20, wherein determining the
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`pixels within a set of tiles of the repeating tile pattern to be processed further comprises
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`providing position coordinates of the pixels within the determined set of tiles to be processed to
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`the corresponding one of the at least two graphics pipelines.
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`23. (canceled)
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`24. (previously presented) A graphics processing circuit, comprising:
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`front end circuitry on a chip operative to generate pixel data in response to primitive data
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`for a primitive to be rendered;
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`first back end circuitry on the chip, coupled to the front end circuitry, operative to process
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`a first portion of the pixel data in response to position coordinates;
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`CHICAGO/#2018275.1
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`6
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`
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`a first scan converter on the chip, coupled between the front end circuitry and the first
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`back end circuitry, operative to determine which set of tiles of a repeating tile pattern are to be
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`processed by the first back end circuitry, the repeating tile pattern including a horizontally and
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`vertically repeating pattern of square regions, and operative to provide the position coordinates to
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`the first back end circuitry in response to the pixel data;
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`second back end circuitry on the chip, coupled to the front end circuitry, operative to
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`process a second portion of the pixel data in response to position coordinates;
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`a second scan converter on the chip, coupled between the front end circuitry and the
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`second back end circuitry, operative to determine which set of tiles of the repeating tile pattern
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`are to be processed by the second back end circuitry, and operative to provide the position
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`coordinates to the second back end circuitry in response to the pixel data; and
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`a memory controller on the chip, coupled to the first and second back end circuitry
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`operative to transmit and receive the processed pixel data.
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`25. (currently amended) A graphics processing circuit, comprising:
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`at least two graphics pipelines on a chip operative to process data in a corresponding set
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`of tiles of a repeating tile pattern corresponding to screen locations, a respective one of the at
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`least two graphics pipelines operative to process data in a dedicated tile, wherein the repeating
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`tile pattern includes a horizontally and vertically repeating pattern of regions;
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`wherein the horizontally and vertically repeating pattern of regions include NxM number
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`of pixels; and a memory controller on the chip, coupled to the at least two graphics pipelines on
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`the chip and operative to transfer pixel data between each of the two graphics pipelines and a
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`memoLv_ shared among the at least two graphics pipelines.
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`CHICAGO/#2018275.1
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`7
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`26. (canceled)
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`CHICAGO/#20 1 8275 .1
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`REMARKS
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`Applicants respectfully traverse and request reconsideration.
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`Claims 1-4, 7, l0, l2, l4 and 25 stand rejected under 35 U.S.C. § l03(a) as allegedly
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`being unpatentable over Maclnnis in view of Perego. This is a new ground of rejection.
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`Applicants wish to thank the Examiner for the remarks in the office action. Applicants have
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`amended claims to indicate what is believed to be inherent subject matter, that the memory
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`controller that is on chip with the at least two graphics pipelines transfers pixel data between
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`each of the first and second pipelines and a memory that is shared among the at least two on chip
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`pipelines.
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`Maclnnis is a conventional graphics processing circuit that includes a single pipeline and
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`corresponding memory controller on chip.
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`It is admitted that Maclnnis does not teach at least
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`two graphics pipelines on a same chip that process data in a corresponding set of tiles for a
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`repeating tile pattern corresponding to screen locations. Nor does it teach a plurality of graphics
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`pipelines and associated memory controller on the same chip in communication with the at least
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`two graphics pipelines wherein the memory controller transfers pixel data between each of the
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`two pipelines and a memory that is shared among the at least two graphic on chip pipelines. The
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`office action alleges that Perego teaches this subject matter.
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`The office alleges that the memory controller 3l0 in FIG. 3 is in communication with at
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`least two graphic pipelines but the office action appears to disregard the actual teachings of
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`Perego. Applicants respectfully submit that is improper to use hindsight reconstruction and
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`ignore the teachings of the reference as a whole in an effort to render a claim obvious. The
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`memory controller 3 l0 is intentionally left off of the modules 304 that include rendering engines
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`and their own dedicated memory. The purpose of the Perego structure is to “provide scalability
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`option to higher levels of aggregate memory bandwidth” (col. 2, lns. 53-57). Perego actually
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`CHICAGO/#2018275.1
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`9
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`CC
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`teaches
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`a system...that provides multiple discrete memory modules coupled to a common
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`memory controller [which is off chip from the dedicated memory modules]. Each memory
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`module includes a computing engine and a shared memory. A data processing task from the
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`memory controller can be partitioned among the different computing engines to allow parallel
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`processing of the various portions of the processing task.” (col. 7, lns. 35-42). As such, the
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`modules described in Perego that have rendering engines also have dedicated memory thereon
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`that are always described as being separate from the CPU/memory controller subsystem and
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`memory controller 310. This is because the separate modules fiom the memory controller 310
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`provides the specific scalability provided by the architecture of Perego. Perego specifically
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`requires the separate memory controller 310 to be off chip and separate from the memory
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`modules 304. As such, combining the graphic pipeline teachings of Perego with those of
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`Maclnnis would render the Perego system inoperable.
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`In addition, or alternatively, the office action alleges that the shared memories 3l4 are
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`each part of main memory and “so are considered to be one memory”. However, Applicants
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`respectfully submit that this is a misconstruction of the actual teachings of the reference. The
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`shared memories 3l4 are actually dedicated memories that are each dedicated to a dedicated
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`graphics pipeline and in no embodiment are these dedicated memories that are on separate
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`modules ever described as storing data fiom more than one rendering engine. This is because
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`this would again eliminate the advantages of Perego’s scalable unified memory architecture. As
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`claimed, not only is the memory controller on chip and in communication with two graphics
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`pipelines that are also on the same chip, but the memory controller is in communication with a
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`memory that is shared among the at least two graphics on chip pipelines.
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`CHICAGO/#2018275.1
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`l0
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`FIG. 8 has been alleged as being properly combinable to teach multiple rendering engines
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`on the same chip and an on chip memory controller that communicates with the memory that is
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`shared among the at least two graphics on chip pipelines. However, as shown in FIG. 8, it is
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`clear that memory devices 804 are only in communication with rendering engine 802 whereas
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`memory devices 812 are only in communication with rendering engine 810. These memories are
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`dedicated and are separate and are not shared among graphics pipelines or rendering engines 802
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`and 810. Accordingly, Applicants respectfully request reconsideration and believe that the
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`claims are in condition for allowance. The dependent claims are believed to add additional novel
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`and non-obvious subject matter.
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`As to claim 25, Applicants respectfully reassert the relevant remarks made above with
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`respect to claim 1 and as such, this claim is also believed to be in condition for allowance.
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`Claims 5, 18, and 24 stand rejected under 35 U.S.C.
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`§
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`l03(a) as allegedly being
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`unpatentable over MacInnis in view of Perego further in view of Kelleher. Claims 5 and 18 are
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`believed to be in condition for allowance as adding novel and non-obvious subject matter and/or
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`being based on allowable base claims.
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`As to independent claim 24, it is alleged that Perego teaches “that two graphics pipelines
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`are the same chip, and so the front end circuitry, first back end circuitry, and second back end
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`circuitry on the same chip.” (office action, page 14) referring to FIG. 8. However, Perego does
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`not teach nor does nit contemplate both front and back end circuitry on the chip both coupled to
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`the same front end circuitry as claimed.
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`In fact, FIG. 8 actually shows separate front end
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`circuitry being employed since separate rendering engines 802 and 810 are employed and each of
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`these are identical in structure. There is no teaching or suggestion in Perego as alleged and as
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`such, this claim is in condition for allowance.
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`CHICAGO/#2018275.1
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`l l
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`Claims 6 and 17 stand rejected under 35 U.S.C. § l03(a) as allegedly being unpatentable
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`oVer Maclnnis, in View of Perego further in View of Furtner. These claims are believed to add
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`additional noVel and non-obVious subject matter and are also allowable at least as depending on
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`allowable base claims.
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`Claims ll, l3, l5, and 16 stand rejected under 35 U.S.C. § l03(a) as allegedly being
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`unpatentable oVer Maclnnis, in View of Perego further in View of Kelleher, further in View of
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`Hamburg. These claims are belieVed to add additional noVel and non-obVious subject matter and
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`are also allowable at least as depending on allowable base claims.
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`Claim 19 stands rejected under 35 U.S.C. § l03(a) as allegedly being unpatentable oVer
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`Maclnnis, in View of Perego, further in View of Furtner, further in View of Kent. This claim is
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`belieVed to add additional noVel and non-obVious subject matter and is also allowable at least as
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`depending on an allowable base claim.
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`Claims 20-22 stand rejected under 35 U.S.C. § l03(a) as allegedly being unpatentable
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`oVer Perego. These claims are belieVed to add additional noVel and non-obVious subject matter
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`and are also allowable at least as depending on allowable base claims.
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`The dependent claims add additional noVel and non-obVious subject matter.
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`CHICAGO/#2018275.1
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`l2
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`Applicants respectfully submit
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`that
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`the claims are in condition for allowance and
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`respectfully request that a timely Notice of Allowance be issued in this case. The Examiner is
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`invited to contact the below listed attorney if the Examiner believes that a telephone conference
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`will advance the prosecution of this application.
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`Respectfully submitted,
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`/Christopher J. Reckamp/
`By:
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`Christopher J. Reckamp
`Registration No. 34,414
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`Date: JanuaLv_ 25, 2010
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`Vedder Price P.C.
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`222 North LaSalle Street, Suite 2600
`Chicago, Illinois 60601
`phone: (312) 609-7599
`fax: (312) 609-5005
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`CHICAGO/#2018275.1
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`13