IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Applicants: Mark M. Leather et al.
`Serial No.: 10/459,797
`
`Examiner: Joni Hsu
`Art Unit: 2628
`
`Filing Date: June 12, 2003
`Confirmation No.: 4148
`
`Our File No.: 00l00.02.0053
`
`Title: DIVIDING WORK AMONG MULTIPLE GRAPHICS PIPELINES USING
`
`A SUPER-TILING TECHNIQUE
`
`Mail Stop Amendment
`Commissioner for Patents
`
`P.O. Box 1450
`
`Alexandria, VA 22313-1450
`
`Dear Sir:
`
`AMENDMENT AND RESPONSE
`
`In response to the Office Action mailed July 23, 2009, Applicants petition for a three
`
`month extension of time and respond as follows:
`
`Amendments to the Claims begin on page 2 of this paper.
`
`Remarks begin on page 9 of this paper.
`
`CHICAGO/#2018275.1
`
`l
`
`UNIFIED 1012
`
`UNIFIED 1012
`
`
`
`Applicants: Mark M. Leather et al.
`Serial No.: 10/459,797
`
`Examiner: Joni Hsu
`Art Unit: 2628
`
`Filing Date: June 12, 2003
`Confirmation No.: 4148
`
`Our File No.: 00l00.02.0053
`
`Title: DIVIDING WORK AMONG MULTIPLE GRAPHICS PIPELINES USING
`
`A SUPER-TILING TECHNIQUE
`
`Mail Stop Amendment
`Commissioner for Patents
`
`P.O. Box 1450
`
`Alexandria, VA 22313-1450
`
`Dear Sir:
`
`AMENDMENT AND RESPONSE
`
`In response to the Office Action mailed July 23, 2009, Applicants petition for a three
`
`month extension of time and respond as follows:
`
`Amendments to the Claims begin on page 2 of this paper.
`
`Remarks begin on page 9 of this paper.
`
`CHICAGO/#2018275.1
`
`l
`
`UNIFIED 1012
`
`UNIFIED 1012
`
`
`
`Amendments to the Claims:
`
`Re-write the claims as set forth below. This listing of claims will replace all prior versions and
`listings of claims in the application:
`
`Listing of Claims:
`
`1. (currently amended) A graphics processing circuit, comprising:
`
`at
`
`least
`
`two graphics pipelines on a same chip operative to process data in a
`
`corresponding set of tiles of a repeating tile pattern corresponding to screen locations, a
`
`respective one of the at least two graphics pipelines operative to process data in a dedicated tile;
`
`and
`
`a memory controller on the chip in communication with the at
`
`least two graphics
`
`pipelines, operative to transfer pixel data between each of a first pipeline and a second pipeline
`
`and a memory shared among the at least two graphics pipelines;
`
`wherein the repeating tile pattern includes a horizontally and vertically repeating pattern
`
`of square regions.
`
`2.
`
`(original) The graphics processing circuit of claim 1, wherein the square regions
`
`comprise a two dimensional partitioning of memory.
`
`3.
`
`(original) The graphics processing circuit of claim 2, wherein the memory is a frame
`
`buffer.
`
`4.
`
`(original) The graphics processing circuit of claim 1, wherein each of the at least two
`
`graphics pipelines further includes front end circuitry operative to receive vertex data and
`
`generate pixel data corresponding to a primitive to be rendered, and back end circuitry, coupled
`
`to the front end circuitry, operative to receive and process a portion of the pixel data.
`
`CHICAGO/#2018275.1
`
`2
`
`
`
`5.
`
`(original) The graphics processing circuit of claim 4, wherein each of the at least two
`
`graphics pipelines further includes a scan converter, coupled to the back end circuitry, operative
`
`to determine the portion of the pixel data to be processed by the back end circuitry.
`
`6.
`
`(original) The graphics processing circuit of claim 1, wherein each tile of the set of
`
`tiles further comprises a 16x16 pixel array.
`
`7. (original) The graphics processing circuit of claim 4, wherein the at least two graphics
`
`pipelines separately receive the pixel data from the front end circuitry.
`
`8. (canceled)
`
`9. (canceled)
`
`10.
`
`(previously presented) The graphics processing circuit of claim 7, wherein a first of
`
`the at least two graphics pipelines processes the pixel data only in a first set of tiles in the
`
`repeating tile pattern.
`
`ll.
`
`(original) The graphics processing circuit of claim 10, wherein the first of the at
`
`least two graphics pipelines further includes a scan converter, coupled to the front end circuitry
`
`and the back end circuitry, operative to provide position coordinates of the pixels within the first
`
`set of tiles to be processed by the back end circuitry, the scan converter including a pixel
`
`identification line for receiving tile identification data indicating which of the set of tiles is to be
`
`processed by the back end circuitry.
`
`CHICAGO/#2018275.1
`
`3
`
`
`
`12.
`
`(previously presented) The graphics processing circuit of claim 1, wherein a second
`
`of the at least two graphics pipelines processes the data only in a second set of tiles in the
`
`repeating tile pattern.
`
`13.
`
`(previously presented) The graphics processing circuit of claim 12, wherein the
`
`second of the at least two graphics pipelines further includes a scan converter, coupled to front
`
`end circuitry and back end circuitry, operative to provide position coordinates of the pixels
`
`within the second set of tiles to be processed by the back end circuitry, the scan converter
`
`including a pixel identification line for receiving tile identification data indicating which of the
`
`set of tiles is to be processed by the back end circuitry.
`
`14.
`
`(original) The graphics processing circuit of claim l
`
`including a third graphics
`
`pipeline and a fourth graphics pipeline, wherein the third graphics pipeline includes front end
`
`circuitry operative to receive vertex data and generate pixel data corresponding to a primitive to
`
`be rendered, and back end circuitry, coupled to the front end circuitry, operative to receive and
`
`process the pixel data in a third set of tiles in the repeating tile pattern, and wherein the fourth
`
`graphics pipeline includes front end circuitry operative to receive vertex data and generate pixel
`
`data corresponding to a primitive to be rendered, and back end circuitry, coupled to the front end
`
`circuitry, operative to receive and process the pixel data in a fourth set of tiles in the repeating
`
`tile pattern.
`
`15.
`
`(original) The graphics processing circuit of claim l4, wherein the third graphics
`
`pipeline further includes a scan converter, coupled to the front end circuitry and the back end
`
`circuitry, operative to provide position coordinates of the pixels within the third set of tiles to be
`
`processed by the back end circuitry, the scan converter including a pixel identification line for
`
`CHICAGO/#2018275.1
`
`4
`
`
`
`receiving tile identification data indicating which of the sets of tiles is to be processed by the
`
`back end circuitry.
`
`16.
`
`(original) The graphics processing circuit of claim 14, wherein the fourth graphics
`
`pipeline further includes a scan converter, coupled to the front end circuitry and the back end
`
`circuitry, operative to provide position coordinates of the pixels within the fourth set of tiles to
`
`be processed by the back end circuitry, the scan converter including a pixel identification line for
`
`receiving tile identification data indicating which of the sets of tiles is to be processed by the
`
`back end circuitry.
`
`17.
`
`(original) The graphics processing circuit of claim 14, wherein the third and fourth
`
`graphics pipelines are on separate chips.
`
`18.
`
`(original) The graphics processing circuit of claim 14, further including a bridge
`
`operative to transmit vertex data to each of the first, second, third and fourth graphics pipelines.
`
`19.
`
`(original) The graphics processing circuit of claim l7 wherein the data includes a
`
`polygon and wherein each separate chip creates a bounding box around the polygon and wherein
`
`each comer of the bounding box is checked against a super tile that belongs to each separate chip
`
`and wherein if the bounding box does not overlap any of the super tiles associated with a
`
`separate chip, then the processing circuit rejects the whole polygon and processes a next one.
`
`20. (currently amended) A graphics processing method, comprising:
`
`receiving vertex data for a primitive to be rendered;
`
`generating pixel data in response to the vertex data;
`
`passing the same pixel data to both of the at least two graphics pipelines on a same chip;
`
`CHICAGO/#2018275.1
`
`5
`
`
`
`determining the pixels within a set of tiles of a repeating tile pattern corresponding to
`
`screen locations to be processed by a corresponding one of ‘th_eat least two graphics pipelines on
`
`a same chip in response to the pixel data, the repeating tile pattern including a horizontally and
`
`vertically repeating pattern of square regions;
`
`performing pixel operations on the pixels within the determined set of tiles by the
`
`corresponding one of the at least two graphics pipelines; and
`
`transmitting the processed pixels to a memory controller, wherein the at
`
`least two
`
`graphics pipelines share the memory controller wherein the memogv_ controller transfers pixel
`
`data from each of the at least two pipelines, to a shared memoLv_.
`
`21.
`
`(original) The graphics processing method of claim 20, wherein determining the
`
`pixels within a set of tiles of the repeating tile pattern to be processed further comprises
`
`determining the set of tiles that the corresponding graphics pipeline is responsible for.
`
`22.
`
`(original) The graphics processing method of claim 20, wherein determining the
`
`pixels within a set of tiles of the repeating tile pattern to be processed further comprises
`
`providing position coordinates of the pixels within the determined set of tiles to be processed to
`
`the corresponding one of the at least two graphics pipelines.
`
`23. (canceled)
`
`24. (previously presented) A graphics processing circuit, comprising:
`
`front end circuitry on a chip operative to generate pixel data in response to primitive data
`
`for a primitive to be rendered;
`
`first back end circuitry on the chip, coupled to the front end circuitry, operative to process
`
`a first portion of the pixel data in response to position coordinates;
`
`CHICAGO/#2018275.1
`
`6
`
`
`
`a first scan converter on the chip, coupled between the front end circuitry and the first
`
`back end circuitry, operative to determine which set of tiles of a repeating tile pattern are to be
`
`processed by the first back end circuitry, the repeating tile pattern including a horizontally and
`
`vertically repeating pattern of square regions, and operative to provide the position coordinates to
`
`the first back end circuitry in response to the pixel data;
`
`second back end circuitry on the chip, coupled to the front end circuitry, operative to
`
`process a second portion of the pixel data in response to position coordinates;
`
`a second scan converter on the chip, coupled between the front end circuitry and the
`
`second back end circuitry, operative to determine which set of tiles of the repeating tile pattern
`
`are to be processed by the second back end circuitry, and operative to provide the position
`
`coordinates to the second back end circuitry in response to the pixel data; and
`
`a memory controller on the chip, coupled to the first and second back end circuitry
`
`operative to transmit and receive the processed pixel data.
`
`25. (currently amended) A graphics processing circuit, comprising:
`
`at least two graphics pipelines on a chip operative to process data in a corresponding set
`
`of tiles of a repeating tile pattern corresponding to screen locations, a respective one of the at
`
`least two graphics pipelines operative to process data in a dedicated tile, wherein the repeating
`
`tile pattern includes a horizontally and vertically repeating pattern of regions;
`
`wherein the horizontally and vertically repeating pattern of regions include NxM number
`
`of pixels; and a memory controller on the chip, coupled to the at least two graphics pipelines on
`
`the chip and operative to transfer pixel data between each of the two graphics pipelines and a
`
`memoLv_ shared among the at least two graphics pipelines.
`
`CHICAGO/#2018275.1
`
`7
`
`
`
`26. (canceled)
`
`CHICAGO/#20 1 8275 .1
`
`
`
`REMARKS
`
`Applicants respectfully traverse and request reconsideration.
`
`Claims 1-4, 7, l0, l2, l4 and 25 stand rejected under 35 U.S.C. § l03(a) as allegedly
`
`being unpatentable over Maclnnis in view of Perego. This is a new ground of rejection.
`
`Applicants wish to thank the Examiner for the remarks in the office action. Applicants have
`
`amended claims to indicate what is believed to be inherent subject matter, that the memory
`
`controller that is on chip with the at least two graphics pipelines transfers pixel data between
`
`each of the first and second pipelines and a memory that is shared among the at least two on chip
`
`pipelines.
`
`Maclnnis is a conventional graphics processing circuit that includes a single pipeline and
`
`corresponding memory controller on chip.
`
`It is admitted that Maclnnis does not teach at least
`
`two graphics pipelines on a same chip that process data in a corresponding set of tiles for a
`
`repeating tile pattern corresponding to screen locations. Nor does it teach a plurality of graphics
`
`pipelines and associated memory controller on the same chip in communication with the at least
`
`two graphics pipelines wherein the memory controller transfers pixel data between each of the
`
`two pipelines and a memory that is shared among the at least two graphic on chip pipelines. The
`
`office action alleges that Perego teaches this subject matter.
`
`The office alleges that the memory controller 3l0 in FIG. 3 is in communication with at
`
`least two graphic pipelines but the office action appears to disregard the actual teachings of
`
`Perego. Applicants respectfully submit that is improper to use hindsight reconstruction and
`
`ignore the teachings of the reference as a whole in an effort to render a claim obvious. The
`
`memory controller 3 l0 is intentionally left off of the modules 304 that include rendering engines
`
`and their own dedicated memory. The purpose of the Perego structure is to “provide scalability
`
`option to higher levels of aggregate memory bandwidth” (col. 2, lns. 53-57). Perego actually
`
`CHICAGO/#2018275.1
`
`9
`
`
`
`CC
`
`teaches
`
`a system...that provides multiple discrete memory modules coupled to a common
`
`memory controller [which is off chip from the dedicated memory modules]. Each memory
`
`module includes a computing engine and a shared memory. A data processing task from the
`
`memory controller can be partitioned among the different computing engines to allow parallel
`
`processing of the various portions of the processing task.” (col. 7, lns. 35-42). As such, the
`
`modules described in Perego that have rendering engines also have dedicated memory thereon
`
`that are always described as being separate from the CPU/memory controller subsystem and
`
`memory controller 310. This is because the separate modules fiom the memory controller 310
`
`provides the specific scalability provided by the architecture of Perego. Perego specifically
`
`requires the separate memory controller 310 to be off chip and separate from the memory
`
`modules 304. As such, combining the graphic pipeline teachings of Perego with those of
`
`Maclnnis would render the Perego system inoperable.
`
`In addition, or alternatively, the office action alleges that the shared memories 3l4 are
`
`each part of main memory and “so are considered to be one memory”. However, Applicants
`
`respectfully submit that this is a misconstruction of the actual teachings of the reference. The
`
`shared memories 3l4 are actually dedicated memories that are each dedicated to a dedicated
`
`graphics pipeline and in no embodiment are these dedicated memories that are on separate
`
`modules ever described as storing data fiom more than one rendering engine. This is because
`
`this would again eliminate the advantages of Perego’s scalable unified memory architecture. As
`
`claimed, not only is the memory controller on chip and in communication with two graphics
`
`pipelines that are also on the same chip, but the memory controller is in communication with a
`
`memory that is shared among the at least two graphics on chip pipelines.
`
`CHICAGO/#2018275.1
`
`l0
`
`
`
`FIG. 8 has been alleged as being properly combinable to teach multiple rendering engines
`
`on the same chip and an on chip memory controller that communicates with the memory that is
`
`shared among the at least two graphics on chip pipelines. However, as shown in FIG. 8, it is
`
`clear that memory devices 804 are only in communication with rendering engine 802 whereas
`
`memory devices 812 are only in communication with rendering engine 810. These memories are
`
`dedicated and are separate and are not shared among graphics pipelines or rendering engines 802
`
`and 810. Accordingly, Applicants respectfully request reconsideration and believe that the
`
`claims are in condition for allowance. The dependent claims are believed to add additional novel
`
`and non-obvious subject matter.
`
`As to claim 25, Applicants respectfully reassert the relevant remarks made above with
`
`respect to claim 1 and as such, this claim is also believed to be in condition for allowance.
`
`Claims 5, 18, and 24 stand rejected under 35 U.S.C.
`
`§
`
`l03(a) as allegedly being
`
`unpatentable over MacInnis in view of Perego further in view of Kelleher. Claims 5 and 18 are
`
`believed to be in condition for allowance as adding novel and non-obvious subject matter and/or
`
`being based on allowable base claims.
`
`As to independent claim 24, it is alleged that Perego teaches “that two graphics pipelines
`
`are the same chip, and so the front end circuitry, first back end circuitry, and second back end
`
`circuitry on the same chip.” (office action, page 14) referring to FIG. 8. However, Perego does
`
`not teach nor does nit contemplate both front and back end circuitry on the chip both coupled to
`
`the same front end circuitry as claimed.
`
`In fact, FIG. 8 actually shows separate front end
`
`circuitry being employed since separate rendering engines 802 and 810 are employed and each of
`
`these are identical in structure. There is no teaching or suggestion in Perego as alleged and as
`
`such, this claim is in condition for allowance.
`
`CHICAGO/#2018275.1
`
`l l
`
`
`
`Claims 6 and 17 stand rejected under 35 U.S.C. § l03(a) as allegedly being unpatentable
`
`oVer Maclnnis, in View of Perego further in View of Furtner. These claims are believed to add
`
`additional noVel and non-obVious subject matter and are also allowable at least as depending on
`
`allowable base claims.
`
`Claims ll, l3, l5, and 16 stand rejected under 35 U.S.C. § l03(a) as allegedly being
`
`unpatentable oVer Maclnnis, in View of Perego further in View of Kelleher, further in View of
`
`Hamburg. These claims are belieVed to add additional noVel and non-obVious subject matter and
`
`are also allowable at least as depending on allowable base claims.
`
`Claim 19 stands rejected under 35 U.S.C. § l03(a) as allegedly being unpatentable oVer
`
`Maclnnis, in View of Perego, further in View of Furtner, further in View of Kent. This claim is
`
`belieVed to add additional noVel and non-obVious subject matter and is also allowable at least as
`
`depending on an allowable base claim.
`
`Claims 20-22 stand rejected under 35 U.S.C. § l03(a) as allegedly being unpatentable
`
`oVer Perego. These claims are belieVed to add additional noVel and non-obVious subject matter
`
`and are also allowable at least as depending on allowable base claims.
`
`The dependent claims add additional noVel and non-obVious subject matter.
`
`CHICAGO/#2018275.1
`
`l2
`
`
`
`Applicants respectfully submit
`
`that
`
`the claims are in condition for allowance and
`
`respectfully request that a timely Notice of Allowance be issued in this case. The Examiner is
`
`invited to contact the below listed attorney if the Examiner believes that a telephone conference
`
`will advance the prosecution of this application.
`
`Respectfully submitted,
`
`/Christopher J. Reckamp/
`By:
`
`Christopher J. Reckamp
`Registration No. 34,414
`
`Date: JanuaLv_ 25, 2010
`
`Vedder Price P.C.
`
`222 North LaSalle Street, Suite 2600
`Chicago, Illinois 60601
`phone: (312) 609-7599
`fax: (312) 609-5005
`
`CHICAGO/#2018275.1
`
`13
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