UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Vi
`'nia 22313-1450
`www.uspto.go
`
`APPLICATION NO.
`
`F ING DATE
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`CONF {MATION NO.
`
`10/459,797
`
`06/12/2003
`
`Mark M. Leather
`
`00100.02.0053
`
`4148
`
`29153
`7590
`07/23/2009
`ADVANCED MICRO DEVICES,INC.
`C/O VEDDER PRICE P.C.
`222 N.LASALLE STREET
`CHICAGO, IL 60601
`
`Hsu, low
`
`2628
`
`MAIL DATE
`
`07/23/2009
`
`PAPER NUMBER
`
`DELIVERY MODE
`
`PAPER
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`PTOL—90A (Rev. 04/07)
`
`UNIFIED 1011
`
`UNIFIED 1011
`
`

`
`Office Action Summary
`
`Application No.
`
`App|icant(s)
`
`10/459,797
`
`Examine,
`
`LEATHER ET AL.
`
`A,, Unit
`
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE 3 MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`- Extensions of time may be available under the provisions of 37 CFR 1.136(a).
`In no event, however, may a reply be timely filed
`after SIX (6) MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1)IXI Responsive to communication(s) filed on 13 May 2009.
`
`2a)I:I This action is FINAL.
`
`2b)IXI This action is non-final.
`
`3)I:I Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`
`closed in accordance with the practice under Ex parte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`Disposition of Claims
`
`4)IXI C|aim(s) 1-7 10-22 24 and 25 is/are pending in the application.
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`4a) Of the above c|aim(s)
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`is/are withdrawn from consideration.
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`5)I:I C|aim(s) j is/are allowed.
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`6)IXI C|aim(s) 1-7 10-22 24 and 25 is/are rejected.
`
`7)I:I C|aim(s) j is/are objected to.
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`8)I:I C|aim(s) j are subject to restriction and/or election requirement.
`
`Application Papers
`
`9)I:I The specification is objected to by the Examiner.
`
`10)I:I The drawing(s) filed on
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`is/are: a)I:I accepted or b)I:I objected to by the Examiner.
`
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
`
`11)I:I The oath or declaration is objected to by the Examiner. Note the attached Office Action or form PTO-152.
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`Priority under 35 U.S.C. § 119
`
`12)I:I Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
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`a)I:I All
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`b)I:I Some * c)I:I None of:
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`Certified copies of the priority documents have been received.
`
`Certified copies of the priority documents have been received in Application No.
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`Copies of the certified copies of the priority documents have been received in this National Stage
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`application from the International Bureau (PCT Rule 17.2(a)).
`
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attach ment(s)
`
`1) D Notice of References Cited (PTO-892)
`2) D Notice of Draftsperson's Patent Drawing Review (PTO-948)
`3) IXI Information Disclosure Statement(s) (PTO/SB/08)
`Paper No(s)/Mail Date 5/13/09.
`U.S. Patent and Trademark Office
`
`4) D Interview Summary (PTO-413)
`Paper N0(S)/IVI3” Data E
`5) I:I Noiice Oi informal Paieiii Appiicaiion
`6) D Other:
`.
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`PTOL-326 (Rev. 08-06)
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`Office Action Summary
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`Part of Paper No./Mail Date 20090513
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`

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`Application/Control Number: 10/459,797
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`Page 2
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`Art Unit: 2628
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`DETAILED ACTION
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`Continued Examination Under 3 7 CFR 1.114
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`1.
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`A request for continued examination under 37 CFR l.l 14, including the fee set forth in
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`37 CFR l.l7(e), was filed in this application after final rejection. Since this application is
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`eligible for continued examination under 37 CFR l.l l4, and the fee set forth in 37 CFR l.l7(e)
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`has been timely paid, the finality of the previous Office action has been withdrawn pursuant to
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`37 CFR 1.114. Applicant's submission filed on May 13, 2009 has been entered.
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`Information Disclosure Statement
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`2.
`
`The information disclosure statement (ID S) submitted on May 13, 2009 was filed after
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`the mailing date of the application on June 12, 2003. The submission is in compliance with the
`
`provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being
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`considered by the examiner.
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`Response to Arguments
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`3.
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`Applicant’s arguments, see p. 8-12, filed May 13, 2009, with respect to the rejection(s) of
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`claim(s) 1-7, 10-22, 24, and 25 under 35 U.S.C. l03(a) have been fully considered and are
`
`persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration,
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`a new ground(s) of rejection is made in view of Maclnnis (US006570579Bl) in view of Perego
`
`(US006864896B2).
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`4.
`
`As per Claim 1, Applicant argues that in the “Response to Arguments” section, the
`
`Examiner states "Claim 1 recites ‘at least two graphics pipelines on a same chip‘ and this is what
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`Perego teaches'". However, in the rejection, it is Furtner (US006778l77Bl) that is cited as
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`

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`Page 3
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`Art Unit: 2628
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`teaching graphics pipelines are on a same chip. As it currently stands, Applicants are unable to
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`determine which reference the Examiner is using (p. 8).
`
`In reply, the Examiner points out that Furtner was used because it more explicitly teaches
`
`the limitation. However, the Examiner agrees that this may be confusing, and is no longer
`
`applying Furtner to teach this limitation.
`
`5.
`
`Applicant argues that Perego states that as to the scalability which is a requirement of
`
`Perego, “this ability to add and remove memory modules 304 provides an upgradeable and
`
`scalable memory and computing architecture.” Perego requires the separate memory controller
`
`310 to be separate from the separate memory controller that is coupled to the memory modules
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`304. Therefore, the teaching from Maclnnis that the memory controller is also on the same chip
`
`cannot be combined with Perego because removing the scalability renders the Perego invention
`
`inoperable for its intended purpose (p. 8-9).
`
`In reply, the Examiner agrees. However, new grounds of rejection are made so that
`
`Maclnnis is used as the main reference and the teaching of the repeating tile pattern from Perego
`
`is combined into the main reference Maclnnis. Therefore, Perego is now only being used for the
`
`teaching of the repeating tile pattern, not for the teaching of the scalability. Since Perego is now
`
`only being used as a secondary reference, the Examiner is no longer relying on the entire device
`
`of Perego for the rejection.
`
`6.
`
`As per Claim 4, Applicant argues that there is no front end circuitry described related to
`
`the CPU 308 in Perego since admitted in the "Response to Arguments" section, the CPU of
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`Perego does not generate pixel data (p. 10-11).
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`Page 4
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`Art Unit: 2628
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`In reply, the Examiner points out that Perego teaches that the CPU sorts the primitive
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`data according to the spatial region of the rendering surface (e.g., the x and y coordinates)
`
`covered by that primitive, and the rendering surface is divided into multiple rectangular regions
`
`of pixels (col. 5, lines 19-27). One of ordinary skill in the art would understand that data
`
`pertaining to the x and y coordinates covered by the primitive would include vertex data. The
`
`main memory is used to store data which are referenced during the execution of the programs
`
`(col. 1, lines 18-21). Therefore, the CPU is operative to receive vertex data (data pertaining to
`
`the x and y coordinates covered by the primitive) from the main memory and generate pixel
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`data corresponding to a primitive to be rendered (col. 5, lines 19-27; col. 1, lines 18-21). Perego
`
`teaches that rendering engine 312 is coupled to the CPU, and is operative to receive and process
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`a rectangular region of pixel data (col. 3, line 64-col. 4, line 2; col. 5, lines 19-44). Since the
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`CPU is coupled to the rendering engine 3 l2, and the CPU and the rendering engine 3 l2 both
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`perform graphics processing, and, the CPU performs the operations of the front end circuitry,
`
`and the rendering engine 3 l2 performs the operations of the back end circuitry, the CPU and the
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`rendering engine 3 l2 are considered to be part of a graphics pipeline, and the CPU is considered
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`to be the front end circuitry included in the graphics pipeline.
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`7.
`
`As per Claim 24, Applicant argues that Perego does not describe multiple backend
`
`circuitry on a common chip nor common front end circuitry and memory controller on a
`
`common chip (p. 11).
`
`In reply, the Examiner points out that Perego shows in Fig. 8 that in one embodiment, a
`
`memory module 800 contains two different rendering engines 802 and 810 (Fig. 8; col. 6, lines
`
`61-62), and therefore at least two graphics pipelines (802, 810) are on a same memory module
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`Page 5
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`Art Unit: 2628
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`800. From Fig. 8 and from the description in Perego, one of ordinary skill in the art would
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`understand that a memory module is equivalent to a chip. Therefore, Perego teaches that two
`
`graphics pipelines are on the same chip, and so first backend circuitry (first rendering engine
`
`312) and second backend circuitry (second rendering engine 312) (col. 3, lines 65-67; col. 4,
`
`liens 1-53; col. 5, lines 32-44) are on a common chip. In response to applicant's arguments
`
`against the references individually, one cannot show nonobviousness by attacking references
`
`individually where the rejections are based on combinations of references. See In re Keller, 642
`
`F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & C0., 800 F.2d 1091, 231 USPQ 375
`
`(Fed. Cir. 1986). Maclnnis is used to expressly teach common front end circuitry and memory
`
`controller are on a common chip.
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`8.
`
`As per Claim 20, Applicant argues that Perego does not teach passing the same pixel data
`
`to both of the two graphics pipelines on a same chip. (See for example, Specification describing
`
`shared front end). Perego does not teach determining the pixels within a set of tiles of the
`
`repeating pattern which are to be processed by corresponding graphics pipeline on the same chip
`
`in response to pixel data (p. 12).
`
`In reply, the Examiner points out that Perego teaches a shared front end (308, Fig. 3) that
`
`passes the pixel data to both of the two graphics pipelines (first rendering engine 312 and second
`
`rendering engine 312) (col. 3, line 63-col. 4, line 2; col. 5, lines 19-44), similarly as what is
`
`described in the instant specification, and so Perego teaches passing the same pixel data to both
`
`of the two graphics pipelines. Perego shows in Fig. 8 that in one embodiment, a memory module
`
`800 contains two different rendering engines 802 and 810 (Fig. 8; col. 6, lines 61-62), and
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`therefore at least two graphics pipelines (802, 810) are on a same memory module 800. From
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`Page 6
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`Art Unit: 2628
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`Fig. 8 and from the description in Perego, one of ordinary skill in the art would understand that a
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`memory module is equivalent to a chip. Therefore, Perego teaches that two graphics pipelines
`
`are on the same chip. Perego teaches determining the pixels within a set of tiles of the repeating
`
`pattern which are to be processed by corresponding graphics pipeline on the same chip in
`
`response to pixel data (col. 5, lines 19-44).
`
`Claim Rejections - 35 USC § 1 03
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`9.
`
`The following is a quotation of 35 U.S.C. l03(a) which forms the basis for all
`
`obviousness rejections set forth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in
`section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are
`such that the subject matter as a whole would have been obvious at the time the invention was made to a person
`having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the
`manner in which the invention was made.
`
`10.
`
`The factual inquiries set forth in Graham v. John Deere C0., 383 U.S. 1, 148 USPQ 459
`
`(1966), that are applied for establishing a background for determining obviousness under 35
`
`U.S.C. l03(a) are summarized as follows:
`
`.-'>P°.'\’.*‘
`
`Determining the scope and contents of the prior art.
`Ascertaining the differences between the prior art and the claims at issue.
`Resolving the level of ordinary skill in the pertinent art.
`Considering objective evidence present in the application indicating obviousness
`or nonobviousness.
`
`11.
`
`Claims 1-4, 7, 10, 12, 14, and 25 are rejected under 35 U.S.C. l03(a) as being
`
`unpatentable over Maclnnis (US006570579Bl) in view of Perego (US006864896B2).
`
`12.
`
`As per Claim 1, Maclnnis teaches a graphics processing circuit, comprising: a graphics
`
`pipeline (58, Fig. 2) on a chip (10); a memory controller (54) on the chip (10), as shown in Fig. 2
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`(col. 4, lines 65-67; col. 5, lines 36-41), in communication with the graphics pipeline (58),
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`Page 7
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`Art Unit: 2628
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`operative to transfer pixel data between the pipeline (58) and a memory (col. 6, lines 10-13, 59-
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`66).
`
`However, Maclnnis does not teach at least two graphics pipelines on the same chip
`
`operative to process data in a corresponding set of tiles of a repeating tile pattern corresponding
`
`to screen locations, a respective one of the at least two graphics pipelines operative to process
`
`data in a dedicated tile; wherein the repeating tile pattern includes a horizontally and vertically
`
`repeating pattern of square regions. However, Perego teaches graphics processing circuit (300,
`
`Fig. 3; col. 3, lines 61-63) having at least 2 graphics pipelines (312) operative to process data in
`
`corresponding set of tiles of repeating tile pattern corresponding to screen locations, respective
`
`one of at least 2 graphics pipelines operative to process data in dedicated tile (col. 5, lines 19-27,
`
`38-44); and memory controller (310, Fig. 3) in communication with at least 2 graphics pipelines
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`312, operative to transfer pixel data between each of 15‘ pipeline and 2nd pipeline and shared
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`memories 314 (col. 3, lines 65-67; col. 4, lines 1-10, 48-65). Shared memories 314 are each part
`
`of main memory (col. 1, lines 44-54; col. 3, lines 3-6), and so are considered to be one memory.
`
`Repeating tile pattern includes horizontally and vertically repeating pattern of regions of square
`
`regions, as shown in Fig. 5 (col. 5, lines 19-27, 38-44). Perego describes “Improvements in
`
`integrated circuit design and manufacturing technologies allow higher levels of integration,
`
`thereby allowing an increasing number of subsystems to be integrated into a single device. This
`
`increased integration reduces the total number of components in a system, such as a computer
`
`system. As subsystems with high memory performance requirements (such as graphics
`
`subsystems) are combined with the traditional main memory controller, the resulting architecture
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`may provide a single high-perforrnance main memory interface” (col. 1, lines 34-43). Perego
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`Page 8
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`Art Unit: 2628
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`shows in Fig. 8 that in one embodiment, a memory module 800 contains two different rendering
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`engines 802 and 810 (Fig. 8; col. 6, lines 61-62), and therefore at least two graphics pipelines
`
`(802, 810) are on a same memory module 800. From Fig. 8 and from the description in Perego,
`
`one of ordinary skill in the art would understand that a memory module is equivalent to a chip.
`
`Therefore, Perego teaches that two graphics pipelines are on the same chip.
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify Maclnnis to include at least two graphics pipelines on the same chip
`
`operative to process data in a corresponding set of tiles of a repeating tile pattern corresponding
`
`to screen locations, a respective one of the at least two graphics pipelines operative to process
`
`data in a dedicated tile; wherein the repeating tile pattern includes a horizontally and vertically
`
`repeating pattern of square regions because Perego suggests that this parallel processing
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`significantly reduces the processing burden on the memory controller/graphics controller (col. 5,
`
`lines 38-46).
`
`l3.
`
`As per Claim 2, Maclnnis does not teaches that the square regions comprise a two
`
`dimensional partitioning of memory. However, Perego teaches square regions have two
`
`dimensional partitioning of memory (col. 5, lines 19-33). This would be obvious for the reasons
`
`given in the rejection for Claim l.
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`14.
`
`As per Claim 3, Maclnnis teaches wherein the memory is a frame buffer (col. 6, line 66-
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`col. 7, line 2).
`
`15.
`
`As per Claim 4, Maclnnis does not teach that each of the at least two graphics pipelines
`
`further includes front end circuitry operative to receive vertex data and generate pixel data
`
`corresponding to a primitive to be rendered, and back end circuitry, coupled to the front end
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`

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`Application/Control Number: 10/459,797
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`Page 9
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`Art Unit: 2628
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`circuitry, operative to receive and process a portion of the pixel data. However, Perego teaches
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`each of at least 2 graphics pipelines includes front end circuitry (308, Fig. 3) operative to
`
`generate pixel data corresponding to primitive to be rendered, and back end circuitry (3 12),
`
`coupled to front end circuitry, operative to receive and process portion of pixel data (col. 3, line
`
`64-col. 4, line 2; col. 5, lines l9-44). In order for front end circuitry (308) to generate pixel data,
`
`it must receive vertex data. Perego teaches that the CPU sorts the primitive data according to the
`
`spatial region of the rendering surface (e.g., the x and y coordinates) covered by that primitive,
`
`and the rendering surface is divided into multiple rectangular regions of pixels (col. 5, lines l9-
`
`27). One of ordinary skill in the art would understand that data pertaining to the x and y
`
`coordinates covered by the primitive would include vertex data. The main memory is used to
`
`store data which are referenced during the execution of the programs (col. l, lines l8-2l).
`
`Therefore, the CPU is operative to receive vertex data (data pertaining to the x and y coordinates
`
`covered by the primitive) from the main memory and generate pixel data corresponding to a
`
`primitive to be rendered (col. 5, lines 19-27; col. 1, lines 18-21). Perego teaches that rendering
`
`engine 3 12 is coupled to the CPU, and is operative to receive and process a rectangular region of
`
`pixel data (col. 3, line 64-col. 4, line 2; col. 5, lines 19-44). Since the CPU is coupled to the
`
`rendering engine 3 l2, and the CPU and the rendering engine 3 l2 both perform graphics
`
`processing, and, the CPU performs the operations of the front end circuitry, and the rendering
`
`engine 3 l2 performs the operations of the back end circuitry, the CPU and the rendering engine
`
`3 l2 are considered to be part of a graphics pipeline, and the CPU is considered to be the front
`
`end circuitry included in the graphics pipeline. This would be obvious for the reasons given in
`
`the rejection for Claim l.
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`

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`Page 10
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`Art Unit: 2628
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`16.
`
`As per Claim 7, Maclnnis does not teach that the at least two graphics pipelines
`
`separately receive the pixel data from the front end circuitry. However, Perego teaches at least
`
`two graphics pipelines (312) separately receive pixel data from front end circuitry (308) (col. 3,
`
`line 64-col. 4, line 2; col. 5, lines 19-44). This would be obvious for the reasons given in the
`
`rejection for Claim 1.
`
`17.
`
`As per Claim 10, Maclnnis does not teach that a first of the at least two graphics pipelines
`
`processes the pixel data only in the first set of tiles in the repeating tile pattern. However, Perego
`
`teaches first of at least two graphics pipelines (first rendering engine of 3 12, Fig. 3) processes
`
`pixel data only in first set of tiles (tiles labeled “REO” in Fig. 5) in repeating tile pattern (col. 5,
`
`lines 23-44). This would be obvious for the reasons given in the rejection for Claim 1.
`
`18.
`
`As per Claim 12, Maclnnis does not teach that a second of the at least two graphics
`
`pipelines processes the data only in a second set of tiles in the repeating tile pattern. However,
`
`Perego teaches second of at least two graphics pipelines (second rendering engine of 312, Fig. 3)
`
`processes pixel data only in second set of tiles (tiles labeled “RE1” in Fig. 5) in repeating tile
`
`pattern (col. 5, lines 23-44). This would be obvious for the reasons given in the rejection for
`
`Claim 1.
`
`19.
`
`As per Claim 14, Claim 14 is similar to Claims 4 and 10, except that Claim 14 is for a
`
`third and fourth graphics pipeline. Perego teaches four graphics pipelines (col. 5, lines 41-44).
`
`So Claim 14 is rejected under the same rationale as Claims 4 and 10.
`
`20.
`
`As per Claim 25, Claim 25 is similar in scope to Claim 1, and therefore is rejected under
`
`the same rationale.
`
`

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`Page 11
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`Art Unit: 2628
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`21.
`
`Claims 5, l8, and 24 are rejected under 35 U.S.C. l03(a) as being unpatentable over
`
`Maclnnis (US006570579Bl) in view of Perego (US006864896B2), further in view of Kelleher
`
`(US0057940 1 6A).
`
`22.
`
`As per Claim 5, Maclnnis and Perego are relied on for teachings for Claim 4.
`
`But, Maclnnis and Perego do not explicitly teach at each of 2 graphics pipelines includes
`
`scan converter, coupled to back end circuitry, operative to determine portion of pixel data to be
`
`processed by back end circuitry. But, Kelleher teaches each of at least 2 graphics pipelines (20A,
`
`20B, Fig. 3; col. 3, lines 22-23; col. 4, lines 9-l4) includes scan converter (update stage, Fig. 7),
`
`coupled to back end circuitry, operative to determine portion of pixel data to be processed by
`
`back end circuitry (col. 8, lines 52-61; col. 9, lines l-23; col. 6, lines 26-28).
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify Maclnnis and Perego so at each of at least two graphics pipelines includes a
`
`scan converter, coupled to the back end circuitry, operative to determine the portion of the pixel
`
`data to be processed by the back end circuitry because Kelleher suggests scan converters are
`
`needed in order to define image data as array of pixels by calculating pixel addresses (col. 9,
`
`lines l-23), as is well-known in the art.
`
`23.
`
`As per Claim l8, Maclnnis does not teach a bridge operable to transmit vertex data to
`
`each of the ls‘, 2nd, 3rd and 4th graphics pipelines. But, Kelleher teaches a bridge (38, Fig. 3)
`
`operative to transmit vertex data to each of the lst (20A), 2nd (20B), 3rd (20C) and 4th (20N)
`
`graphics pipelines (col. 3, lines 22-23; col. 4, lines 9-l4; col. 8, lines 56-65; col. 3, lines 46-50).
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify Maclnnis to include a bridge operable to transmit vertex data to each of the
`
`

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`Page 12
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`Art Unit: 2628
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`first, second, third and fourth graphics pipelines because Kelleher suggests being able to convert
`
`the vertex data to pixel data in parallel, which increases the efficiency of the graphics system
`
`(col. 2, lines 31-35; col. 8, lines 56-65; col. 9, lines 1-23).
`
`24.
`
`As per Claim 24, Maclnnis teaches a graphics processing circuit, comprising: front end
`
`circuitry (90, Fig. 4) operative to generate pixel data in response to primitive data for a primitive
`
`to be rendered (col. 8, lines 49-59); back end circuitry (98), coupled to the front end circuitry
`
`(90) (col. 9, lines 15-34), operative to process the pixel data in response to position coordinates
`
`(col. 9, lines 35-54). The front end circuitry (90) and the back end circuitry (98) are in the
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`graphics display pipeline (80) (col. 7, lines 55-63), and the graphics display pipeline (80) is
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`equivalent to display engine (58, Fig. 2), which is on graphics chip (l0) (col. 4, lines 65-67; col.
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`5, lines 36-39). A memory controller (54) is also on graphics chip (l0) (col. 4, lines 65-67; col.
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`5, lines 36-3 9). Therefore, the front end circuitry (90), the back end circuitry (98), and the
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`memory controller (54) are on the chip (l0). The memory controller (54) is coupled to the
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`display engine (58) and is operative to transmit and receive the processed pixel data (col. 6, lines
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`10-13, 59-67; col. 7, lines l-2). Since the display engine (5 8) is equivalent to the graphics
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`display pipeline (80) which contains the back end circuitry (98) (col. 6, lines 59-67; col. 7, lines
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`55-63), the memory controller (54) is coupled to the back end circuitry (98) and is operative to
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`transmit and receive the processed pixel data.
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`However, Maclnnis does not teach first back end circuitry operative to process a first
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`portion of the pixel data; set of tiles of a repeating tile pattern are to be processed by the first
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`back end circuitry, the repeating tile pattern including a horizontally and vertically repeating
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`pattern of square regions; second back end circuitry operative to process a second portion of the
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`pixel data; set of tiles of the repeating tile pattern are to be processed by the second back end
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`circuitry. However, Perego teaches graphics processing circuit (300, Fig. 3; col. 3, lines 61-63),
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`having front end circuitry (308) operative to generate pixel data in response to primitive data for
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`primitive to be rendered (col. 5, lines. 19-23); 15‘ back end circuitry (lst rendering engine 312),
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`coupled to front end circuitry 308, operative to process 15‘ portion of pixel data (labeled “REO” in
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`Fig. 5) in response to position coordinates; set of tiles of repeating tile pattern are to be processed
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`by 15‘ back end circuitry, repeating tile pattern including horizontally and vertically repeating
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`pattern of square regions, as shown in Fig. 5; 2nd back end circuitry (second rendering engine
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`312), coupled to front end circuitry 308, operative to process 2nd portion of pixel data (labeled
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`“REl” in Fig. 5) in response to position coordinates; set of tiles of repeating tile pattern are to be
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`processed by 2nd back end circuitry (col. 3, line 63-col. 4, line 2; col. 5, lines 19-44); and
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`memory controller (310), coupled to 15‘ and 2nd back end circuitry (312) operative to transmit and
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`receive processed pixel data (col. 3, lines 65-67; col. 4, lines 1-53; col. 5, lines 32-44). Perego
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`describes “Improvements in integrated circuit design and manufacturing technologies allow
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`higher levels of integration, thereby allowing an increasing number of subsystems to be
`
`integrated into a single device. This increased integration reduces the total number of
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`components in a system, such as a computer system. As subsystems with high memory
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`performance requirements (such as graphics subsystems) are combined with the traditional main
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`memory controller, the resulting architecture may provide a single high-perforrnance main
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`memory interface” (col. 1, lines 34-43). Perego shows in Fig. 8 that in one embodiment, a
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`memory module 800 contains two different rendering engines 802 and 810 (Fig. 8; col. 6, lines
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`61-62), and therefore at least two graphics pipelines (802, 810) are on a same memory module
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`800. From Fig. 8 and from the description in Perego, one of ordinary skill in the art would
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`understand that a memory module is equivalent to a chip. Therefore, Perego teaches that two
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`graphics pipelines are on the same chip, and so the front end circuitry, first back end circuitry,
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`and second back end circuitry are on the same chip. This would be obvious for the reasons given
`
`in the rejection for Claim 1.
`
`However, Maclnnis and Perego do not explicitly teach first scan converter and second
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`scan converter. However, Kelleher teaches first scan converter, coupled between front end
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`circuitry (14, Fig. 3) and first back end circuitry (update stage, Fig. 7 in 20A, Fig. 3), operative to
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`determine which set of tiles of repeating tile pattern are to be processed by first back end
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`circuitry (col. 3, lines 22-23; col. 8, line 33-col. 9, line 23), and operative to provide position
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`coordinates to first back end circuitry in response to pixel data (col. 4, lines 60-62; col. 8, lines
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`52-65; col. 6, lines 36-38); second scan converter, coupled between front end circuitry and
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`second back end circuitry (update stage, Fig. 7 in 20B, Fig. 3), operative to determine which set
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`of tiles of repeating tile pattern are to be processed by second back end circuitry, and operative to
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`provide position coordinates to second back end circuitry in response to pixel data (col. 3, lines
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`22-23; col. 8, line 33-col. 9, line 23; col. 4, lines 60-62; col. 8, lines 52-65; col. 6, lines 36-38).
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`Therefore, by implement this teaching into the device of Perego, front end circuitry, first back
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`end circuitry, and first scan converter of Perego-Kelleher combination make up one graphics
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`pipeline, and front end circuitry, second back end circuitry, and second scan converter of Perego-
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`Kelleher combination make up another graphics pipeline. Since Perego teaches graphics
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`pipelines are on the same chip, the teaching from Kelleher can be applied to Perego so that the
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`first scan converter and the second scan converter are also on the same chip. This would be
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`obvious for reasons given in the rejection for Claim 5.
`
`25.
`
`Claims 6 and 17 are rejected under 35 U.S.C. l03(a) as being unpatentable over Maclnnis
`
`(US006570579Bl) in View of Perego (US006864896B2), further in View of Furtner
`
`(US006778l77Bl).
`
`26.
`
`As per Claim 6, Maclnnis and Perego are relied upon for the teachings as discussed
`
`above relative to Claim 1.
`
`However, Maclnnis and Perego do not expressly teach that each tile of the set of tiles
`
`further comprises a l6xl6 pixel array. However, Furtner teaches that each tile of the set of tiles
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`further comprises a l6xl6 pixel array (col. ll, lines 45-48, 64-65).
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify Maclnnis and Perego so each tile of set of tiles further has l6xl6 pixel array
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`because Furtner suggests depending on number of parallel image-rendering pipelines and
`
`depending on memory organization, optimum tile size and shape can be selected (col. ll, lines
`
`45-48, 64-65), and so it would be obvious to modify tile size to be l6xl6 pixels if that would be
`
`optimum tile size for particular number of parallel image-rendering pipelines and particular
`
`memory organization.
`
`27.
`
`As per Claim l7, Maclnnis does not teach 3rd and 4th graphics pipelines are on separate
`
`chips. However, Furtner teaches this limitation (col. 6, lines 47-5 1).
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
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`applicant to modify Maclnnis so pipelines are on separate chips because Furtner teaches this
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`makes system more configurable by being able to easily add more graphics pipelines to increase
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`performance (col. 6, lines 29-30, 42-51).
`
`28.
`
`Claims 11, 13, 15, and 16 are rejected under 35 U.S.C. l03(a) as being unpatentable over
`
`Maclnnis (US006570579Bl) in view of Perego (US006864896B2), further in view of Kelleher
`
`(US0057940l6A), further in view of Hamburg (US005905506A).
`
`Maclnnis and Perego are relied upon for teachings relative to Claim 10.
`
`However, Maclnnis and Perego do not explicitly teach scan converter. However,
`
`Kelleher teaches first of the at least two graphics pipelines (20A, Fig. 3; col. 3, lines 22-23; col.
`
`4, lines 9-14) further includes scan converter (84, Fig. 7), coupled to front end circuitry (80, 82)
`
`and back end circuitry (col. 8, line 52-col. 9, line 23). Scan converter determines which groups of
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`blocks