UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Oflice
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`www.uspto.gov
`
`APPLICATION NO.
`
`.
`
`FILING DATE
`
`FIRST NAMED INVENTOR
`
`_
`
`ATTORNEY DOCKET NO.
`
`CONFIRMATION NO.
`
`I0/459,797
`
`06/I 2/2003
`
`‘ Mark M. Leather
`
`O0|00.02.0053
`
`4148
`
`29153
`7590
`02/04/2008
`ADVANCED MICRO DEVICES, me.
`C/O VEDDER PRICE P.C.
`222 N.LASALLE STREET
`CHICAGO, IL 60601
`
`.
`
`Hsu. Jom
`
`’
`
`PAPER “UMBER
`
`DELIVERY MODE
`
`PAPER
`
`2628
`
`MAIL DATE
`
`02/04/2008
`
`Please find below and/or attached an Of_fice communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`PTOL-90A (Rev. 04/07)
`
`U N I Fl ED 1 01 0
`
`UNIFIED 1010
`
`

`
`Office Action Summary
`
`Application No.
`
`»
`
`Applicant(s)
`
`.10/459,797
`
`Examine,
`
`Joni Hsu
`
`LEATHER ET AL.
`
`M Uni,
`
`2628
`
`‘
`
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE § MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`- Extensions of time may be available under the provisions of 37 CF R 1.136(3).
`In no event. however, may a reply be timely filed
`after SIX (6) MONTHS from the mailing date of this communication.
`If No period for reply is specified above. the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute. cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1)|Z] Responsive to communication(s) filed on 28 November 2007.
`
`2a)E This action is FINAL.
`
`2b)EI This action is non—final.
`
`3)[] Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`
`closed in accordance with the practice under Ex parte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`Disposition of Claims
`
`4)lX| Claim(s) 1-7 10-22 24 and 25 is/are pending in the application.
`4a) Of the above claim(s) '_ is/are withdrawn from consideration.
`
`5)[:I Claim(s) _ is/are allowed.
`
`em Claim(s) 1-7 10-22 24 and 25 is/are rejected.
`
`7)I:] Claim(s) _____ is/are objected to.
`
`8)E] Claim(s) __ are subject to restriction and/or election requirement.
`
`Application Papers
`
`A
`9)|:I The specification is objected to by the Examiner.
`10)l:I The drawing(s) filed on :_ is/are: a)[:] accepted or b)I:I objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
`
`11)[:l The oath or declaration is objected to by the Examiner. Note the attached Office ‘Action or form PTO-152.
`
`Priority under 35 U.S.C. § 119
`
`12)l:l Acknowledgment is made of a claim for foreignipriority under 35 U.S.C. § 119(a)-(d) or (f).
`b)I:I Some * c)I:I None of:
`I
`-
`Certified copies of the priority documents have been received.
`
`Certified copies of the priority documents have been received in Application No. __
`
`Copies of the certified copies of the priority documents have been received in this National Stage
`
`application from the International Bureau (PCT Rule 17.2(a)).
`
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1) E Notice of References Cited (PTO-892)
`2) D Notice of Draflsperson's Patent Drawing Review (PTO-948)
`3) El lnfonnation Disclosure Statement(s) (PTO/SB/08)
`Paper No(s)/Mail Date 11/28/07.
`U.S. Patent and Trademark Office
`
`4) D Interview Summary (PTO-413)
`Paper N0(S)/M3iI 9316- __
`5) CI Notice of Informal Patent Appliéation
`6) D Other:
`.
`
`.
`
`PTOL-326 (Rev. 08-06)
`
`Office Action Summary
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`Part of Paper No_/Ma" page 112897
`
`

`
`it /-—
`
`Application/Control Number:
`1 0/459,797
`Art Unit: 2628
`
`4
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`Page 2
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`DETAILED ACTION
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`1 Information Disclosure Statement
`
`1.
`
`Information disclosure statement (IDS) submitted on November 28, 2007 was filed after
`
`mailing date of application on June 12, 2003. Submission is in compliance with.provisions of 37
`CFR 1.97. Accordingly, information disclosure statement is being considered by the examiner.
`
`Response to Arguments
`
`2.
`Applicant’s arguments, see pages 9-11, filed November 28, 2007, with respect to the
`rejection(s) ofclaim(s) 11-4, 7, 10, 12, 14, 20-22, and 25 under 35 U.S.C. lO2(e). and claims 5, 6,
`
`11, 13, 15-19, and 24 under 35 U.S.C. 103(a) have been fully considered and are persuasive. So,
`
`the rejection has been withdrawn. However, upon further consideration, a new ground(s) of
`
`rejection is made in view of Furtner (US006778l77Bl) and Maclnnis (US006570579B1).
`
`3.
`
`’ Applicant argues Perego (US006864896B2) does not teach multi-graphics pipeline
`
`circuitry on same chip nor memory controller on the same chip but instead teaches discrete
`memory modules having separate and single graphics engines thereon. The memory controller
`
`taught in Perego is not on a same chip nor is it part of the memory module (page 10).
`
`' In reply, new grounds of rejection are made in view of Furtner and Maclnnis.
`
`Claim Rejections - 35 USC § 103
`
`' 4.
`
`»
`
`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
`
`obviousness rejections set forth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in
`section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are
`such that the subject matter as a whole would have been obvious at the time the invention was made to a person
`having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the
`manner in which the invention was made.
`
`

`
`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page 3
`'
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`V The factual inquiries set forth in Graham v. John Deere C0., 383 U.S. 1, 148 USPQ 459
`
`(1966), that are applied for establishing a background for determining obviousness under 35
`
`U.S.C. 103(a) are summarized as follows:
`
`:“P’!\’:“
`
`Determining the scope and contents of the prior art.
`Ascertaining the differences between the prior art and the claims- at issue.
`Resolving the level of ordinary skill in the pertinent art.
`Considering objective evidence present in the application indicating obviousness -
`or nonobviousness.
`
`5.
`
`Claims 1-4, 6, 7, 10, 12, 14, and 17 are rejected under 35 U.S.C. 103(a) as being
`
`unpatentable over Perego (USO06864896B2) in view of Furtner (US006778 1 77B 1), further in
`View of Maclnnis (US00657O579Bl).
`.
`
`6.
`
`As per Claim 1, Perego teaches graphics processing circuit (300, Fig. 3; c. 3, 11. 61-63),
`
`having at least 2 graphics pipelines (312) operative to process data in corresponding set of tiles
`
`of repeating tile pattern corresponding to screen locations, respective one of at least two graphics
`
`pipelines operative to process data in dedicated tile (c. 5, 11. 19-27, 38-44); and memory
`
`controller (310, Fig. 3) in communication with at least 2 graphics pipelines (312), operative to
`
`transfer pixel data between each of 15‘ pipeline and 2”’ pipeline and shared memories (314) (c. 3,
`
`11. 65-67; c. 4, 11. 1-10, 48-65). Shared memories (314) are each part of main memory (c. 1, ll. 44-
`54; c. 3, 11. 3-6), and so are considered to be one memory. Repeating tile pattern includes
`
`horizontally and vertically repeating pattern of regions of square regions, as shown in Fig. 5 (c.
`
`5, 11. 19-27, 38-44).
`
`However, Perego does not teach that the graphics pipelines are on a same chip. However,
`
`Furtner teaches that the graphics pipelines are on a same chip (c. 6, ll. 30-32).
`
`

`
`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page 4
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`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify device of Perego so graphics pipelines are on same chip as suggested by
`
`Furtner. Placing plurality of modules on single chip takes up less space as compared to using
`
`multiple chips, and this is well-known in the art.
`
`However, Perego and Furtner do not teach memory controller is also on the same chip.
`
`However, Maclnnis teaches memory controller (54) is on same chip (10) as graphics pipeline
`
`(58), as shown in Fig. 2 (c. 4,11. 65-67; c. 5, 11. 36-41; c. 6, 11. 10-13). This would be obvious for
`
`same reasons given above.
`
`7.
`
`As per Claim 2, Perego teaches square regions have two dimensional partitioning of
`
`memory (c. 5,11. 19-33).
`
`8.
`
`9.
`
`As per Claim 3, Perego discloses that the memory is a frame buffer (c. 5, 11. 32-33).
`
`As per Claim 4, Perego teaches each of at least two graphics pipelines includes front end
`
`circuitry (308, Fig. 3) operative to generate pixel data corresponding to primitive to be rendered,
`
`and back end circuitry (312), coupled to front end circuitry, operative to receive and process
`
`portion of pixel data (c. 3, 11. 64-0. 4, ll. 2; c. 5, 11. 19-44). In order for front end circuitry (308) to
`
`generate pixel data, it must inherently receive vertex data.
`
`10.
`
`As per Claim 6, Perego does not explicitly teach each tile of set of tiles has 16x16 pixel
`
`array. But, Furtner teaches each tile of set of tiles has 16x16 pixel array (c. 11, 11. 45-48, 64-65).
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify Perego so each tile of set of tiles further has 16x16 pixel array because
`
`Furtner suggests depending on number of parallel image-rendering pipelines and depending on
`
`memory organization, optimum tile size and shape can be selected (c. 11, 11. 45-48, 64-65), and
`
`

`
`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page'5
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`so it would be obvious to modify tile size to be 16x16 pixels if that would be optimum tile size
`
`for particular number of parallel image-rendering pipelines and particular memory organization.
`
`11.
`
`. As per Claim 7, Perego teaches the at least two graphics pipelines (312, Fig. 3) separately
`
`receive the pixel data from the front end circuitry (308) (c. 3, ll. 64-c. 4, ll. 2; c. 5, 11. 19-44).
`
`12.
`As per Claim 10, Perego teaches first of at least two graphics pipelines (first rendering
`engine of 312, Fig. 3) processes pixel data only infirst set oftiles (tiles labeled f‘REO” in Fig. 5)
`
`in repeating tile pattern (c. 5, 11. 23-44).
`
`13.
`
`As per Claim 12, Perego teaches second of at least two graphics pipelines (second A
`
`rendering engine of 312, Fig. 3) processes pixel data only in second set of tiles (tiles labeled
`
`‘.‘RE1"’ in Fig. 5) in repeating tile pattern (c. 5, 11. 23-44).
`
`14.
`
`1 As per Claim 14, Claim 14 is similar to Claims 4 and 10, except that Claim 14 is for a
`
`third and fourth graphics pipeline. Perego teaches four graphics pipelines (c. 5, 11. 41-44). So
`
`Claim 14 is rejected under the same rationale as Claims 4 and 10.
`
`15.
`
`As per Claim 17, Perego does not teach 3” and 4”‘ graphics pipelines are on separate
`
`chips. However, Furtner teaches 3'“ and 4"‘ pipelines are on separate chips (c. 6, 11. 47-51).
`
`It would have been obvious to one of ordinary skill in the art at the time of‘invention by
`
`applicant to modify Perego so pipelines are on separate chips because Furtner teaches this makes
`
`system more configurable by being able to easily add more graphics pipelines to increase
`
`performance (c. 6, 11. 29-30, 42-51).
`16.
`Claims 5, 18, and 24 are rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`Perego (USO06864896B2), Furtner (USO06778177B1), and Maclnnis (USOO6570579B1) in View
`
`of Kelleher (US0057940l6A).
`
`

`
`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page 6
`-
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`17.
`
`As per Claim 5, Perego, Furtner, and Maclnnis are relied upon for teachings for Claim 4.
`
`But, Perego, Furtner, and Maclnnis do not explicitly teach at each of at least two graphics
`
`pipelines further includes scan converter, coupled to back end circuitry, operative to determine
`
`portion of pixel data to be processed by back end circuitry.’ But, Kelleher teaches each of at least
`
`two graphics pipelines (20A, 20B, Fig. 3; c. 3, 11. 22-23; c. 4, 11. 9-14) further includes scan
`
`converter (update stage, Fig. 7), coupled to back end circuitry, operative to determine portion of
`
`pixel data to be processed by back end circuitry (c. 8, 11. 52-61; c. 9, 11. 1-23; c. _6, 11. 26-28).
`
`. It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify devices of Perego, Furtner, and Maclnnis so at each of at least two graphics
`
`pipelines further includes a scan converter, coupled to the back end circuitry, operative to
`
`' determine the portion of the pixel data to be processed by the back end circuitry because
`
`Kelleher suggests scan converters are needed in order to define image data as array of pixels by
`
`calculating pixel addresses (c. 9, 11. 1-23), as is well-known in the art.
`
`18.
`
`As per Claim 18, Perego does not teach a bridge operable to transmit vertex data to each
`
`of the first, second, third and fourth graphics pipelines. However, Kelleher discloses a bridge
`
`(38, Fig. 3) operative to transmit vertex data to‘ each of the first (2OA), second (2OB), third (20C) 1
`
`and fourth (2ON) graphics pipelines (c. 3, 11. 22-23; c. 4, 11. 9-14; c. 8, 11. 56-65; c. 3, 11. 46-50).
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify Perego to include a bridge operable to transmit vertex data to each of the
`first, second, third and fourth graphics pipelines as suggested by Kelleher because Kelleher
`
`suggests the advantage of being able to convert the vertex data to pixel data in parallel, which
`
`increases the efficiency of the graphics system (c. 2, 11. 31-35; c. 8, 11. 56-65; c. 9, 11. 1-23).
`
`

`
`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page 7
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`19.
`
`As per Claim 24, Perego teaches graphics processing circuit (300, Fig. 3; c. 3, 11. 61-63),
`
`having front end circuitry (308) operative to generate pixel data in response to primitive data for
`primitive to be rendered (c. 5, 11. 19-23); first back end circuitry (first rendering engine 312),
`
`coupled to front end circuitry 308, operative to process first portion of pixel data (labeled “REO”
`
`in Fig. 5) in response to position coordinates; set of tiles of repeating tile pattern are to be
`
`processed by first back end circuitry, repeating tile pattern including horizontally and vertically
`
`repeating pattern of square regions, as shown in Fig. 5; second back end circuitry (second
`
`rendering engine 312), coupled to front end circuitry 308, operative to process second portion of
`
`pixel data (labeled “RE1” in Fig. 5) in response to position coordinates; set" of tiles of repeating
`
`tile pattern are to be processed by second back end circuitry (c. 3, ll. 63-c. 4, ll. 2; c. 5, 11. 19-44);
`
`and memory controller (310), coupled to first and second back end circuitry (312) operative to
`
`transmit and receive processed pixel data (c. 3, 11. 65-67; c. 4, 11. 1-53; c. 5, 11. 32-44).
`
`However, Perego does not explicitly teach first scan converter and second scan converter.
`
`However, Kelleher teaches first scan converter, coupled between front end circuitry (14, Fig. 3)
`and first back end circuitry (update stage, Fig. 7 in 20A, Fig. 3), operative to determine which set
`
`oftiles of repeating tile pattern are to be processed by first back end, circuitry (cl. 3, 11. 22-23; c. 8,
`
`11. 33-c. 9, 11. 23), and operative to provide position coordinates to first back end circuitry in
`
`response to pixel data (c. 4, 11. 60-62; c. 8, 11. 52-65; c. 6, 11. 36-38); second scan converter,
`
`coupled between front end circuitry and second back end circuitry (update stage, Fig. 7 in 20B,
`
`Fig. 3), operative to determine which set oftiles of repeating tile pattern are to be processed by
`
`second back end circuitry, and operative to provide position coordinates to second back end
`
`

`
`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page 8
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`'
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`circuitry in response to pixel data (c. 3, 11. 22-23; c. 8, ll. 33-c. 9, 11. 23; c. 4, 11. 60-62; c. 8, ll. 52-
`
`65; c. 6, 11. 36-38). This would be obvious for same reasons given in the rejection for Claim 5.
`
`However, Perego and Kelleher do not teach front end circuitry, first back end circuitry,
`
`first scan converter, second back end circuitry, and second scan converter are all on same chip.
`However, Furtner teachesigraphics pipelines are on same chip (c. 6, 11. 30-32). Front end
`
`circuitry, first back end circuitry, and first scan converter of Perego-Kelleher combination make
`
`up one graphics pipeline, and front end circuitry, second back end circuitry, and second scan
`
`converter of Perego-Kelleher combination make up another graphics pipeline, as discussed
`
`above. Since Furtner teaches graphics pipelines are on same chip, this teaching from Furtner can
`
`be applied to Perego-Kelleher combination so front end circuitry, first back end circuitry, first
`
`scan converter, second back end circuitry, and second scan converter are all on same chip. This
`
`would be obvious for reasons for Claim 1.
`
`However, Perego, Kelleher, and Furtner do not teach memory controller is also on the
`
`same chip. However, Maclnnis teaches this limitation, as discussed in the rejection for Claim 1.
`
`20.
`Claims 11, 13, 15, and 16 are rejected under 35 U.S.C. l03(a) as being unpatentable over
`Perego (USOO6864896B2), Furtner (US006778l77B1), and Maclnnis (USOO6570579Bl) in view
`
`of Kelleher (US005794016A), further in view of Hamburg (US0O5905506A).
`
`Perego, Furtner, and Maclnnis are relied upon for teachings relative to Claim 10.
`
`However, Perego, Furtner, and Maclnnis do not explicitly teach scan converter.
`
`However, Kelleher teaches first of the at least two graphics pipelines\(20A, Fig.‘ 3; c. 3, 11. 22-23;
`
`c. 4, 11. 9-14) further includes scan converter (84, Fig. 7), coupled to front end circuitry (80, 82)
`
`and back end circuitry (c. 8, ll. 52-c. 9, ll. 23). Scan converter determines which groups of blocks
`
`

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`Application/Control Number:
`10/459,797
`Art Unit: 2628
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`Page 9
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`52 within graphics memory 22 are allocated to and controlled by graphics pipelines (c. 8, ll. 52-
`
`65; c. 6, 11. 26-28). Graphics memory is partitioned into plurality ofpixel blocks that are tiled in
`
`x-and y-direction of graphics memory (c. 4, 11. 60-62). So, scan converter is inherently operative
`
`to provide memory addresses or position coordinates of pixels within first set of tiles to be
`
`processed by back end circuitry. This would be obvious for reasons for Claim 5'.
`
`But, Perego, Furtner, Maclnnis, Kelleher do not explicitly teach using tile identification
`
`data to indicate which tiles are to be processed. But, Hamburg teaches pixel identification line
`
`for receiving tile identification data indicating which tiles are to be processed (c. 5, 11. 35-52).
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify devices of Perego, Furtner, Maclnnis, and Kelleher to include using tile
`
`identification data to indicate which tiles are to be processed because Hamburg suggests
`
`advantage of using tile identification data to easily track storage locations of tile pixel data and
`
`being able to easily retrieve data for particular image tile (c. 1, 11. 46-54).
`
`21.
`
`Claim 19 is rejected under 35 U.S.C. l03(a) as being unpatentable over Perego
`
`(US006864896B2), Furtner (US006778177B1), and Maclnnis (USO06570579B1) in view of
`
`Kent (US 20030164830A1).
`
`' Perego, Furtner, and Maclnnis are relied on for teachings for Claim 17. Perego teaches
`
`data includes polygon (c. 5, 11. 19-23). Furtner teaches third and fourth graphics pipelines are on
`
`separate chips (c. 6, 11. 47-51), as discussed for Claim 17.
`
`But, Perego, Furtner, and Maclnnis do not teach creating bounding box around polygon
`
`and each corner of bounding box is checked against super tile that belongs to each separate chip
`
`and if bounding box does not overlap any of super tiles associated with separate chip, then
`
`

`
`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`-
`
`Page 10
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`processing circuit rejects whole polygon and processes next one. But, Kent teaches graphics
`
`pipeline [0006] calculates bounding box of primitive and testing this against VisRect. If
`
`bounding box of primitive is contained in other Pl0’s super tile the primitive is discarded at this
`
`stage [0129]. Primitive can be polygon [0088]. Method used is to calculate distance from each
`
`subpixel sample point in point’s bounding box to point’s center and compare this to point’s
`
`radius. Subpixel sample points with distance greater than radius do not contribute to pixel’s
`
`coverage. Cost of this is kept low by only allowing small radius points hence distance calculation
`
`is a small multiply and by taking a cycle per subpixel sample per pixel within bounding box
`
`[Ol44]. Since method calculates distance from each subpixel sample point in point’s bounding
`
`box, this must include all comers ofbounding box. So, Kent teaches data includes polygon and
`
`graphics pipeline creates bounding box around polygon and wherein each comer of bounding
`
`box is checkedlagainst super tile that belongs to graphics pipeline and if bounding box does not
`
`overlap any of super tiles, then processing circuit rejects whole polygon and processes next one.
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify Perego, Further, and Maclnnis to include bounding box as because Kent
`
`suggests processing super tiles one at a time in order to hide page break costs [0129, 0051].
`
`22.
`. Claims 20-22 and 25 are rejected under 35 U.S.C. 103(a) as being unpatentable over
`Perego (US006864896B2) in view of Furtner (USO06778177B1).
`A
`
`23.
`
`As per Claim 20, Perego teaches graphics processing method, comprising generating
`
`pixel data (c. 5, 11. 19-25), which is inherently generated in response to received vertex data;
`
`determining pixels within set of tiles of repeating tile pattern corresponding to screen locations to
`
`be processed by corresponding one of at least two graphics pipelines (312, Fig. 3) in response to
`
`

`
`Application/Control Number:
`10/459,797
`Art Unit: 2628
`
`Page 11
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`pixel data, repeating tile pattern including horizontally and vertically repeating pattern of square
`
`regions, as shown in Fig. 5; performing pixel operations on pixels within determined set of tiles
`
`by corresponding one of at least two graphics pipelines (c. 5, 11. 19-44); and transmitting
`
`processed pixels to memory controller (310), wherein at least two graphics pipelines share
`
`memory controller (c. 3, ll. 65-c. 4, ll. 25; c. 5, 11. 31-44).
`
`However, Perego does not teach that the graphics pipelines are on a same chip. However,
`
`Furtner teaches graphics pipelines are on a same chip (c. 6, ll. 30-32), as discussed for Claim 1.
`
`24.
`
`As per Claim 21, Perego teaches determining pixels within set of tiles of repeating tile
`
`pattern to be processed further comprises determining set of tiles that corresponding graphics
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`pipeline is responsible for (c. 5, 11. 19-50).
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`25.
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`As per Claim 22, Perego teaches determining pixels within set of tiles of repeating tile
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`pattern to be processed comprises providing position coordinates of pixels within determined set
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`of tiles to be processed to corresponding one of at least two graphics pipelines (c. 5, ll. 19-44).
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`26.
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`H As per Claim 25, Perego teaches graphics processing circuit (300, Fig. 3; c. 3, 11. 61-63)
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`having at least two graphics pipelines (312) operative to process data in corresponding set of tiles
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`of repeating tile pattern corresponding to screen locations, respective one of at least two graphics
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`pipelines operative to process data in a dedicated tile (c. 5, 11. 19-27, 38-44), wherein the
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`repeating tile pattern includes a horizontally and vertically repeating pattern of regions of square
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`regions, as shown in Fig. 5 (c. 5, 11. 19-27, 38-44).
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`However, Perego does not teach‘ that the graphics pipelines are on a same chip. However,
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`Furtner teaches graphics pipelines are on a same chip (c. 6, 11. 30-32), as discussed for Claim 1.
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`

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`Application/Control Number:
`10/459,797
`_Art Unit: 2628
`
`Page 12
`'
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`Conclusion
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`Applicant's amendment necessitated the new ground(s) of rejection presented in this
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`Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP §.706.07(a).
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`Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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`A shortened statutory period for reply to final action is set to expire THREE MONTHS
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`'
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`from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of
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`the mailing date of this final action and the advisory action is not mailed until after the end of the
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`THRE.E-MONTH shortened statutory period, then the shortened statutory period will expire on
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`the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be
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`calculated from the mailing date of the advisory action. In no event, however, will the statutory
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`period for reply expire later than SIX MONTHS from the date of this final action.
`5 Any inquiry concerning this communication or earlier communications from the
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`examiner should be directed to Joni Hsu whose telephone number is 571-272-7785. The
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`examiner can normally be reached on M-F ’8arn-5pm.
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`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
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`supervisor, Kee Tung can be reached on 571-272-7794. The fax phone number for the
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`organization where this application or proceeding is assigned is 571-273-8300.
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`

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`\\
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`‘
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`Application/Control Number:
`10/459,797
`Art Unit: 2628
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`Page 13
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`JH
`
`KEE M.Tl_JNG
`SUPERVESORY PATENT EXAMINER