F'(t‘v‘4'3?.‘R“.lR
`
`integrated 2D/3D graphics accelerator — Product Overview
`
`PF\’ELllVllNARY DATA
`
`FEATURES
`
`I PowerVRTM Series 3 arcade
`
`performance 3D
`0 DirectX7 Flexible Vertex Format support
`I 8 layer Multi—texturing
`0 Twin high performance texturing
`pipelines
`0 Full triangle setup (hidden surface
`removal, shading and texturing)
`0 RGB gouraud shading and specular
`highlights
`0 Bilinear, trilinear and anisotropic texture
`filtering
`0 Color key and Alpha blended textures
`I Table and vertex fog
`0 Texture compression
`0 Full scene anti—a|iasing
`I 128-bit GUI accelerator
`
`O 3 operand ROPs
`0 Hardware clipping
`0 Color expansion
`0 Transparent and stretch BitBLT
`I AGP 2.0 bus master
`
`0 DMA bus mastering for minimum CPU
`load
`I AGP 1x, 2x and 4x with SBA for host
`based textures
`0 3.3V PCl support
`
`I Digital Video Output
`0 12~bit Multiplexed digital interface
`I Glueless connection to standard LCD
`interface devices and digital TV encoders
`0 24-bit LCD modes up to1280x1024 60Hz
`
`I Video playback & MPEG2 decode
`acceleration
`
`0 Motion compensation
`O 422:0 Overlay support
`0 Sub picture blending
`O X, Y interpolated scaling
`0 Color Keying
`I SGRAM/SDRAM 128-bit interface
`
`0 Single memory for frame buffer, video
`and texture memory
`0 2.0 GB/s bandwidth
`0 16 to 64 MBytes support
`
`I Video port
`0 Video port for video capture, TV Tuner,
`videoconferencing
`O VBl data capture for lntercast, Closed
`Caption and Teletext
`
`I integrated 270MHz palette DAC and
`clock synthesizer
`0 32x32 hardware cursor
`O 1920x1280 true color at 75Hz refresh
`
`I PC’99 compliant
`
`DESCRIPTION
`
`KYRO is an integrated 2D/3D accelerator which
`extends the leadership of the PowerVRTM family
`of chips. it is designed to provide the highest
`Direct3D performance along with excellent 2D
`performance and video playback and decode
`acceleration.
`
`KYRO integrates a 3D engine, 2D engine,
`24-bpp palette RAMDAC, clock generators, a
`video input bus and digital interface into a
`400~pin PBGA package.
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`This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
`
`UNIFIED 1006
`
`UNIFIED 1006
`
`

`
`PRELIMINARY DATA
`
`KYRO
`
`SUPPORT
`
`I
`
`ORDERING INFORMATION
`
`To order sample trays or production quantities
`please contact your local ST Sales office.
`3 I
`a °s“”°°
`STG4000A1SITR
`Tape and Reels
`
`STG4000A1S
`
`Trays
`
`I BIOS Support
`. Fuuy ‘BM VGA Compatible BIOS
`O VBE V3.0 support
`0 DPMS and DDC2Bi
`0 OEM Configuration
`
`' U“"t'eS
`0 Manufacturing test software
`0 Smart Tools
`0 Install
`
`LOCALIZATION
`
`0 English
`0 French
`
`0 Italian
`
`0 Traditional
`Chinese
`
`0 Japanese
`0 German
`
`0 Spanish
`
`0 Simplified
`Chinese
`
`0 Korean
`
`3 0 Brazilian
`
`SOFTWARE DRIVER SUPPORT
`
`Win 95/
`DX7
`
`Win2000l
`DX7
`
`DOS
`
`Y
`
`.
`
`Y
`
`Y
`
`Y
`
`Y
`
`Y
`
`Y
`
`
`
`Direct3D HAL
`
`OpenGL ICD
`
`Video Capture /WDM
`
`Y
`
`Y
`
`Display Driver
`
`Y
`
`DirectDraw HAL (inc. VPE)
`
`Y (no VPE)
`
`DVD Playback Support
`
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`

`
`PRELIMINARY DATA
`
`KYRO
`
`1
`
`Functional Description
`
`1.1 General
`
`KYRO is a single chip multimedia display device which integrates 2D and 3D accelerators
`with separate palette DAC and clock synthesizers for graphics output and includes a digital
`interface for connection to a TV Encoder or LCD interface device.
`
`The KYRO includes glueless interfaces to AGP, SDRAM/SGRAM and video port.
`
`
`
`PowerVR
`
`Series 3
`
`3D Engine.
`
`
`
` Texturing
`RGB Monitor
`Pipeline
`
`Graphics
`
`CRTC &
`
`RAMDAC
` Flat Panel
`
`or
`PAL/NTSC
`Encoder
`
`Video Part
`..
`
`
` Video In
`
`BIOSI
`Host Port
`
`
`
` 1X/2Xl4X AGP Interface
`
`'_Connector«
`
`
`
`[if r
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`
`PRELIMINARY DATA
`
`KYRO
`
`1.2 Host Interface
`
`The KYRO host interface is a glueless AGP v2.0 interface which acts as a bus master for 2D
`and 3D parameters as well as host based textures and video capture.
`
`The AGP interface supports Memory Read, Memory Write, |ORead, |OWrite, Memory Read
`Line and Memory Read Multiple PCI commands.
`
`The AGP interface is a full 1x, 2x and 4x with side band addressing implementation
`supporting a peak bandwidth of 1GB/s. The read queue buffer supports 32 outstanding
`requests,
`
`PCI power management device states of D0, D1, D2, D3HOT and D300“) are supported
`allowing ACPl compliant system design.
`
`Sub System Device and Vendor IDs are also supported in the PCI configuration space.
`
`1.3 Memory interface
`
`KYRO is designed with a 128-bit SDRAM / SGRAM memory interface with a peak bandwidth
`of 2.0GB/s. On-chip caches and memory controller ensures that bandwidth is shared
`efficiently between the 2D, 3D and display functions.
`
`The following memory configurations are supported:
`Memory Type
`Ijmber of devices
`
`16 Mbit SDRAM (x16)
`
`_
`
`
`
`8_ 48 8
`
`64 Mbit SDRAM (x32)
`
`64 Mbit SDRAM (X16)
`
`1.4
`
`2D Graphics Engine
`
`KYRO incorporates a powerful 2D graphics accelerator which accelerates all three operand
`ROP BitBLTs and Transparent BLTs. The engine has been optimized to ensure there is no
`penalty for operating in 24bpp packed pixel modes. Other 2D operations supported in
`hardware include clipping, mono to color expansion, points and lines.
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`PRELIMINARY DATA
`
`KYRO
`
`The engine bus masters both it’s commands and parameters from either framebuffer or host
`which allows the CPU to do the minimum amount of work, increasing system throughput and
`supporting the use of Write Combining.»
`-
`
`1.5
`
`3D Graphics Engine
`
`KYRO uses the PowerVR Series 3 3D core to provide the huge performance and advanced
`features. required by tomorrow's 3D applications. The ‘engine uses twin high performance
`texturing pipelines.
`
`The 3D engine is a display list renderer which takes a whole scene of data to be rendered,
`partitions the data into screen tiles, performs hidden surface removal (without the need of an
`external Z—buffer) and performs deferred texturing on the resultant visible pixels. '
`
`Performance is ensured by the inclusion of complete hardware set—up of both triangle and
`texturing/shading parameters, the scene parameters being stored in host memory and bus
`«mastered for maximum performance.
`
`The chip supports Z-buffer—|ess hidden surface removal, RGB gouraud shading, perspective
`correct texture mapping, alpha blending and advanced texture filtering including bilinear,
`trilinear and anisotropic filtering as well as full scene anti-aliasing
`
`1.6 Graphics Output
`
`The graphics pixel pipeline incorporates color space conversion, overlay support, scaling
`and loadable LUT usable in all color depths to enable color management. DPMS and
`DDC2Bi are also supported.
`
`1.7 Digital Port
`
`Support for TV or LCD output in KYRO is provided by a 12—bit multiplexed RGB Port. This
`can be connected to an external digital TV encoders including the Conexant Bt868/9 or
`Chrontel CH7003/4, or to a digital flat panel transmitter using the Silicon image PanelLink
`Sil154. The port allows operation up to 1280x1024 60Hz, and supports both 18bpp and
`24bpp modes.
`
`The digital port can act in either master or slave mode. In master mode, the” chip generates
`DAC clock, HSYNC, and VSYNC and in slave mode the production of pixels is synchronized
`to an externally generated DAC clock, HSYNC, and VSYNC.
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`KYRO
`
`F'RELiMiNARY DATA
`
`Data is multiplexed onto the 12-bit port DVA__D[11:0] in the order shown below:
`
`
` NormalMode
`
`
`Rising Edge
`
`Falling Edge
`
`Bt868/9Modes
`
`Rising Edge
`
`Falling Edge
`
`
`1
`R7
`
`
`
`
`
`R5
`
`R4
`
`R3
`
`R1
`
`R0
`
`or
`
`B7
`
`B6
`
`
`
`G7
` :
`B4
`G6
`’
`G5
`B3 H
`R2
`
`A
`
`R7
`R6
`
`R5
`
`R4
`
`R3
`
`R1
`
`R0
`
`G7
`
`G6
`
`G5
`
`GO
`
`B7
`
`B B
`
`5
`B4
`B3
`
`B2
`
`B1
`
`B0
`
`
`
`
`
`G4
`
`DVA_D8
`
`DVA_D7
`
`DVA_D6
`
`DVA_D3
`
`DVA__D2
`
`DVA_D1
`
`DVA__D0
`
`
`
`
`
`1.8 Video Port
`
`The video interface allows capture of video data, including support for cropping, VB! capture,
`bus mastered data capture and image decimation.
`
`1.9 BIOS
`
`The BIOS interface is shared with the Frame Buffer Memory pins.
`
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`
`PRELIMINARY DAT/-\
`
`KYRO
`
`
`
`Not Connected
`
`Not Connected
`
`PAL/NTSC
`Resolutions Only
`
`2 Mode Support
`
`2.‘! Supported Modes
`
`The KYRO supports the following three display modes:
`
`Display Modes
`
`
`
`Connected Devices
`
`
`CRT Monitor
` Digital Flat Panel
`
`
` Not Connected
`All Graphics
`
`
`Same as DFP
`
`Maximum of
`1280x1024 at 6OHz
`
`
`
`
`Same as TV
`
`Not Connected -
`
`2.2 Graphics Resolutions
`
`KYRO supports a fully programmable PLL to allow a full range of resolutions and refresh «
`rates to be supported:
`
`Resolution
`
`up to 16.7 million
`
`up to 16.7 million
`
`1920x1440
`
`1920x1280
`
`1600x1200
`
`1280x1024
`
`1152x864
`1 024x768
`
`800x600
`
`640x480
`
`VGA Modes
`0,1,2,3,4,5,6,7,0Dh, 0Eh, 0Fh,
`
`10h,11h,12h,13h
`
`up to 16.7 million
`
`up to 85Hz
`
`up to 16.7 million
`
`up to 12OHz
`
`up to 16.7 million
`
`up to 1201-12
`
`up to 16.7 million
`
`up to 12OHz
`
`up to 16.7 million
`
`. up to 12OHz
`
`up to 16.7 million
`
`up to 12OHz
`
`£y,'
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`PRELIMINARY DATA
`
`KYRO
`
`Mode Support
`
`2.3 Digital Flat Panel Mode
`
`The digital port may be programmed at refresh rates to match the requirements of the
`attached LCD device to a maximum of 1280x1024 at 60Hz (normal blanking). Lower
`resolutions will be centered in the screen.
`
`2.4
`
`TV Mode
`
`All PAL/NTSC TV formats are supported. When connected to TV, the Digital Flat Panel
`cannot be used. However the CRT Monitor can simultaneously display the same resolution
`(mirror) as the TV Mode.
`‘
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`PRELIMINARY DATA
`
`KYRO
`
`3 Mechanica|IPackage Specifications
`
`3.1 Thermal Specification
`
`9 Thermal resistance: OJ/A = 15°CNV
`
`3.2 Material Data
`
`Standard BOM for BGA27 sq malta.
`
`BT resin
`
`IBIDEN
`
`_Giue
`Resin
`
`Bails
`
`Wire
`
`abiebond 8390
`Nitto HC100HF
`
`Sn/Pb, 30 mils
`
`gold, 1.2 mils
`
`3.2.1 Package Dimensions
`
`Dimensions
`
`Drawing (mm)
`
`Drawing (inch)
`
`Controlling Dimension: Millimeters, Drawing BGA27x27 finished 14090202—O04.
`Reference Document: JEDEC M0151.
`
`[ff
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`‘
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`_
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`PRELIMINARY DATA
`
`KYRO
`
`Mechanical/Package Specifications
`
`400 Pin Plastic Ball Grid Array Package dimension reference.
`
`if
`
`22A.2993»
`
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`
`
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`
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`
`OOOOOOOOOOOOOOOOOOOO
`
`OOOOOOOOOOOOOOOOOOOO
`
`OOOOOOOOOOOOOOOOOOOO
`
`OOOOOOOOOOOOOOOOOOOO
`
`OOOOOOOOOOOOOOOOOOOO
`
`OOOOOOOOOOOOOOOOOOOO
`
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`
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`
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`
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`
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`
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`
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`
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`
`I
`~<£<u:—«»'vaz:r—><f~:: 0-1~.mc:nco>
`
`10/12
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`111..
`
`30>Bx$930Bxfixwm\GoSn
`
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`
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`
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`
`~3..:m:3a:a;_:owmumm»uM.
`
`
`
`
`
`
`
`

`
`PRELIMINARY DATA
`
`KYRO
`
`
`7133766
`
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`
`PRELIMINARY DATA
`
`KYRO
`
`MechanicalIPackage Specifications
`
`This publication contains proprietary information of the STMicroelectronics Group. This publication is not to be copied
`in whole or part.
`-
`
`information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility
`for the consequences of use of such information nor for any infringement of patents or other rights of third parties which
`may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
`STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication
`supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use
`as critical components in life support devices or systems without express written approval of STMicroelectronics.
`
`Specifications mentioned in this publication are subject to change without notice.
`
`517®
`
`The ST logo is a registered trademark of STMicroelectronics
`
`
`
`KYRO is a trademark of STMicroelectronics
`
`
`
`PowerVR is a trademark of Imagination Technologies Group plc
`
`© 2000 STMicroelectronics - All Rights Reserved
`© 2000 imagination Technologies Group plc
`
`STMicroelectronics GROUP OF COMPANIES
`Australia - Brazil - China — Finland - France ~ Germany v Hong Kong - India - Italy — Japan — Malaysia ~ Malta - Morocco
`- Singapore — Spain — Sweden — Switzerland - United Kingdom — U.S.A.
`
`http://www.st.com
`
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