United States Patent 119]
`Yew et a].
`
`USOO58
`01094A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,801,094
`Sep. 1, 1998
`
`[54] DUAL DAMASCENE PROCESS
`
`FOREIGN PATENT DOCUMENTS
`
`Inventors:
`
`Yew,
`Meng-Chang Liu, Chia-‘?; Water
`Lur; Shih-Wei Sun, both of Taipei, all
`°f Taiwan
`
`................................... ..
`Primary Examiner-T. N. Quach
`Attome); Agent, or Firm-Rabin & Champagne. P.C.
`[57]
`ABSTRACT
`
`Assignec: United Micf‘od?ctmnics Corporation,
`HSm-ChU Clty, Taiwan
`
`App]. No.: 873,500
`_
`_
`F?cd'
`
`Jun’ 12’ 1997
`.
`.
`Related U‘S' Apphmtmn Dam
`.
`.
`.
`.
`Provisional application No' 60,038’872’ Feb’ 28’ [990'
`Int. Cl. 6
`H01L 21/28
`U.S. Cl.
`438/624; 438/633; 438/640;
`438fl40
`438/622, 624,
`Field of Search
`433/626, 633, 634, 540, 492, 439, 740
`
`[73]
`
`[21]
`[22]
`
`[60]
`[5 1]
`[52]
`
`[5 8]
`
`[56]
`
`A dual damascene process forms a two level metal inter
`connect structure by ?rst providing a inter-layer oxide over a
`device structure and covering the interlevel oxide layer with
`an etch stop layer. The etch stop layer is patterned to form
`openings corresponding to the pattern of the interconnects
`that are to be formed in the ?rst level of the two level
`interconnect structure. After the etch stop layer is patterned,
`an intermetal oxide layer is provided over the etch stop layer.
`Because the etch stop layer is relatively thin, the topography
`formed on the surface of the intermetal oxide layer is
`relatively small. A photoresist mask is then provided over
`the intermetal oxide layer with openings in the mask expos
`ing portions of the intermetal oxide layer in the pattern of the
`Wiring 1111cs to be Provided in the second level of the
`interconnect structure. The inter-metal oxide layer is etched
`and the etching process continues to form openings in the
`interlayer oxide where the interlayer oxide is exposed by the
`openings in the etch stop layer. Thus, in a single etching step,
`the openings for both the second level wiring lines and the
`?rst lcvd imdwnnws m de?nesi M991 is then dcposiwd
`438/624
`43mm over the structm‘e and excess metal is removed by chemical
`438/634
`mechanical polishing to de?ne the two level interconnect
`438/640
`structure,
`438/633
`438/633
`
`12 Claims, 7 Drawing Sheets
`
`References Cited
`
`U'S' PATENT DOCUMENTS
`?Jl983 Bohr
`4,372,034
`4,560,034 12/1985 Bnkhman et a]. ..
`4,789,648 12/1988 Chow et a1.
`5,246,882
`9/1993 Hartmann ....
`5,466,639 11/1995 Ireland
`5,635,423
`6/1997 Huang et al.
`
`76
`i
`/f/
`
`/
`
`5a
`
`f 54
`
`54
`
`76
`1
`
`/78
`
`/
`
`/
`
`_
`
`_5_§
`52
`
`2Q
`
`Petitioner Nanya Technology Corp. - Ex. 1015, p. 1
`
`

`
`U.S. Patent
`
`Sep. 1, 1998
`
`Sheet 1 of 7
`
`5,801,094
`
`FIG. 1
`Prior Art
`
`A IS
`
`1
`
`A
`
`FIG. 2
`"
`K
`Prior Art U
`
`'1'; \\ \
`
`FIG. 3
`Prior Art
`
`Petitioner Nanya Technology Corp. - Ex. 1015, p. 2
`
`

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`US. Patent
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`Sep. 1, 1998
`
`Sheet 2 of 7
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`5,801,094
`
`FIG. 4
`Prior Art
`
`Var/M; 18
`
`10
`
`20
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`16
`
`2‘0
`
`FIG. 5
`Prior Art
`
`r
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`/
`
`<2 /;
`
`/
`
`1Q
`
`20
`
`22
`
`FIG. 6
`Prior Art
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`/ / /
`Q //
`
`Petitioner Nanya Technology Corp. - Ex. 1015, p. 3
`
`

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`US. Patent
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`Sep. 1, 1998
`
`Sheet 3 of 7
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`5,801,094
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`20
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`1 6
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`20
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`‘a M r i
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`/
`/
`
`Prior Art
`
`_
`
`FIG. 8
`Prior An‘
`
`FIG. 9
`Prior Art
`
`FIG. 10
`Prior An‘
`
`32
`
`I
`
`\ 12
`1;
`
`12
`
`1 1_2
`1
`
`f 30
`
`of 30
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`}
`
`Petitioner Nanya Technology Corp. - Ex. 1015, p. 4
`
`

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`U.S. Patent
`
`Sep. 1, 1993
`
`Sheet 4 of 7
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`5,801,094
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`34
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`38 /
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`34
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`38 /
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`
`
`FIG. 1 1
`
`Prior An‘
`
`FIG. 12
`
`Prior An‘
`
`FIG. 13
`
`Prior An‘
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`Petitioner Nanya Technology Corp. - Ex. 1015, p. 5
`
`Petitioner Nanya Technology Corp. - Ex. 1015, p. 5
`
`

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`US. Patent
`
`Sep. 1, 1998
`
`5,801,094
`
`Sheet 5 of 7
`46
`48
`4l6
`t
`/
`38
`FIG. 14 \E /% /y/::§:
`
`Prior An‘
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`2
`
`/
`
`FIG. 16
`
`(i2
`
`Petitioner Nanya Technology Corp. - Ex. 1015, p. 6
`
`

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`US. Patent
`
`Sep. 1, 1998
`
`Sheet 6 of 7
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`5,801,094
`
`FIG. 17
`
`54
`5
`
`,
`
`56
`,? L
`\52
`_5_Q
`
`56
`
`FIG. 18
`
`‘
`
`62 72
`
`64
`
`68
`
`66 70 62
`
`FIG. 19 \ _
`
`~f54
`
`Petitioner Nanya Technology Corp. - Ex. 1015, p. 7
`
`

`
`US. Patent
`
`Sep. 1, 1998
`
`Sheet 7 0f 7
`
`5,801,094
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`74
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`68
`
`\__/~ 58
`
`FIG. 20
`
`54
`
`54
`
`FIG. 21
`
`58
`
`Petitioner Nanya Technology Corp. - Ex. 1015, p. 8
`
`

`
`1
`DUAL DAMASCENE PROCESS
`
`5,801,094
`
`This application claims priority from provisional patent
`application Ser. No. 60/038,872, ?led on Feb. 28, 1997.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to the formation of wiring
`structures in integrated circuit devices. More particularly,
`the present invention relates to the formation of vias. inter
`connect metallization and wiring lines using a dual dama
`scene process.
`2. Description of the Related Art
`Many highly integrated semiconductor circuits utilize
`multilevel wiring line structures for interconneaing regions
`within devices and for interconnecting one or more devices
`within the integrated circuits. In forming such structures, it
`is conventional to provide ?rst or lower level wiring lines or
`interconnect structures and men to form a second level
`wiring line in contact with the ?rst level wiring lines or
`interconnect structures. A ?rst level interconnect might be
`formed in contact with a doped region within the substrate
`of an integrated circuit device. Alternately, a ?rst level
`interconnect might be formed to a polysilicon or metal
`wiring line that is in contact with one or more device
`structures in or on the substrate of the integrated circuit
`device. One or more interconnections are typically formed
`between the ?rst level wiring line or interconnect and othm'
`portions of the integrated circuit device or to structures
`external to the integrated circuit device. This is
`accomplished, in part, through the second level of wiring
`lines.
`One conventional strategy for forming a two level wiring
`structure is illustrated in FIGS. 1-7. Referring ?rst to FIG.
`1, a two level interconnect structm'e is formed ova‘ a
`substrate 10 in which the device structures of an integrated
`circuit have been formed. Conventionally, the substrate 10
`includes sn'urxures such as MOSFETs or bipolar transistors
`and doped contact regions that are to be connected to othe
`portions of the integrated circuit or to I/O terminals provided
`for the
`circuit. The surface of the substrate 10 may
`be the surface of a silicon device structure, including one or
`more doped regions, or the surface of substrate 10 may be
`an insulating layer. Typically, if the surface of the substrate
`10 is an insulating layer, the layer will be over 1,000 A in
`thickness and will include vertical interconnects ?lled with
`conductors connected to devices in the substrate. An oxide
`layer 12 is typically deposited over me substrate 10 by
`chemical vapor deposition (CVD) from a TEOS source gas
`to a thiclmess of 4,000-6,000 A or more as an
`step in
`the process of forming the two level interconnect structure.
`The positions of the ?rst level interconnect structures are
`de?ned by a conventional photclithog'aphy process which
`forms openings 14 through the oxide layer 12 (FIG. 2) where
`the ?rst level interconnects will be formed. Generally, the
`openings 14 expose all or portions of conductors or doped
`regions in the substrate to which interconnects are formed.
`The openings 14 are ?lled with a metal interconnect 16 that
`might, for example, consist of a thin “glue” or adhesion layer
`over the inner surface of the contact opening 14 and over the
`exposed surface of the substrate 10. Suitable adhesion layers
`include titanium nitride and other conductive materials
`incorporating refractory metals. The reminder of the open
`ing 14 is ?lled with a metal such as tungsten to form the
`interconnect 16. The tungsten portion of the interconnea
`might be formed by CVD or by selective CVD, followed by
`
`10
`
`15
`
`35
`
`40
`
`55
`
`2
`an etchback or polishing process. The resulting structure is
`shown in FIG. 3.
`Referring now to FIG. 4, a layer of metal 18 is deposited
`to a thickness appropriate for second level wiring lines over
`the surface of the oxide layer 12 and over the metal plug 16.
`The metal layer 18 will be patterned into the second level
`wiring lines and might be a single layer of aluminum or layer
`18 might be a multilayer wiring structure including refrac
`tory metals or compounds including refractory metals, along
`with other less expensive metals. The second level wiring
`lines 210 are de?ned in a conventional photolithography
`process by providing a layer of photoresist over the metal
`layer 18, exposing the photoresist through a mask and
`removing portions of the exposed photoresist layer to form
`a photoresist etch mask. The portions of the metal layer 18
`exposed by openings in the photoresist mask are then
`removed by etching and the photoresist mask is removed by
`ashing to form the structure shown in FIG. 5. After the two
`level interconnect structure shown in FIG. 5 is formed, it is
`necessary to provide an interrnetal dielectric (IMD) layer
`between the second level wiring lines and covering the
`second level wiring lines to accommodate further processing
`of the integrated circuit device. The interrnetal dielectric
`layer might consist of one or more layers of oxide deposited
`by plasma enhanced chemical vapor deposition (PECVD) or
`other CVD processes. The intermetal dielectric layer 22
`formed in this manner generally has an uneven surface
`topography, as illustrated in FIG. 6. It is thus necessary to
`planan'ze the interrnetal dielectric layer 22, using for
`example chemical mechanical polishing (CMP), to form a
`planarized intermetal dielectric laya 24 as shown in FIG. 7.
`The method used to form the two level interconnect
`structure of FIG. 7 has a variety of disadvantages. For those
`future applications which use copper within the conductors
`or wiring lines, etching of the copper metal is very di?icult
`since appropriate etching chemicals and techniques have not
`yet been identi?ed. It is therefore desirable to utilize a
`method of forming wiring lines that does not rely on
`a metal layer in a chemical etching process.
`Reduced device dimensions also introduce di?iculties into
`the described wiring line formation method. Depositing
`metals into openings in dielectric layers and depositing
`dielectric materials into relatively narrow openings between
`metal lines are di?icult processes that are subject to void
`formation and the trapping of impurities. This is particularly
`hue as interconnects and wiring lines are made smaller and
`the spacing between wiring lines is made narrower. As such,
`the process of forming the FIG. 7 structure exhibits a fairly
`high rate of defect formation which is expected to increase
`for smaller design rules. Because the process of FIGS. 1-7
`requires that spaces between wiring lines he ?lled by depo
`sition processes, the process of FIGS. 1-7 is ill suited to
`further reductions in the design rules used in the manufac
`ture of the device. In addition, providing the necessary
`planar surface on the intermetal dielectric layer after
`completion of the two level interconnect structure requires
`additional processing steps. It is desirable whenever possible
`to reduce the number of processing steps required to form a
`device because reducing the numbm‘ of processing steps
`shortens the time required to produce the device and because
`eliminating processing steps improves yields and so reduces
`costs. Because of these factors, other methods of making
`multilevel interconnect structures have been investigated.
`One alternative to the conventional interconnect forma
`tion process is the so called dual damascene process. Dual
`damascene processes are more immediately scaleable to
`smaller design rules and most dual damascene processes
`
`Petitioner Nanya Technology Corp. - Ex. 1015, p. 9
`
`

`
`5,801,094
`
`3
`naturally produce a planan'zed ?nal surface over the inter
`connect structure. Accordingly, a surface that is appropriate
`for further processing steps can be obtained using the dual
`damascene process in fewer process steps than in the method
`illustrated in FIGS. 1-7. Aspects of a dual damascene
`process are illustrated in FIGS. 8-14. As with the more
`conventional interconnect process illustrated in FIGS. l-7,
`the dual damascene process begins with deposition of an
`oxide layer 12 over the substrate 10, as illustrated in FIG. 8.
`A relatively thin silicon nitride etch stop layer 30 is depos
`ited over the oxide layer 12 (FIG. 9) for use in a subsequent
`etching step. As shown in FIG. 10, a layer of interrnetal
`dielectric 32 is deposited on the etch stop layer 30. Typically,
`the intermetal dielectric material is chosen to be silicon
`oxide so that the underlying silicon nitride layer 32 is an
`etfective etch stop when openings for second level intercon
`nects are provided in the oxide intermetal oxide layer 32.
`The thickness of the intermetal oxide layer 32 is chosen to
`be that appropriate for the second level metal wiring lines,
`typically 4,000-6,000 A or more.
`A saies of photolithography steps are performed to ?rst
`de?ne the pattern of the second level wiring lines and then
`to de?ne the patch of the interconnects within the ?rst level
`of the interconnect structure. A mask is formed on the
`intermetal oxide layer 32 where the mask includes a pattern
`of openings that correspond to the pattern of wiring lines
`desired for the second level wiring lines. Openings 34 are
`then formed in the intermetal oxide layer 32 by etching
`through the openings in the photoresist mask. The etching
`step proceeds ?rst through the intermetal oxide layer to
`leave remaining portions 36 of the intermetal oxide layer
`between the openings 34. This ?rst etching steps stops on the
`silicon nitride layer 30, and then etching is performed
`aligned with the openings 34 to etch through the silicon
`nitride layer 30, leaving remaining portions of the silicon
`nitride layer 38 on either side of the openings 34. The
`photoresist mask is then removed by ashing, producing the
`structure illustrated in FIG. 11. It is generally necessary for
`the width of the openings 34 in the patterned inta'metal
`oxide layer 36 to be greater than the lithography resolution
`limit because further photolithography steps are necessary to
`de?ne the interconnects of the ?rst level. Forming the
`openings 34 wider than the resolution limit provides greater
`process latitude for the steps used to form the ?rst level
`interconnects.
`Referring now to FIG. 12, a photoresist mask 40 is formed
`over the device of FIG. 11 by conventional photolithogra
`phy. Openings 42 are provided in the mask 40 that expose
`selected portions of the ?rst oxide layer 12 lying within the
`openings 34. Etching is performed on the ?rst oxide layer 12
`exposed within the openings 42 in the photoresist mask 40
`to de?ne the pattern of interconnects that make up the ?rst
`level of the interconnect structure. The photoresist mask 40
`is then removed by ashing. Next, a layer of metal 44 is
`deposited over the device to ?ll the openings in the inter
`metal oxide layer 36 and to ?ll the openings in the ?rst oxide
`layer 12. As illustrated in FIG. 13, it is conventional to
`over?ll the openings 34 in the inter-metal oxide layer 36 to
`ensure that the openings in both the intermetal oxide 36 and
`the ?rst oxide layer 12 are completely ?lled. The excess
`metal is then removed, typically in a CMP process, to
`provide the second level metal wiring lines 46 and ?rst level
`interconnects 48 of the two level interconnect structure
`shown in FIG. 14. As is illustrated in FIG. 14, the result of
`the ?nal CMP step provides a planarized surface which is
`well suited to further processing steps.
`The dual damascene process illustrated in FIGS. 8-14
`provides several advantages over the conventional process
`
`4
`illustrated in FIGS. l-7. The process illustrated in FIGS.
`8-14, however, is very demanding from a process technol
`ogy point of view. It is therefore desirable to develop a dual
`damascene process that has wider process latitude and is
`more readily adapted to a high volume manufacturing pro
`cess.
`
`SUMMARY OF THE PREFERRED
`EMBODIMENTS
`
`In accordance with one aspect of the present invention, an
`integrated circuit including ?rst level and second level
`condudor structures are formed on a substrate incorporating
`one or more integrated circuit devices. First an interlayer
`dielectric layer and then an etch stop layer are provided over
`the substrate. The etch stop layer is patterned to de?ne
`openings in the patterned etch stop layer corresponding to
`positions where ?rst level conductor structures are to be
`formed.
`An intermetal dieledric layer is then provided over the
`patterned etch stop layer. A second level mask is formed
`over the intermetal dielectric layer having openings corre
`sponding to positions where second level conductor struc
`tures are to be formed. The method continues by etching
`through the openings in the second level mask to form
`second level conductor openings in the intermetal dielectric
`layer and etching through the openings in the patterned etch
`stop layer to form ?rst level conductor structures in the
`interlayer dielectric layer. Metal is deposited into the second
`level conductor openings and into the ?rst level conductor
`structures.
`
`35
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIGS. 1-'! illustrate a conventional process for forming a
`two level interconnect structure.
`FIGS. 8-14 illustrate aspects of a dual damascene process
`for forming a two level intaconnect structure.
`FIGS. 15-21 illustrate aspects of a dual damascene pro
`cess in accordance with preferred embodiments of the
`present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`The dual damascene process illustrated in FIGS. 8-14
`requires formation of a thick photoresist layer 40 over the
`uneven topography of the FIG. 11 structure. Accordingly, it
`is necessary to have a long depth of focus to expose the
`entire thickness of the photoresist mask 40 to provide well
`de?ned openings 42 in the photoresist mask. High resolution
`steppers of the type prefen'ed in modern manufacturing
`processes have great di?iculty in providing the depth of
`focus required for the formation of the photoresist mask
`illusu'ated in FIG. 12. This process step is even more di?icult
`when performed over the uneven surface topography typi
`cally present above an integrated circuit device. Preferred
`embodiments of the present invention avoid the necessity of
`such a thick photoresist mask, and the associated require
`ment for a long depth of focus photolithography process, by
`patta'ning the etch stop layer of the conventional dual
`damascene process prior to depositing the intermetal oxide
`layer. Thus, preferred embodiments of the present invention
`form photoresist masks over far more planar structures than
`those illustrated in FIG. 11 of the conventional dual dama
`scene process. Photoresist masks having a more uniform
`thickness can then be provided and the mask exposure step
`canbeperformedwithasmallerdepthoffocus,asis
`preferred to accommodate the highest resolution stoppers.
`
`45
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`55
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`Petitioner Nanya Technology Corp. - Ex. 1015, p. 10
`
`

`
`5
`In a particularly preferred embodiment of the present
`invention, a two level interconnect structure is formed by
`providing a ?rst oxide layer over the substrate and covering
`the ?rst oxide layer with an etch stop layer. The etch stop
`layer is patterned to form openings corresponding to the
`pattern of interconnects that are later to be formed in the ?rst
`level of the two level interconnect structure. After the etch
`stop layer is patterned, an intermetal oxide layer is provided
`over the etch stop layer, within which the second level
`wiring lines are to be formed. Because the etch stop layer is
`relatively thin, the topography formed on the surface of the
`intermetal oxide layer by the interconnect patterning within
`the etch stop layer is relatively small. A mask is then
`provided over the intermetal oxide layer with openings in
`the mask exposing portions of the intermetal oxide layer in
`the pattern of the wiring lines to be provided in the second
`level of the interconnect structure. The intm'metal oxide
`layer is etched and the etching process continues into the
`?rst oxide layer where the ?rst oxide laym' is exposed
`through the openings in the etch stop layer to form openings
`in the ?rst oxide layer corresponding to the openings in the
`etch stop layer. In effect, the etch stop layer acts as a hard
`mask for the process of etching the interconnect pattern into
`the ?rst oxide layer. Thus, in a single etching step, the
`openings for both the second level wiring lines and the ?rst
`level interconnects are de?ned. Metal is then deposited over
`the structure and excess metal is removed by, for example,
`polishing to de?ne the ?nal two level interconnect structure.
`Prefen‘ed embodiments of the present invention are now
`described with more particular reference to FIGS. 15-21.
`While the following description is made in terms of ?rst
`level interconnects and second level wiring lines, it is to be
`understood ?aat aspects of the present invention ?nd appli
`cation to the formation of contacts between two layu's of
`wiring lines and between nonadjacent layers of conductors.
`Accordingly, it is possible to use aspects of the present
`invention in forming interconnects between a ?rst level and
`a third or other level of a wiring structure. The interconnect
`formation method of the present invention is preferably
`begun after formation of an integrated circuit device within
`substrate 50. The interconnect fu'mation method begins by
`depositing an interlayer dielectric layer 52 over the surface
`of the substrate 50 (FIG. 15). The interlayer dielectric layer
`52 may be an oxide layer deposited to a thickness of seve'al
`thousand angstroms or more by a PECVD process, a low
`pressure chemical vapor deposition (LPCVD) process, or
`another dielectric deposition process. Any of these processes
`might use, for example, a TEOS source gas. Often, the
`surface of the substrate 50 will have an uneven topography
`corresponding to the device structures within the integrated
`circuit device. It is accordingly prefared that the surface of
`the interlayer dielectric layer 52 be planarized before the two
`level intu'connect structure is formed. Planarization may be
`accomplished in an etch back process, but is more preferably
`accomplished using CMP. The end thickness of the inter
`layer dielectric layer 52 is dictated by the topography of the
`underlying integrated circuit device and will thus vary from
`design to design. The height of the ?rst level interconnect
`formed through layer 52 will be dictated by whatever
`thickness is provided for the interlaya' dielectric 52.
`An etch stop layer 54 is deposited over the planarizcd
`surface of the interlayer dielectric layer 52 (FIG. 16). It is
`preferred that the material chosen for the etch stop layer be
`different from both the interlayer dielectric layer beneath the
`etch stop layer and the inter-metal dielectric layer formed
`over the etch stop layer. Typically, the interlayer dielectric
`layer 50 and the intermetal dielectric layer are bo?r preferred
`
`45
`
`50
`
`65
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`5,801,094
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`15
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`35
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`6
`to be oxides, so an appropriate choice for the etch stop layer
`54 is silicon nitride. Besides being sul?ciently different from
`silicon oxide to serve as an etch stop layer, silicon nitride has
`the further advantage of being an insulator which is desir
`able since the etch stop layer will generally be left in place
`in the ?nished interconnect structure and will extend
`between different wiring lines. The etch stop layer 54 is
`preferably made thin to minimize the impact of the etch stop
`layer on the surface topography of the device in later
`processing steps. 0n the other hand, the etch stop layer 54
`should be sul?ciently thick to function as an etch stop layer
`throughout the etching of both the intermetal dielectric and
`the interlayer dielectric layers. In addition, the etch stop
`layer should be su?iciently thick to act as a hard mask in the
`etching of interconnect openings in the interlayer dielectric
`layer 50. An appropriate silicon nitride etch stop layer 54
`might have a thickness of between about 200-1,500 A.
`The etch stop layer 54 is then patterned to provide
`openings in the etch stop layer 54 corresponding to the
`positions whm'e ?rst level interconnects are to be formed
`wi?rin the interlayer dielectric layer 50. Accordingly, a mask
`is formed over the silicon nitride layer 54 which provides
`appropriate openings which expose portions of the silicon
`nitride layer 54 where interconnects are to be formed, and
`then the silicon nitride etch stop layer 54 is etched to provide
`openings 56 which expose portions of the interlayer dielec
`tric layer 52. To minimize the impact of the openings 56
`through the etch stop layer 54 on the surface topography of
`the not yet formed intermetal dielectric layer, it is preferred
`that the etching process which forms the openings 56
`through the silicon nitride etch stop layer 54 stop on the
`underlying surface of the interlayer oxide layer 52.
`Preferably, no depression is formed at the surface of the
`interlayu' oxide layer 52 in the process of forming the
`openings 56. This and other etching steps performed on the
`dielectric and etch stop layers of the present invention an be
`advantageously pa-formed in an etching system such as the
`Lam Research Rainbow system. The Lam Research Rain
`bow system uses etchants derived from one or more source
`gases such as SF6 or 0J6 mixed with diiferent quantities of
`other gases such as H31‘ and He to adjust the selectivity of
`the etching process. In such a system, the selectivity of the
`etch process between silicon oxide and silicon nitride can be
`automatically adjusted over a wide range of selectivities.
`Thus, in the etching process used to etch the silicon nitride
`etch stop layer 54, the selectivity is adjusted to etch silicon
`nitride while not etching silicon oxide, prefa'ably to the
`greatest extent possible. Variations are possible, though
`presently undesired, because etching of the interlaya' silicon
`oxide layer 52 at this time will require a higher depth of
`focus in subsequent lithography processes. The mask used
`for patterning the silicon nitride etch stop by: 54 is then
`removed, forming the structure illustrated in FIG. 17.
`An intermetal dielectric layer 58 is then deposited ova
`the patterned etch stop layer 54 (FIG. 18). As discussed
`above, it is preferred that the intermetal dielectric layu' 58
`be formed of the same mataial as the inta'layer dielectric 52
`and of a material diffa'ent from the etch stop layer 54. As
`such, the intermetal dielectric layer 58 is preferably a laym
`of silicon oxide. The intermetal oxide layer 58 might be
`deposited through a CVD process from a TEOS precursor or
`SiH4 source gas to a thickness appropriate for second level
`wiring lines, since the thickness of the second level wiring
`lines will be determined by the thickness of the interrnetal
`oxide layer. For present device structures, second level
`wiring lines might be on the order of 4,000-8,000 A in
`thickness and so the inter-metal oxide layer 58 is deposited
`
`Petitioner Nanya Technology Corp. - Ex. 1015, p. 11
`
`

`
`5,801,094
`
`10
`
`35
`
`7
`to a thickness on the order of 4,000-8,000 A. Relatively
`small depressions 60 will be formed on the surface of the
`intermetal oxide layer 58 corresponding to the presence of
`the openings 56 in the etch stop layer 54. Because the depth
`of the depressions 60 will be much smaller than the topog
`raphy present in the conventional dual damascene process,
`such as that illustrated in FIG. 11, the depressions 60 will
`present a comparatively small problem for maintaining
`focus through a photoresist layer provided over the inter
`metal dielectric layer 58 in the photolithogaphy step used to
`de?ne the pattern for the second level wiring lines.
`Referring now to FIG. 19, a photoresist mask 62 is formed
`on the interrnetal oxide layer 58. The mask 62 has a pattern
`of openings corresponding to the pattern of second level
`wiring lines that are to be formed in the intermetal oxide
`layer 58. Some of the openings 64 in the photoresist mask
`62 are disposed over the openings 56 in the etch stop layer
`54 where ?rst level interconnects are to be formed beneath
`portions of the second level wiring lines. Others of the
`openings 66 in the photoresist mask 62 are formed over
`positions where second level wiring lines are to be formed
`but no ?rst level interconnects are to be formed. It may be
`desirable to form slightly wider openings 64 in the photo
`resist mask 62 over the openings 56 in the etch stop layu- 54.
`Such wider openings 64 in the photoresist mask 62 will form
`wider openings in the intermetal oxide layer 58, which can
`have several bene?ts in the manufactming process. First,
`alignment of the second level wiring lines with respect to the
`openings 56 in the etch stop layer, and thus the ?rst level
`interconnects, will be made easier. In addition, the resultant
`widu' openings in the intermetal oxide layer 58 will reduce
`?reaspectratiooftheholestobe?lledinthemexal
`deposition process, thu'eby making it easier to ?ll the holes
`in the process of forming the ?rst level interconnects.
`The intermetal oxide layer 58 is then etched through the
`openings 64, 66 in the photoresist mask 62 using a process
`that is highly selective to oxide, that is, the etching process
`should readily etch oxide but not etch the material of the etch
`stop layer 54, (silicon nitride), to the extent possible. An
`appropriately selective etching process may, for example, be
`accomplished using an etchant derived from a mixture of
`source gases including C4FJCO or CF‘ mixed with CHF3,
`Ar or N 2. Thus, the etching process removes portions of the
`intermetal oxide laya' 58 everywhere that it is exposed by
`the photoresist mask to de?ne openings within the intu'metal
`dielectric layer 58 in which the second level wiring lines are
`to be formed. The etching process stops on the silicon nitride
`etch stop layer 54 within those pations of the photoresist
`mask openings 66 that lie over a solid etch stop layer 54.
`Within those photoresist mask openings 64 that lie over
`openings 56 in the silicon nitride etch stop layer 54, the
`etching process continues into the inter-layer dielectric oxide
`layer52toformopenings 68alignedwiththeetchstopmask
`openings 56, with the etch stop layer 54 acting partially as
`a hard mask for this process. The openings in the interlayer
`dielectric oxide layer 52 will later be ?lled with metal to
`provide the ?rst level intu'connects for the device.
`The etching process used in forming the second level
`wiring lines and the ?rst level interconnects is highly
`selective to oxide while substantially not etching the silicon
`nitride etch stop layer 54. Despite the high level of
`selectivity, the etching process used to form the openings in
`the interlayer oxide layer 52 still etches exposed surfaces of
`the silicon nitride etch stop layer 54 to a small extent Thus,
`the surface of the etch stop layer 54 exposed may be etched
`to form slight depressions 70 within the openings 66 in the
`photoresist mask that are not over openings 56 in the etch
`
`8
`stop layer. The edges of the openings 56 in the etch stop
`layer 54 are also etched slightly in this process, providing a
`tapered edge 72 to the openings in the etch stop layer.
`Formation of such a tapered edge 72 to the openings in the
`etch stop layer 54 is preferred, because such a tapered edge
`enhances the ability to ?ll the openings 68 within the
`interlayer dielectric layer 52. The presence of a tapered edge
`72 reduces the propensity to form an overhang over the
`opening 68 in the interlayer dielectric layer 52. As such, if
`the process used to etch the intermetal oxide layer 58 and the
`interlayer oxide layer 52 do not form a taper 72 along the
`edge of the openings 56 in the etch stop layer 54, it may be
`desirable to include an isotropic etching process on the
`edges of the openings in the etch stop layer 54 aftm' the
`intermetal dielectric layer 52 is etched to form a tapered
`sidewall on the openings in the etch stop layer.
`After the FIG. 19 structure is complete, the photoresist
`mask 62 is stripped by ashing and the structure is ready for
`the deposition of a metal layer 74 to ?ll the openings in the
`intermetal dielectric layer 58 and the intu'layer dielectric
`layer 52, as illustrated in FIG. 20. The metal layer 74 may
`be a si